1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) 4 * 5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren 6 * 7 * This driver is inspired by: 8 * pinctrl-nomadik.c, please see original file for copyright information 9 * pinctrl-tegra.c, please see original file for copyright information 10 */ 11 12 #include <linux/bitmap.h> 13 #include <linux/bug.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/err.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/io.h> 19 #include <linux/irq.h> 20 #include <linux/irqdesc.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/module.h> 24 #include <linux/of_address.h> 25 #include <linux/of.h> 26 #include <linux/of_irq.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/pinctrl/machine.h> 29 #include <linux/pinctrl/pinconf.h> 30 #include <linux/pinctrl/pinctrl.h> 31 #include <linux/pinctrl/pinmux.h> 32 #include <linux/pinctrl/pinconf-generic.h> 33 #include <linux/platform_device.h> 34 #include <linux/seq_file.h> 35 #include <linux/slab.h> 36 #include <linux/spinlock.h> 37 #include <linux/types.h> 38 #include <dt-bindings/pinctrl/bcm2835.h> 39 40 #define MODULE_NAME "pinctrl-bcm2835" 41 #define BCM2835_NUM_GPIOS 54 42 #define BCM2711_NUM_GPIOS 58 43 #define BCM2835_NUM_BANKS 2 44 #define BCM2835_NUM_IRQS 3 45 46 /* GPIO register offsets */ 47 #define GPFSEL0 0x0 /* Function Select */ 48 #define GPSET0 0x1c /* Pin Output Set */ 49 #define GPCLR0 0x28 /* Pin Output Clear */ 50 #define GPLEV0 0x34 /* Pin Level */ 51 #define GPEDS0 0x40 /* Pin Event Detect Status */ 52 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */ 53 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */ 54 #define GPHEN0 0x64 /* Pin High Detect Enable */ 55 #define GPLEN0 0x70 /* Pin Low Detect Enable */ 56 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */ 57 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ 58 #define GPPUD 0x94 /* Pin Pull-up/down Enable */ 59 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ 60 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */ 61 62 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) 63 #define FSEL_SHIFT(p) (((p) % 10) * 3) 64 #define GPIO_REG_OFFSET(p) ((p) / 32) 65 #define GPIO_REG_SHIFT(p) ((p) % 32) 66 67 #define PUD_2711_MASK 0x3 68 #define PUD_2711_REG_OFFSET(p) ((p) / 16) 69 #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2) 70 71 /* argument: bcm2835_pinconf_pull */ 72 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1) 73 74 #define BCM2711_PULL_NONE 0x0 75 #define BCM2711_PULL_UP 0x1 76 #define BCM2711_PULL_DOWN 0x2 77 78 struct bcm2835_pinctrl { 79 struct device *dev; 80 void __iomem *base; 81 int *wake_irq; 82 83 /* note: locking assumes each bank will have its own unsigned long */ 84 unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; 85 unsigned int irq_type[BCM2711_NUM_GPIOS]; 86 87 struct pinctrl_dev *pctl_dev; 88 struct gpio_chip gpio_chip; 89 struct pinctrl_desc pctl_desc; 90 struct pinctrl_gpio_range gpio_range; 91 92 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS]; 93 /* Protect FSEL registers */ 94 spinlock_t fsel_lock; 95 }; 96 97 /* pins are just named GPIO0..GPIO53 */ 98 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) 99 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = { 100 BCM2835_GPIO_PIN(0), 101 BCM2835_GPIO_PIN(1), 102 BCM2835_GPIO_PIN(2), 103 BCM2835_GPIO_PIN(3), 104 BCM2835_GPIO_PIN(4), 105 BCM2835_GPIO_PIN(5), 106 BCM2835_GPIO_PIN(6), 107 BCM2835_GPIO_PIN(7), 108 BCM2835_GPIO_PIN(8), 109 BCM2835_GPIO_PIN(9), 110 BCM2835_GPIO_PIN(10), 111 BCM2835_GPIO_PIN(11), 112 BCM2835_GPIO_PIN(12), 113 BCM2835_GPIO_PIN(13), 114 BCM2835_GPIO_PIN(14), 115 BCM2835_GPIO_PIN(15), 116 BCM2835_GPIO_PIN(16), 117 BCM2835_GPIO_PIN(17), 118 BCM2835_GPIO_PIN(18), 119 BCM2835_GPIO_PIN(19), 120 BCM2835_GPIO_PIN(20), 121 BCM2835_GPIO_PIN(21), 122 BCM2835_GPIO_PIN(22), 123 BCM2835_GPIO_PIN(23), 124 BCM2835_GPIO_PIN(24), 125 BCM2835_GPIO_PIN(25), 126 BCM2835_GPIO_PIN(26), 127 BCM2835_GPIO_PIN(27), 128 BCM2835_GPIO_PIN(28), 129 BCM2835_GPIO_PIN(29), 130 BCM2835_GPIO_PIN(30), 131 BCM2835_GPIO_PIN(31), 132 BCM2835_GPIO_PIN(32), 133 BCM2835_GPIO_PIN(33), 134 BCM2835_GPIO_PIN(34), 135 BCM2835_GPIO_PIN(35), 136 BCM2835_GPIO_PIN(36), 137 BCM2835_GPIO_PIN(37), 138 BCM2835_GPIO_PIN(38), 139 BCM2835_GPIO_PIN(39), 140 BCM2835_GPIO_PIN(40), 141 BCM2835_GPIO_PIN(41), 142 BCM2835_GPIO_PIN(42), 143 BCM2835_GPIO_PIN(43), 144 BCM2835_GPIO_PIN(44), 145 BCM2835_GPIO_PIN(45), 146 BCM2835_GPIO_PIN(46), 147 BCM2835_GPIO_PIN(47), 148 BCM2835_GPIO_PIN(48), 149 BCM2835_GPIO_PIN(49), 150 BCM2835_GPIO_PIN(50), 151 BCM2835_GPIO_PIN(51), 152 BCM2835_GPIO_PIN(52), 153 BCM2835_GPIO_PIN(53), 154 BCM2835_GPIO_PIN(54), 155 BCM2835_GPIO_PIN(55), 156 BCM2835_GPIO_PIN(56), 157 BCM2835_GPIO_PIN(57), 158 }; 159 160 /* one pin per group */ 161 static const char * const bcm2835_gpio_groups[] = { 162 "gpio0", 163 "gpio1", 164 "gpio2", 165 "gpio3", 166 "gpio4", 167 "gpio5", 168 "gpio6", 169 "gpio7", 170 "gpio8", 171 "gpio9", 172 "gpio10", 173 "gpio11", 174 "gpio12", 175 "gpio13", 176 "gpio14", 177 "gpio15", 178 "gpio16", 179 "gpio17", 180 "gpio18", 181 "gpio19", 182 "gpio20", 183 "gpio21", 184 "gpio22", 185 "gpio23", 186 "gpio24", 187 "gpio25", 188 "gpio26", 189 "gpio27", 190 "gpio28", 191 "gpio29", 192 "gpio30", 193 "gpio31", 194 "gpio32", 195 "gpio33", 196 "gpio34", 197 "gpio35", 198 "gpio36", 199 "gpio37", 200 "gpio38", 201 "gpio39", 202 "gpio40", 203 "gpio41", 204 "gpio42", 205 "gpio43", 206 "gpio44", 207 "gpio45", 208 "gpio46", 209 "gpio47", 210 "gpio48", 211 "gpio49", 212 "gpio50", 213 "gpio51", 214 "gpio52", 215 "gpio53", 216 "gpio54", 217 "gpio55", 218 "gpio56", 219 "gpio57", 220 }; 221 222 enum bcm2835_fsel { 223 BCM2835_FSEL_COUNT = 8, 224 BCM2835_FSEL_MASK = 0x7, 225 }; 226 227 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = { 228 [BCM2835_FSEL_GPIO_IN] = "gpio_in", 229 [BCM2835_FSEL_GPIO_OUT] = "gpio_out", 230 [BCM2835_FSEL_ALT0] = "alt0", 231 [BCM2835_FSEL_ALT1] = "alt1", 232 [BCM2835_FSEL_ALT2] = "alt2", 233 [BCM2835_FSEL_ALT3] = "alt3", 234 [BCM2835_FSEL_ALT4] = "alt4", 235 [BCM2835_FSEL_ALT5] = "alt5", 236 }; 237 238 static const char * const irq_type_names[] = { 239 [IRQ_TYPE_NONE] = "none", 240 [IRQ_TYPE_EDGE_RISING] = "edge-rising", 241 [IRQ_TYPE_EDGE_FALLING] = "edge-falling", 242 [IRQ_TYPE_EDGE_BOTH] = "edge-both", 243 [IRQ_TYPE_LEVEL_HIGH] = "level-high", 244 [IRQ_TYPE_LEVEL_LOW] = "level-low", 245 }; 246 247 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) 248 { 249 return readl(pc->base + reg); 250 } 251 252 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, 253 u32 val) 254 { 255 writel(val, pc->base + reg); 256 } 257 258 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, 259 unsigned bit) 260 { 261 reg += GPIO_REG_OFFSET(bit) * 4; 262 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1; 263 } 264 265 /* note NOT a read/modify/write cycle */ 266 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc, 267 unsigned reg, unsigned bit) 268 { 269 reg += GPIO_REG_OFFSET(bit) * 4; 270 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); 271 } 272 273 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get( 274 struct bcm2835_pinctrl *pc, unsigned pin) 275 { 276 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 277 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 278 279 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, 280 bcm2835_functions[status]); 281 282 return status; 283 } 284 285 static inline void bcm2835_pinctrl_fsel_set( 286 struct bcm2835_pinctrl *pc, unsigned pin, 287 enum bcm2835_fsel fsel) 288 { 289 u32 val; 290 enum bcm2835_fsel cur; 291 unsigned long flags; 292 293 spin_lock_irqsave(&pc->fsel_lock, flags); 294 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 295 cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 296 297 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, 298 bcm2835_functions[cur]); 299 300 if (cur == fsel) 301 goto unlock; 302 303 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) { 304 /* always transition through GPIO_IN */ 305 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 306 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); 307 308 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin, 309 bcm2835_functions[BCM2835_FSEL_GPIO_IN]); 310 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 311 } 312 313 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 314 val |= fsel << FSEL_SHIFT(pin); 315 316 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin, 317 bcm2835_functions[fsel]); 318 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 319 320 unlock: 321 spin_unlock_irqrestore(&pc->fsel_lock, flags); 322 } 323 324 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 325 { 326 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 327 328 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 329 return 0; 330 } 331 332 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) 333 { 334 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 335 336 return bcm2835_gpio_get_bit(pc, GPLEV0, offset); 337 } 338 339 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 340 { 341 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 342 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 343 344 /* Alternative function doesn't clearly provide a direction */ 345 if (fsel > BCM2835_FSEL_GPIO_OUT) 346 return -EINVAL; 347 348 if (fsel == BCM2835_FSEL_GPIO_IN) 349 return GPIO_LINE_DIRECTION_IN; 350 351 return GPIO_LINE_DIRECTION_OUT; 352 } 353 354 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 355 { 356 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 357 358 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); 359 } 360 361 static int bcm2835_gpio_direction_output(struct gpio_chip *chip, 362 unsigned offset, int value) 363 { 364 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 365 366 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); 367 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT); 368 return 0; 369 } 370 371 static int bcm2835_add_pin_ranges_fallback(struct gpio_chip *gc) 372 { 373 struct device_node *np = dev_of_node(gc->parent); 374 struct pinctrl_dev *pctldev = of_pinctrl_get(np); 375 376 if (!pctldev) 377 return 0; 378 379 gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0, 380 gc->ngpio); 381 382 return 0; 383 } 384 385 static const struct gpio_chip bcm2835_gpio_chip = { 386 .label = MODULE_NAME, 387 .owner = THIS_MODULE, 388 .request = gpiochip_generic_request, 389 .free = gpiochip_generic_free, 390 .direction_input = bcm2835_gpio_direction_input, 391 .direction_output = bcm2835_gpio_direction_output, 392 .get_direction = bcm2835_gpio_get_direction, 393 .get = bcm2835_gpio_get, 394 .set = bcm2835_gpio_set, 395 .set_config = gpiochip_generic_config, 396 .base = -1, 397 .ngpio = BCM2835_NUM_GPIOS, 398 .can_sleep = false, 399 .add_pin_ranges = bcm2835_add_pin_ranges_fallback, 400 }; 401 402 static const struct gpio_chip bcm2711_gpio_chip = { 403 .label = "pinctrl-bcm2711", 404 .owner = THIS_MODULE, 405 .request = gpiochip_generic_request, 406 .free = gpiochip_generic_free, 407 .direction_input = bcm2835_gpio_direction_input, 408 .direction_output = bcm2835_gpio_direction_output, 409 .get_direction = bcm2835_gpio_get_direction, 410 .get = bcm2835_gpio_get, 411 .set = bcm2835_gpio_set, 412 .set_config = gpiochip_generic_config, 413 .base = -1, 414 .ngpio = BCM2711_NUM_GPIOS, 415 .can_sleep = false, 416 .add_pin_ranges = bcm2835_add_pin_ranges_fallback, 417 }; 418 419 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, 420 unsigned int bank, u32 mask) 421 { 422 unsigned long events; 423 unsigned offset; 424 unsigned gpio; 425 426 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); 427 events &= mask; 428 events &= pc->enabled_irq_map[bank]; 429 for_each_set_bit(offset, &events, 32) { 430 gpio = (32 * bank) + offset; 431 generic_handle_domain_irq(pc->gpio_chip.irq.domain, 432 gpio); 433 } 434 } 435 436 static void bcm2835_gpio_irq_handler(struct irq_desc *desc) 437 { 438 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 439 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 440 struct irq_chip *host_chip = irq_desc_get_chip(desc); 441 int irq = irq_desc_get_irq(desc); 442 int group = 0; 443 int i; 444 445 for (i = 0; i < BCM2835_NUM_IRQS; i++) { 446 if (chip->irq.parents[i] == irq) { 447 group = i; 448 break; 449 } 450 } 451 /* This should not happen, every IRQ has a bank */ 452 BUG_ON(i == BCM2835_NUM_IRQS); 453 454 chained_irq_enter(host_chip, desc); 455 456 switch (group) { 457 case 0: /* IRQ0 covers GPIOs 0-27 */ 458 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff); 459 break; 460 case 1: /* IRQ1 covers GPIOs 28-45 */ 461 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000); 462 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff); 463 break; 464 case 2: /* IRQ2 covers GPIOs 46-57 */ 465 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000); 466 break; 467 } 468 469 chained_irq_exit(host_chip, desc); 470 } 471 472 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id) 473 { 474 return IRQ_HANDLED; 475 } 476 477 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 478 unsigned reg, unsigned offset, bool enable) 479 { 480 u32 value; 481 reg += GPIO_REG_OFFSET(offset) * 4; 482 value = bcm2835_gpio_rd(pc, reg); 483 if (enable) 484 value |= BIT(GPIO_REG_SHIFT(offset)); 485 else 486 value &= ~(BIT(GPIO_REG_SHIFT(offset))); 487 bcm2835_gpio_wr(pc, reg, value); 488 } 489 490 /* fast path for IRQ handler */ 491 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 492 unsigned offset, bool enable) 493 { 494 switch (pc->irq_type[offset]) { 495 case IRQ_TYPE_EDGE_RISING: 496 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 497 break; 498 499 case IRQ_TYPE_EDGE_FALLING: 500 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 501 break; 502 503 case IRQ_TYPE_EDGE_BOTH: 504 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 505 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 506 break; 507 508 case IRQ_TYPE_LEVEL_HIGH: 509 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable); 510 break; 511 512 case IRQ_TYPE_LEVEL_LOW: 513 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable); 514 break; 515 } 516 } 517 518 static void bcm2835_gpio_irq_unmask(struct irq_data *data) 519 { 520 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 521 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 522 unsigned gpio = irqd_to_hwirq(data); 523 unsigned offset = GPIO_REG_SHIFT(gpio); 524 unsigned bank = GPIO_REG_OFFSET(gpio); 525 unsigned long flags; 526 527 gpiochip_enable_irq(chip, gpio); 528 529 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); 530 set_bit(offset, &pc->enabled_irq_map[bank]); 531 bcm2835_gpio_irq_config(pc, gpio, true); 532 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 533 } 534 535 static void bcm2835_gpio_irq_mask(struct irq_data *data) 536 { 537 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 538 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 539 unsigned gpio = irqd_to_hwirq(data); 540 unsigned offset = GPIO_REG_SHIFT(gpio); 541 unsigned bank = GPIO_REG_OFFSET(gpio); 542 unsigned long flags; 543 544 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); 545 bcm2835_gpio_irq_config(pc, gpio, false); 546 /* Clear events that were latched prior to clearing event sources */ 547 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 548 clear_bit(offset, &pc->enabled_irq_map[bank]); 549 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 550 551 gpiochip_disable_irq(chip, gpio); 552 } 553 554 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, 555 unsigned offset, unsigned int type) 556 { 557 switch (type) { 558 case IRQ_TYPE_NONE: 559 case IRQ_TYPE_EDGE_RISING: 560 case IRQ_TYPE_EDGE_FALLING: 561 case IRQ_TYPE_EDGE_BOTH: 562 case IRQ_TYPE_LEVEL_HIGH: 563 case IRQ_TYPE_LEVEL_LOW: 564 pc->irq_type[offset] = type; 565 break; 566 567 default: 568 return -EINVAL; 569 } 570 return 0; 571 } 572 573 /* slower path for reconfiguring IRQ type */ 574 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc, 575 unsigned offset, unsigned int type) 576 { 577 switch (type) { 578 case IRQ_TYPE_NONE: 579 if (pc->irq_type[offset] != type) { 580 bcm2835_gpio_irq_config(pc, offset, false); 581 pc->irq_type[offset] = type; 582 } 583 break; 584 585 case IRQ_TYPE_EDGE_RISING: 586 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 587 /* RISING already enabled, disable FALLING */ 588 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 589 bcm2835_gpio_irq_config(pc, offset, false); 590 pc->irq_type[offset] = type; 591 } else if (pc->irq_type[offset] != type) { 592 bcm2835_gpio_irq_config(pc, offset, false); 593 pc->irq_type[offset] = type; 594 bcm2835_gpio_irq_config(pc, offset, true); 595 } 596 break; 597 598 case IRQ_TYPE_EDGE_FALLING: 599 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 600 /* FALLING already enabled, disable RISING */ 601 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 602 bcm2835_gpio_irq_config(pc, offset, false); 603 pc->irq_type[offset] = type; 604 } else if (pc->irq_type[offset] != type) { 605 bcm2835_gpio_irq_config(pc, offset, false); 606 pc->irq_type[offset] = type; 607 bcm2835_gpio_irq_config(pc, offset, true); 608 } 609 break; 610 611 case IRQ_TYPE_EDGE_BOTH: 612 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) { 613 /* RISING already enabled, enable FALLING too */ 614 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 615 bcm2835_gpio_irq_config(pc, offset, true); 616 pc->irq_type[offset] = type; 617 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) { 618 /* FALLING already enabled, enable RISING too */ 619 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 620 bcm2835_gpio_irq_config(pc, offset, true); 621 pc->irq_type[offset] = type; 622 } else if (pc->irq_type[offset] != type) { 623 bcm2835_gpio_irq_config(pc, offset, false); 624 pc->irq_type[offset] = type; 625 bcm2835_gpio_irq_config(pc, offset, true); 626 } 627 break; 628 629 case IRQ_TYPE_LEVEL_HIGH: 630 case IRQ_TYPE_LEVEL_LOW: 631 if (pc->irq_type[offset] != type) { 632 bcm2835_gpio_irq_config(pc, offset, false); 633 pc->irq_type[offset] = type; 634 bcm2835_gpio_irq_config(pc, offset, true); 635 } 636 break; 637 638 default: 639 return -EINVAL; 640 } 641 return 0; 642 } 643 644 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) 645 { 646 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 647 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 648 unsigned gpio = irqd_to_hwirq(data); 649 unsigned offset = GPIO_REG_SHIFT(gpio); 650 unsigned bank = GPIO_REG_OFFSET(gpio); 651 unsigned long flags; 652 int ret; 653 654 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); 655 656 if (test_bit(offset, &pc->enabled_irq_map[bank])) 657 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type); 658 else 659 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); 660 661 if (type & IRQ_TYPE_EDGE_BOTH) 662 irq_set_handler_locked(data, handle_edge_irq); 663 else 664 irq_set_handler_locked(data, handle_level_irq); 665 666 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 667 668 return ret; 669 } 670 671 static void bcm2835_gpio_irq_ack(struct irq_data *data) 672 { 673 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 674 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 675 unsigned gpio = irqd_to_hwirq(data); 676 677 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 678 } 679 680 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on) 681 { 682 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 683 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 684 unsigned gpio = irqd_to_hwirq(data); 685 unsigned int irqgroup; 686 int ret = -EINVAL; 687 688 if (!pc->wake_irq) 689 return ret; 690 691 if (gpio <= 27) 692 irqgroup = 0; 693 else if (gpio >= 28 && gpio <= 45) 694 irqgroup = 1; 695 else if (gpio >= 46 && gpio <= 57) 696 irqgroup = 2; 697 else 698 return ret; 699 700 if (on) 701 ret = enable_irq_wake(pc->wake_irq[irqgroup]); 702 else 703 ret = disable_irq_wake(pc->wake_irq[irqgroup]); 704 705 return ret; 706 } 707 708 static const struct irq_chip bcm2835_gpio_irq_chip = { 709 .name = MODULE_NAME, 710 .irq_set_type = bcm2835_gpio_irq_set_type, 711 .irq_ack = bcm2835_gpio_irq_ack, 712 .irq_mask = bcm2835_gpio_irq_mask, 713 .irq_unmask = bcm2835_gpio_irq_unmask, 714 .irq_set_wake = bcm2835_gpio_irq_set_wake, 715 .flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE), 716 GPIOCHIP_IRQ_RESOURCE_HELPERS, 717 }; 718 719 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) 720 { 721 return BCM2835_NUM_GPIOS; 722 } 723 724 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev, 725 unsigned selector) 726 { 727 return bcm2835_gpio_groups[selector]; 728 } 729 730 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev, 731 unsigned selector, 732 const unsigned **pins, 733 unsigned *num_pins) 734 { 735 *pins = &bcm2835_gpio_pins[selector].number; 736 *num_pins = 1; 737 738 return 0; 739 } 740 741 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, 742 struct seq_file *s, 743 unsigned offset) 744 { 745 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 746 struct gpio_chip *chip = &pc->gpio_chip; 747 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 748 const char *fname = bcm2835_functions[fsel]; 749 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset); 750 int irq = irq_find_mapping(chip->irq.domain, offset); 751 752 seq_printf(s, "function %s in %s; irq %d (%s)", 753 fname, value ? "hi" : "lo", 754 irq, irq_type_names[pc->irq_type[offset]]); 755 } 756 757 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev, 758 struct pinctrl_map *maps, unsigned num_maps) 759 { 760 int i; 761 762 for (i = 0; i < num_maps; i++) 763 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 764 kfree(maps[i].data.configs.configs); 765 766 kfree(maps); 767 } 768 769 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, 770 struct device_node *np, u32 pin, u32 fnum, 771 struct pinctrl_map **maps) 772 { 773 struct pinctrl_map *map = *maps; 774 775 if (fnum >= ARRAY_SIZE(bcm2835_functions)) { 776 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum); 777 return -EINVAL; 778 } 779 780 map->type = PIN_MAP_TYPE_MUX_GROUP; 781 map->data.mux.group = bcm2835_gpio_groups[pin]; 782 map->data.mux.function = bcm2835_functions[fnum]; 783 (*maps)++; 784 785 return 0; 786 } 787 788 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, 789 struct device_node *np, u32 pin, u32 pull, 790 struct pinctrl_map **maps) 791 { 792 struct pinctrl_map *map = *maps; 793 unsigned long *configs; 794 795 if (pull > 2) { 796 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull); 797 return -EINVAL; 798 } 799 800 configs = kzalloc(sizeof(*configs), GFP_KERNEL); 801 if (!configs) 802 return -ENOMEM; 803 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull); 804 805 map->type = PIN_MAP_TYPE_CONFIGS_PIN; 806 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name; 807 map->data.configs.configs = configs; 808 map->data.configs.num_configs = 1; 809 (*maps)++; 810 811 return 0; 812 } 813 814 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 815 struct device_node *np, 816 struct pinctrl_map **map, unsigned int *num_maps) 817 { 818 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 819 struct property *pins, *funcs, *pulls; 820 int num_pins, num_funcs, num_pulls, maps_per_pin; 821 struct pinctrl_map *maps, *cur_map; 822 int i, err; 823 u32 pin, func, pull; 824 825 /* Check for generic binding in this node */ 826 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps); 827 if (err || *num_maps) 828 return err; 829 830 /* Generic binding did not find anything continue with legacy parse */ 831 pins = of_find_property(np, "brcm,pins", NULL); 832 if (!pins) { 833 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np); 834 return -EINVAL; 835 } 836 837 funcs = of_find_property(np, "brcm,function", NULL); 838 pulls = of_find_property(np, "brcm,pull", NULL); 839 840 if (!funcs && !pulls) { 841 dev_err(pc->dev, 842 "%pOF: neither brcm,function nor brcm,pull specified\n", 843 np); 844 return -EINVAL; 845 } 846 847 num_pins = pins->length / 4; 848 num_funcs = funcs ? (funcs->length / 4) : 0; 849 num_pulls = pulls ? (pulls->length / 4) : 0; 850 851 if (num_funcs > 1 && num_funcs != num_pins) { 852 dev_err(pc->dev, 853 "%pOF: brcm,function must have 1 or %d entries\n", 854 np, num_pins); 855 return -EINVAL; 856 } 857 858 if (num_pulls > 1 && num_pulls != num_pins) { 859 dev_err(pc->dev, 860 "%pOF: brcm,pull must have 1 or %d entries\n", 861 np, num_pins); 862 return -EINVAL; 863 } 864 865 maps_per_pin = 0; 866 if (num_funcs) 867 maps_per_pin++; 868 if (num_pulls) 869 maps_per_pin++; 870 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps), 871 GFP_KERNEL); 872 if (!maps) 873 return -ENOMEM; 874 875 for (i = 0; i < num_pins; i++) { 876 err = of_property_read_u32_index(np, "brcm,pins", i, &pin); 877 if (err) 878 goto out; 879 if (pin >= pc->pctl_desc.npins) { 880 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n", 881 np, pin); 882 err = -EINVAL; 883 goto out; 884 } 885 886 if (num_funcs) { 887 err = of_property_read_u32_index(np, "brcm,function", 888 (num_funcs > 1) ? i : 0, &func); 889 if (err) 890 goto out; 891 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, 892 func, &cur_map); 893 if (err) 894 goto out; 895 } 896 if (num_pulls) { 897 err = of_property_read_u32_index(np, "brcm,pull", 898 (num_pulls > 1) ? i : 0, &pull); 899 if (err) 900 goto out; 901 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, 902 pull, &cur_map); 903 if (err) 904 goto out; 905 } 906 } 907 908 *map = maps; 909 *num_maps = num_pins * maps_per_pin; 910 911 return 0; 912 913 out: 914 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin); 915 return err; 916 } 917 918 static const struct pinctrl_ops bcm2835_pctl_ops = { 919 .get_groups_count = bcm2835_pctl_get_groups_count, 920 .get_group_name = bcm2835_pctl_get_group_name, 921 .get_group_pins = bcm2835_pctl_get_group_pins, 922 .pin_dbg_show = bcm2835_pctl_pin_dbg_show, 923 .dt_node_to_map = bcm2835_pctl_dt_node_to_map, 924 .dt_free_map = bcm2835_pctl_dt_free_map, 925 }; 926 927 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev, 928 unsigned offset) 929 { 930 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 931 932 /* disable by setting to GPIO_IN */ 933 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 934 return 0; 935 } 936 937 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev) 938 { 939 return BCM2835_FSEL_COUNT; 940 } 941 942 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev, 943 unsigned selector) 944 { 945 return bcm2835_functions[selector]; 946 } 947 948 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, 949 unsigned selector, 950 const char * const **groups, 951 unsigned * const num_groups) 952 { 953 /* every pin can do every function */ 954 *groups = bcm2835_gpio_groups; 955 *num_groups = BCM2835_NUM_GPIOS; 956 957 return 0; 958 } 959 960 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev, 961 unsigned func_selector, 962 unsigned group_selector) 963 { 964 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 965 966 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector); 967 968 return 0; 969 } 970 971 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 972 struct pinctrl_gpio_range *range, 973 unsigned offset) 974 { 975 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 976 977 /* disable by setting to GPIO_IN */ 978 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 979 } 980 981 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 982 struct pinctrl_gpio_range *range, 983 unsigned offset, 984 bool input) 985 { 986 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 987 enum bcm2835_fsel fsel = input ? 988 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT; 989 990 bcm2835_pinctrl_fsel_set(pc, offset, fsel); 991 992 return 0; 993 } 994 995 static const struct pinmux_ops bcm2835_pmx_ops = { 996 .free = bcm2835_pmx_free, 997 .get_functions_count = bcm2835_pmx_get_functions_count, 998 .get_function_name = bcm2835_pmx_get_function_name, 999 .get_function_groups = bcm2835_pmx_get_function_groups, 1000 .set_mux = bcm2835_pmx_set, 1001 .gpio_disable_free = bcm2835_pmx_gpio_disable_free, 1002 .gpio_set_direction = bcm2835_pmx_gpio_set_direction, 1003 }; 1004 1005 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, 1006 unsigned pin, unsigned long *config) 1007 { 1008 /* No way to read back config in HW */ 1009 return -ENOTSUPP; 1010 } 1011 1012 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc, 1013 unsigned int pin, unsigned int arg) 1014 { 1015 u32 off, bit; 1016 1017 off = GPIO_REG_OFFSET(pin); 1018 bit = GPIO_REG_SHIFT(pin); 1019 1020 bcm2835_gpio_wr(pc, GPPUD, arg & 3); 1021 /* 1022 * BCM2835 datasheet say to wait 150 cycles, but not of what. 1023 * But the VideoCore firmware delay for this operation 1024 * based nearly on the same amount of VPU cycles and this clock 1025 * runs at 250 MHz. 1026 */ 1027 udelay(1); 1028 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); 1029 udelay(1); 1030 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); 1031 } 1032 1033 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, 1034 unsigned int pin, unsigned long *configs, 1035 unsigned int num_configs) 1036 { 1037 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1038 u32 param, arg; 1039 int i; 1040 1041 for (i = 0; i < num_configs; i++) { 1042 param = pinconf_to_config_param(configs[i]); 1043 arg = pinconf_to_config_argument(configs[i]); 1044 1045 switch (param) { 1046 /* Set legacy brcm,pull */ 1047 case BCM2835_PINCONF_PARAM_PULL: 1048 bcm2835_pull_config_set(pc, pin, arg); 1049 break; 1050 1051 /* Set pull generic bindings */ 1052 case PIN_CONFIG_BIAS_DISABLE: 1053 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF); 1054 break; 1055 1056 case PIN_CONFIG_BIAS_PULL_DOWN: 1057 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN); 1058 break; 1059 1060 case PIN_CONFIG_BIAS_PULL_UP: 1061 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP); 1062 break; 1063 1064 /* Set output-high or output-low */ 1065 case PIN_CONFIG_OUTPUT: 1066 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); 1067 break; 1068 1069 default: 1070 return -ENOTSUPP; 1071 1072 } /* switch param type */ 1073 } /* for each config */ 1074 1075 return 0; 1076 } 1077 1078 static const struct pinconf_ops bcm2835_pinconf_ops = { 1079 .is_generic = true, 1080 .pin_config_get = bcm2835_pinconf_get, 1081 .pin_config_set = bcm2835_pinconf_set, 1082 }; 1083 1084 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc, 1085 unsigned int pin, unsigned int arg) 1086 { 1087 u32 shifter; 1088 u32 value; 1089 u32 off; 1090 1091 off = PUD_2711_REG_OFFSET(pin); 1092 shifter = PUD_2711_REG_SHIFT(pin); 1093 1094 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4)); 1095 value &= ~(PUD_2711_MASK << shifter); 1096 value |= (arg << shifter); 1097 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value); 1098 } 1099 1100 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev, 1101 unsigned int pin, unsigned long *configs, 1102 unsigned int num_configs) 1103 { 1104 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1105 u32 param, arg; 1106 int i; 1107 1108 for (i = 0; i < num_configs; i++) { 1109 param = pinconf_to_config_param(configs[i]); 1110 arg = pinconf_to_config_argument(configs[i]); 1111 1112 switch (param) { 1113 /* convert legacy brcm,pull */ 1114 case BCM2835_PINCONF_PARAM_PULL: 1115 if (arg == BCM2835_PUD_UP) 1116 arg = BCM2711_PULL_UP; 1117 else if (arg == BCM2835_PUD_DOWN) 1118 arg = BCM2711_PULL_DOWN; 1119 else 1120 arg = BCM2711_PULL_NONE; 1121 1122 bcm2711_pull_config_set(pc, pin, arg); 1123 break; 1124 1125 /* Set pull generic bindings */ 1126 case PIN_CONFIG_BIAS_DISABLE: 1127 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE); 1128 break; 1129 case PIN_CONFIG_BIAS_PULL_DOWN: 1130 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN); 1131 break; 1132 case PIN_CONFIG_BIAS_PULL_UP: 1133 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP); 1134 break; 1135 1136 /* Set output-high or output-low */ 1137 case PIN_CONFIG_OUTPUT: 1138 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); 1139 break; 1140 1141 default: 1142 return -ENOTSUPP; 1143 } 1144 } /* for each config */ 1145 1146 return 0; 1147 } 1148 1149 static const struct pinconf_ops bcm2711_pinconf_ops = { 1150 .is_generic = true, 1151 .pin_config_get = bcm2835_pinconf_get, 1152 .pin_config_set = bcm2711_pinconf_set, 1153 }; 1154 1155 static const struct pinctrl_desc bcm2835_pinctrl_desc = { 1156 .name = MODULE_NAME, 1157 .pins = bcm2835_gpio_pins, 1158 .npins = BCM2835_NUM_GPIOS, 1159 .pctlops = &bcm2835_pctl_ops, 1160 .pmxops = &bcm2835_pmx_ops, 1161 .confops = &bcm2835_pinconf_ops, 1162 .owner = THIS_MODULE, 1163 }; 1164 1165 static const struct pinctrl_desc bcm2711_pinctrl_desc = { 1166 .name = "pinctrl-bcm2711", 1167 .pins = bcm2835_gpio_pins, 1168 .npins = BCM2711_NUM_GPIOS, 1169 .pctlops = &bcm2835_pctl_ops, 1170 .pmxops = &bcm2835_pmx_ops, 1171 .confops = &bcm2711_pinconf_ops, 1172 .owner = THIS_MODULE, 1173 }; 1174 1175 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { 1176 .name = MODULE_NAME, 1177 .npins = BCM2835_NUM_GPIOS, 1178 }; 1179 1180 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = { 1181 .name = "pinctrl-bcm2711", 1182 .npins = BCM2711_NUM_GPIOS, 1183 }; 1184 1185 struct bcm_plat_data { 1186 const struct gpio_chip *gpio_chip; 1187 const struct pinctrl_desc *pctl_desc; 1188 const struct pinctrl_gpio_range *gpio_range; 1189 }; 1190 1191 static const struct bcm_plat_data bcm2835_plat_data = { 1192 .gpio_chip = &bcm2835_gpio_chip, 1193 .pctl_desc = &bcm2835_pinctrl_desc, 1194 .gpio_range = &bcm2835_pinctrl_gpio_range, 1195 }; 1196 1197 static const struct bcm_plat_data bcm2711_plat_data = { 1198 .gpio_chip = &bcm2711_gpio_chip, 1199 .pctl_desc = &bcm2711_pinctrl_desc, 1200 .gpio_range = &bcm2711_pinctrl_gpio_range, 1201 }; 1202 1203 static const struct of_device_id bcm2835_pinctrl_match[] = { 1204 { 1205 .compatible = "brcm,bcm2835-gpio", 1206 .data = &bcm2835_plat_data, 1207 }, 1208 { 1209 .compatible = "brcm,bcm2711-gpio", 1210 .data = &bcm2711_plat_data, 1211 }, 1212 { 1213 .compatible = "brcm,bcm7211-gpio", 1214 .data = &bcm2711_plat_data, 1215 }, 1216 {} 1217 }; 1218 1219 static int bcm2835_pinctrl_probe(struct platform_device *pdev) 1220 { 1221 struct device *dev = &pdev->dev; 1222 struct device_node *np = dev->of_node; 1223 const struct bcm_plat_data *pdata; 1224 struct bcm2835_pinctrl *pc; 1225 struct gpio_irq_chip *girq; 1226 struct resource iomem; 1227 int err, i; 1228 const struct of_device_id *match; 1229 int is_7211 = 0; 1230 1231 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS); 1232 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS); 1233 1234 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); 1235 if (!pc) 1236 return -ENOMEM; 1237 1238 platform_set_drvdata(pdev, pc); 1239 pc->dev = dev; 1240 1241 err = of_address_to_resource(np, 0, &iomem); 1242 if (err) { 1243 dev_err(dev, "could not get IO memory\n"); 1244 return err; 1245 } 1246 1247 pc->base = devm_ioremap_resource(dev, &iomem); 1248 if (IS_ERR(pc->base)) 1249 return PTR_ERR(pc->base); 1250 1251 match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node); 1252 if (!match) 1253 return -EINVAL; 1254 1255 pdata = match->data; 1256 is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio"); 1257 1258 pc->gpio_chip = *pdata->gpio_chip; 1259 pc->gpio_chip.parent = dev; 1260 1261 spin_lock_init(&pc->fsel_lock); 1262 for (i = 0; i < BCM2835_NUM_BANKS; i++) { 1263 unsigned long events; 1264 unsigned offset; 1265 1266 /* clear event detection flags */ 1267 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); 1268 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0); 1269 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0); 1270 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0); 1271 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0); 1272 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0); 1273 1274 /* clear all the events */ 1275 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4); 1276 for_each_set_bit(offset, &events, 32) 1277 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); 1278 1279 raw_spin_lock_init(&pc->irq_lock[i]); 1280 } 1281 1282 pc->pctl_desc = *pdata->pctl_desc; 1283 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); 1284 if (IS_ERR(pc->pctl_dev)) { 1285 gpiochip_remove(&pc->gpio_chip); 1286 return PTR_ERR(pc->pctl_dev); 1287 } 1288 1289 pc->gpio_range = *pdata->gpio_range; 1290 pc->gpio_range.base = pc->gpio_chip.base; 1291 pc->gpio_range.gc = &pc->gpio_chip; 1292 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range); 1293 1294 girq = &pc->gpio_chip.irq; 1295 gpio_irq_chip_set_chip(girq, &bcm2835_gpio_irq_chip); 1296 girq->parent_handler = bcm2835_gpio_irq_handler; 1297 girq->num_parents = BCM2835_NUM_IRQS; 1298 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS, 1299 sizeof(*girq->parents), 1300 GFP_KERNEL); 1301 if (!girq->parents) { 1302 err = -ENOMEM; 1303 goto out_remove; 1304 } 1305 1306 if (is_7211) { 1307 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS, 1308 sizeof(*pc->wake_irq), 1309 GFP_KERNEL); 1310 if (!pc->wake_irq) { 1311 err = -ENOMEM; 1312 goto out_remove; 1313 } 1314 } 1315 1316 /* 1317 * Use the same handler for all groups: this is necessary 1318 * since we use one gpiochip to cover all lines - the 1319 * irq handler then needs to figure out which group and 1320 * bank that was firing the IRQ and look up the per-group 1321 * and bank data. 1322 */ 1323 for (i = 0; i < BCM2835_NUM_IRQS; i++) { 1324 int len; 1325 char *name; 1326 1327 girq->parents[i] = irq_of_parse_and_map(np, i); 1328 if (!is_7211) { 1329 if (!girq->parents[i]) { 1330 girq->num_parents = i; 1331 break; 1332 } 1333 continue; 1334 } 1335 /* Skip over the all banks interrupts */ 1336 pc->wake_irq[i] = irq_of_parse_and_map(np, i + 1337 BCM2835_NUM_IRQS + 1); 1338 1339 len = strlen(dev_name(pc->dev)) + 16; 1340 name = devm_kzalloc(pc->dev, len, GFP_KERNEL); 1341 if (!name) { 1342 err = -ENOMEM; 1343 goto out_remove; 1344 } 1345 1346 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i); 1347 1348 /* These are optional interrupts */ 1349 err = devm_request_irq(dev, pc->wake_irq[i], 1350 bcm2835_gpio_wake_irq_handler, 1351 IRQF_SHARED, name, pc); 1352 if (err) 1353 dev_warn(dev, "unable to request wake IRQ %d\n", 1354 pc->wake_irq[i]); 1355 } 1356 1357 girq->default_type = IRQ_TYPE_NONE; 1358 girq->handler = handle_level_irq; 1359 1360 err = gpiochip_add_data(&pc->gpio_chip, pc); 1361 if (err) { 1362 dev_err(dev, "could not add GPIO chip\n"); 1363 goto out_remove; 1364 } 1365 1366 return 0; 1367 1368 out_remove: 1369 pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range); 1370 return err; 1371 } 1372 1373 static struct platform_driver bcm2835_pinctrl_driver = { 1374 .probe = bcm2835_pinctrl_probe, 1375 .driver = { 1376 .name = MODULE_NAME, 1377 .of_match_table = bcm2835_pinctrl_match, 1378 .suppress_bind_attrs = true, 1379 }, 1380 }; 1381 module_platform_driver(bcm2835_pinctrl_driver); 1382 1383 MODULE_AUTHOR("Chris Boot"); 1384 MODULE_AUTHOR("Simon Arlott"); 1385 MODULE_AUTHOR("Stephen Warren"); 1386 MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver"); 1387 MODULE_LICENSE("GPL"); 1388