1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) 4 * 5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren 6 * 7 * This driver is inspired by: 8 * pinctrl-nomadik.c, please see original file for copyright information 9 * pinctrl-tegra.c, please see original file for copyright information 10 */ 11 12 #include <linux/bitmap.h> 13 #include <linux/bug.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/err.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/io.h> 19 #include <linux/irq.h> 20 #include <linux/irqdesc.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/module.h> 24 #include <linux/of_address.h> 25 #include <linux/of.h> 26 #include <linux/of_irq.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/pinctrl/machine.h> 29 #include <linux/pinctrl/pinconf.h> 30 #include <linux/pinctrl/pinctrl.h> 31 #include <linux/pinctrl/pinmux.h> 32 #include <linux/pinctrl/pinconf-generic.h> 33 #include <linux/platform_device.h> 34 #include <linux/seq_file.h> 35 #include <linux/slab.h> 36 #include <linux/spinlock.h> 37 #include <linux/types.h> 38 #include <dt-bindings/pinctrl/bcm2835.h> 39 40 #define MODULE_NAME "pinctrl-bcm2835" 41 #define BCM2835_NUM_GPIOS 54 42 #define BCM2711_NUM_GPIOS 58 43 #define BCM2835_NUM_BANKS 2 44 #define BCM2835_NUM_IRQS 3 45 46 /* GPIO register offsets */ 47 #define GPFSEL0 0x0 /* Function Select */ 48 #define GPSET0 0x1c /* Pin Output Set */ 49 #define GPCLR0 0x28 /* Pin Output Clear */ 50 #define GPLEV0 0x34 /* Pin Level */ 51 #define GPEDS0 0x40 /* Pin Event Detect Status */ 52 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */ 53 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */ 54 #define GPHEN0 0x64 /* Pin High Detect Enable */ 55 #define GPLEN0 0x70 /* Pin Low Detect Enable */ 56 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */ 57 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ 58 #define GPPUD 0x94 /* Pin Pull-up/down Enable */ 59 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ 60 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */ 61 62 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) 63 #define FSEL_SHIFT(p) (((p) % 10) * 3) 64 #define GPIO_REG_OFFSET(p) ((p) / 32) 65 #define GPIO_REG_SHIFT(p) ((p) % 32) 66 67 #define PUD_2711_MASK 0x3 68 #define PUD_2711_REG_OFFSET(p) ((p) / 16) 69 #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2) 70 71 /* argument: bcm2835_pinconf_pull */ 72 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1) 73 74 #define BCM2711_PULL_NONE 0x0 75 #define BCM2711_PULL_UP 0x1 76 #define BCM2711_PULL_DOWN 0x2 77 78 struct bcm2835_pinctrl { 79 struct device *dev; 80 void __iomem *base; 81 int *wake_irq; 82 83 /* note: locking assumes each bank will have its own unsigned long */ 84 unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; 85 unsigned int irq_type[BCM2711_NUM_GPIOS]; 86 87 struct pinctrl_dev *pctl_dev; 88 struct gpio_chip gpio_chip; 89 struct pinctrl_desc pctl_desc; 90 struct pinctrl_gpio_range gpio_range; 91 92 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS]; 93 /* Protect FSEL registers */ 94 spinlock_t fsel_lock; 95 }; 96 97 /* pins are just named GPIO0..GPIO53 */ 98 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) 99 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = { 100 BCM2835_GPIO_PIN(0), 101 BCM2835_GPIO_PIN(1), 102 BCM2835_GPIO_PIN(2), 103 BCM2835_GPIO_PIN(3), 104 BCM2835_GPIO_PIN(4), 105 BCM2835_GPIO_PIN(5), 106 BCM2835_GPIO_PIN(6), 107 BCM2835_GPIO_PIN(7), 108 BCM2835_GPIO_PIN(8), 109 BCM2835_GPIO_PIN(9), 110 BCM2835_GPIO_PIN(10), 111 BCM2835_GPIO_PIN(11), 112 BCM2835_GPIO_PIN(12), 113 BCM2835_GPIO_PIN(13), 114 BCM2835_GPIO_PIN(14), 115 BCM2835_GPIO_PIN(15), 116 BCM2835_GPIO_PIN(16), 117 BCM2835_GPIO_PIN(17), 118 BCM2835_GPIO_PIN(18), 119 BCM2835_GPIO_PIN(19), 120 BCM2835_GPIO_PIN(20), 121 BCM2835_GPIO_PIN(21), 122 BCM2835_GPIO_PIN(22), 123 BCM2835_GPIO_PIN(23), 124 BCM2835_GPIO_PIN(24), 125 BCM2835_GPIO_PIN(25), 126 BCM2835_GPIO_PIN(26), 127 BCM2835_GPIO_PIN(27), 128 BCM2835_GPIO_PIN(28), 129 BCM2835_GPIO_PIN(29), 130 BCM2835_GPIO_PIN(30), 131 BCM2835_GPIO_PIN(31), 132 BCM2835_GPIO_PIN(32), 133 BCM2835_GPIO_PIN(33), 134 BCM2835_GPIO_PIN(34), 135 BCM2835_GPIO_PIN(35), 136 BCM2835_GPIO_PIN(36), 137 BCM2835_GPIO_PIN(37), 138 BCM2835_GPIO_PIN(38), 139 BCM2835_GPIO_PIN(39), 140 BCM2835_GPIO_PIN(40), 141 BCM2835_GPIO_PIN(41), 142 BCM2835_GPIO_PIN(42), 143 BCM2835_GPIO_PIN(43), 144 BCM2835_GPIO_PIN(44), 145 BCM2835_GPIO_PIN(45), 146 BCM2835_GPIO_PIN(46), 147 BCM2835_GPIO_PIN(47), 148 BCM2835_GPIO_PIN(48), 149 BCM2835_GPIO_PIN(49), 150 BCM2835_GPIO_PIN(50), 151 BCM2835_GPIO_PIN(51), 152 BCM2835_GPIO_PIN(52), 153 BCM2835_GPIO_PIN(53), 154 BCM2835_GPIO_PIN(54), 155 BCM2835_GPIO_PIN(55), 156 BCM2835_GPIO_PIN(56), 157 BCM2835_GPIO_PIN(57), 158 }; 159 160 /* one pin per group */ 161 static const char * const bcm2835_gpio_groups[] = { 162 "gpio0", 163 "gpio1", 164 "gpio2", 165 "gpio3", 166 "gpio4", 167 "gpio5", 168 "gpio6", 169 "gpio7", 170 "gpio8", 171 "gpio9", 172 "gpio10", 173 "gpio11", 174 "gpio12", 175 "gpio13", 176 "gpio14", 177 "gpio15", 178 "gpio16", 179 "gpio17", 180 "gpio18", 181 "gpio19", 182 "gpio20", 183 "gpio21", 184 "gpio22", 185 "gpio23", 186 "gpio24", 187 "gpio25", 188 "gpio26", 189 "gpio27", 190 "gpio28", 191 "gpio29", 192 "gpio30", 193 "gpio31", 194 "gpio32", 195 "gpio33", 196 "gpio34", 197 "gpio35", 198 "gpio36", 199 "gpio37", 200 "gpio38", 201 "gpio39", 202 "gpio40", 203 "gpio41", 204 "gpio42", 205 "gpio43", 206 "gpio44", 207 "gpio45", 208 "gpio46", 209 "gpio47", 210 "gpio48", 211 "gpio49", 212 "gpio50", 213 "gpio51", 214 "gpio52", 215 "gpio53", 216 "gpio54", 217 "gpio55", 218 "gpio56", 219 "gpio57", 220 }; 221 222 enum bcm2835_fsel { 223 BCM2835_FSEL_COUNT = 8, 224 BCM2835_FSEL_MASK = 0x7, 225 }; 226 227 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = { 228 [BCM2835_FSEL_GPIO_IN] = "gpio_in", 229 [BCM2835_FSEL_GPIO_OUT] = "gpio_out", 230 [BCM2835_FSEL_ALT0] = "alt0", 231 [BCM2835_FSEL_ALT1] = "alt1", 232 [BCM2835_FSEL_ALT2] = "alt2", 233 [BCM2835_FSEL_ALT3] = "alt3", 234 [BCM2835_FSEL_ALT4] = "alt4", 235 [BCM2835_FSEL_ALT5] = "alt5", 236 }; 237 238 static const char * const irq_type_names[] = { 239 [IRQ_TYPE_NONE] = "none", 240 [IRQ_TYPE_EDGE_RISING] = "edge-rising", 241 [IRQ_TYPE_EDGE_FALLING] = "edge-falling", 242 [IRQ_TYPE_EDGE_BOTH] = "edge-both", 243 [IRQ_TYPE_LEVEL_HIGH] = "level-high", 244 [IRQ_TYPE_LEVEL_LOW] = "level-low", 245 }; 246 247 static bool persist_gpio_outputs; 248 module_param(persist_gpio_outputs, bool, 0644); 249 MODULE_PARM_DESC(persist_gpio_outputs, "Enable GPIO_OUT persistence when pin is freed"); 250 251 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) 252 { 253 return readl(pc->base + reg); 254 } 255 256 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, 257 u32 val) 258 { 259 writel(val, pc->base + reg); 260 } 261 262 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, 263 unsigned bit) 264 { 265 reg += GPIO_REG_OFFSET(bit) * 4; 266 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1; 267 } 268 269 /* note NOT a read/modify/write cycle */ 270 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc, 271 unsigned reg, unsigned bit) 272 { 273 reg += GPIO_REG_OFFSET(bit) * 4; 274 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); 275 } 276 277 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get( 278 struct bcm2835_pinctrl *pc, unsigned pin) 279 { 280 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 281 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 282 283 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, 284 bcm2835_functions[status]); 285 286 return status; 287 } 288 289 static inline void bcm2835_pinctrl_fsel_set( 290 struct bcm2835_pinctrl *pc, unsigned pin, 291 enum bcm2835_fsel fsel) 292 { 293 u32 val; 294 enum bcm2835_fsel cur; 295 unsigned long flags; 296 297 spin_lock_irqsave(&pc->fsel_lock, flags); 298 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 299 cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 300 301 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, 302 bcm2835_functions[cur]); 303 304 if (cur == fsel) 305 goto unlock; 306 307 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) { 308 /* always transition through GPIO_IN */ 309 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 310 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); 311 312 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin, 313 bcm2835_functions[BCM2835_FSEL_GPIO_IN]); 314 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 315 } 316 317 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 318 val |= fsel << FSEL_SHIFT(pin); 319 320 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin, 321 bcm2835_functions[fsel]); 322 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 323 324 unlock: 325 spin_unlock_irqrestore(&pc->fsel_lock, flags); 326 } 327 328 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 329 { 330 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 331 332 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 333 return 0; 334 } 335 336 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) 337 { 338 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 339 340 return bcm2835_gpio_get_bit(pc, GPLEV0, offset); 341 } 342 343 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 344 { 345 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 346 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 347 348 /* Alternative function doesn't clearly provide a direction */ 349 if (fsel > BCM2835_FSEL_GPIO_OUT) 350 return -EINVAL; 351 352 if (fsel == BCM2835_FSEL_GPIO_IN) 353 return GPIO_LINE_DIRECTION_IN; 354 355 return GPIO_LINE_DIRECTION_OUT; 356 } 357 358 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 359 { 360 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 361 362 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); 363 } 364 365 static int bcm2835_gpio_direction_output(struct gpio_chip *chip, 366 unsigned offset, int value) 367 { 368 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 369 370 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); 371 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT); 372 return 0; 373 } 374 375 static int bcm2835_add_pin_ranges_fallback(struct gpio_chip *gc) 376 { 377 struct device_node *np = dev_of_node(gc->parent); 378 struct pinctrl_dev *pctldev = of_pinctrl_get(np); 379 380 if (!pctldev) 381 return 0; 382 383 return gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0, 384 gc->ngpio); 385 } 386 387 static const struct gpio_chip bcm2835_gpio_chip = { 388 .label = MODULE_NAME, 389 .owner = THIS_MODULE, 390 .request = gpiochip_generic_request, 391 .free = gpiochip_generic_free, 392 .direction_input = bcm2835_gpio_direction_input, 393 .direction_output = bcm2835_gpio_direction_output, 394 .get_direction = bcm2835_gpio_get_direction, 395 .get = bcm2835_gpio_get, 396 .set = bcm2835_gpio_set, 397 .set_config = gpiochip_generic_config, 398 .base = -1, 399 .ngpio = BCM2835_NUM_GPIOS, 400 .can_sleep = false, 401 .add_pin_ranges = bcm2835_add_pin_ranges_fallback, 402 }; 403 404 static const struct gpio_chip bcm2711_gpio_chip = { 405 .label = "pinctrl-bcm2711", 406 .owner = THIS_MODULE, 407 .request = gpiochip_generic_request, 408 .free = gpiochip_generic_free, 409 .direction_input = bcm2835_gpio_direction_input, 410 .direction_output = bcm2835_gpio_direction_output, 411 .get_direction = bcm2835_gpio_get_direction, 412 .get = bcm2835_gpio_get, 413 .set = bcm2835_gpio_set, 414 .set_config = gpiochip_generic_config, 415 .base = -1, 416 .ngpio = BCM2711_NUM_GPIOS, 417 .can_sleep = false, 418 .add_pin_ranges = bcm2835_add_pin_ranges_fallback, 419 }; 420 421 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, 422 unsigned int bank, u32 mask) 423 { 424 unsigned long events; 425 unsigned offset; 426 unsigned gpio; 427 428 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); 429 events &= mask; 430 events &= pc->enabled_irq_map[bank]; 431 for_each_set_bit(offset, &events, 32) { 432 gpio = (32 * bank) + offset; 433 generic_handle_domain_irq(pc->gpio_chip.irq.domain, 434 gpio); 435 } 436 } 437 438 static void bcm2835_gpio_irq_handler(struct irq_desc *desc) 439 { 440 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 441 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 442 struct irq_chip *host_chip = irq_desc_get_chip(desc); 443 int irq = irq_desc_get_irq(desc); 444 int group = 0; 445 int i; 446 447 for (i = 0; i < BCM2835_NUM_IRQS; i++) { 448 if (chip->irq.parents[i] == irq) { 449 group = i; 450 break; 451 } 452 } 453 /* This should not happen, every IRQ has a bank */ 454 BUG_ON(i == BCM2835_NUM_IRQS); 455 456 chained_irq_enter(host_chip, desc); 457 458 switch (group) { 459 case 0: /* IRQ0 covers GPIOs 0-27 */ 460 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff); 461 break; 462 case 1: /* IRQ1 covers GPIOs 28-45 */ 463 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000); 464 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff); 465 break; 466 case 2: /* IRQ2 covers GPIOs 46-57 */ 467 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000); 468 break; 469 } 470 471 chained_irq_exit(host_chip, desc); 472 } 473 474 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id) 475 { 476 return IRQ_HANDLED; 477 } 478 479 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 480 unsigned reg, unsigned offset, bool enable) 481 { 482 u32 value; 483 reg += GPIO_REG_OFFSET(offset) * 4; 484 value = bcm2835_gpio_rd(pc, reg); 485 if (enable) 486 value |= BIT(GPIO_REG_SHIFT(offset)); 487 else 488 value &= ~(BIT(GPIO_REG_SHIFT(offset))); 489 bcm2835_gpio_wr(pc, reg, value); 490 } 491 492 /* fast path for IRQ handler */ 493 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 494 unsigned offset, bool enable) 495 { 496 switch (pc->irq_type[offset]) { 497 case IRQ_TYPE_EDGE_RISING: 498 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 499 break; 500 501 case IRQ_TYPE_EDGE_FALLING: 502 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 503 break; 504 505 case IRQ_TYPE_EDGE_BOTH: 506 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 507 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 508 break; 509 510 case IRQ_TYPE_LEVEL_HIGH: 511 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable); 512 break; 513 514 case IRQ_TYPE_LEVEL_LOW: 515 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable); 516 break; 517 } 518 } 519 520 static void bcm2835_gpio_irq_unmask(struct irq_data *data) 521 { 522 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 523 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 524 unsigned gpio = irqd_to_hwirq(data); 525 unsigned offset = GPIO_REG_SHIFT(gpio); 526 unsigned bank = GPIO_REG_OFFSET(gpio); 527 unsigned long flags; 528 529 gpiochip_enable_irq(chip, gpio); 530 531 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); 532 set_bit(offset, &pc->enabled_irq_map[bank]); 533 bcm2835_gpio_irq_config(pc, gpio, true); 534 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 535 } 536 537 static void bcm2835_gpio_irq_mask(struct irq_data *data) 538 { 539 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 540 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 541 unsigned gpio = irqd_to_hwirq(data); 542 unsigned offset = GPIO_REG_SHIFT(gpio); 543 unsigned bank = GPIO_REG_OFFSET(gpio); 544 unsigned long flags; 545 546 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); 547 bcm2835_gpio_irq_config(pc, gpio, false); 548 /* Clear events that were latched prior to clearing event sources */ 549 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 550 clear_bit(offset, &pc->enabled_irq_map[bank]); 551 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 552 553 gpiochip_disable_irq(chip, gpio); 554 } 555 556 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, 557 unsigned offset, unsigned int type) 558 { 559 switch (type) { 560 case IRQ_TYPE_NONE: 561 case IRQ_TYPE_EDGE_RISING: 562 case IRQ_TYPE_EDGE_FALLING: 563 case IRQ_TYPE_EDGE_BOTH: 564 case IRQ_TYPE_LEVEL_HIGH: 565 case IRQ_TYPE_LEVEL_LOW: 566 pc->irq_type[offset] = type; 567 break; 568 569 default: 570 return -EINVAL; 571 } 572 return 0; 573 } 574 575 /* slower path for reconfiguring IRQ type */ 576 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc, 577 unsigned offset, unsigned int type) 578 { 579 switch (type) { 580 case IRQ_TYPE_NONE: 581 if (pc->irq_type[offset] != type) { 582 bcm2835_gpio_irq_config(pc, offset, false); 583 pc->irq_type[offset] = type; 584 } 585 break; 586 587 case IRQ_TYPE_EDGE_RISING: 588 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 589 /* RISING already enabled, disable FALLING */ 590 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 591 bcm2835_gpio_irq_config(pc, offset, false); 592 pc->irq_type[offset] = type; 593 } else if (pc->irq_type[offset] != type) { 594 bcm2835_gpio_irq_config(pc, offset, false); 595 pc->irq_type[offset] = type; 596 bcm2835_gpio_irq_config(pc, offset, true); 597 } 598 break; 599 600 case IRQ_TYPE_EDGE_FALLING: 601 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 602 /* FALLING already enabled, disable RISING */ 603 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 604 bcm2835_gpio_irq_config(pc, offset, false); 605 pc->irq_type[offset] = type; 606 } else if (pc->irq_type[offset] != type) { 607 bcm2835_gpio_irq_config(pc, offset, false); 608 pc->irq_type[offset] = type; 609 bcm2835_gpio_irq_config(pc, offset, true); 610 } 611 break; 612 613 case IRQ_TYPE_EDGE_BOTH: 614 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) { 615 /* RISING already enabled, enable FALLING too */ 616 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 617 bcm2835_gpio_irq_config(pc, offset, true); 618 pc->irq_type[offset] = type; 619 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) { 620 /* FALLING already enabled, enable RISING too */ 621 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 622 bcm2835_gpio_irq_config(pc, offset, true); 623 pc->irq_type[offset] = type; 624 } else if (pc->irq_type[offset] != type) { 625 bcm2835_gpio_irq_config(pc, offset, false); 626 pc->irq_type[offset] = type; 627 bcm2835_gpio_irq_config(pc, offset, true); 628 } 629 break; 630 631 case IRQ_TYPE_LEVEL_HIGH: 632 case IRQ_TYPE_LEVEL_LOW: 633 if (pc->irq_type[offset] != type) { 634 bcm2835_gpio_irq_config(pc, offset, false); 635 pc->irq_type[offset] = type; 636 bcm2835_gpio_irq_config(pc, offset, true); 637 } 638 break; 639 640 default: 641 return -EINVAL; 642 } 643 return 0; 644 } 645 646 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) 647 { 648 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 649 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 650 unsigned gpio = irqd_to_hwirq(data); 651 unsigned offset = GPIO_REG_SHIFT(gpio); 652 unsigned bank = GPIO_REG_OFFSET(gpio); 653 unsigned long flags; 654 int ret; 655 656 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); 657 658 if (test_bit(offset, &pc->enabled_irq_map[bank])) 659 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type); 660 else 661 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); 662 663 if (type & IRQ_TYPE_EDGE_BOTH) 664 irq_set_handler_locked(data, handle_edge_irq); 665 else 666 irq_set_handler_locked(data, handle_level_irq); 667 668 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 669 670 return ret; 671 } 672 673 static void bcm2835_gpio_irq_ack(struct irq_data *data) 674 { 675 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 676 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 677 unsigned gpio = irqd_to_hwirq(data); 678 679 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 680 } 681 682 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on) 683 { 684 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 685 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 686 unsigned gpio = irqd_to_hwirq(data); 687 unsigned int irqgroup; 688 int ret = -EINVAL; 689 690 if (!pc->wake_irq) 691 return ret; 692 693 if (gpio <= 27) 694 irqgroup = 0; 695 else if (gpio >= 28 && gpio <= 45) 696 irqgroup = 1; 697 else if (gpio >= 46 && gpio <= 57) 698 irqgroup = 2; 699 else 700 return ret; 701 702 if (on) 703 ret = enable_irq_wake(pc->wake_irq[irqgroup]); 704 else 705 ret = disable_irq_wake(pc->wake_irq[irqgroup]); 706 707 return ret; 708 } 709 710 static const struct irq_chip bcm2835_gpio_irq_chip = { 711 .name = MODULE_NAME, 712 .irq_set_type = bcm2835_gpio_irq_set_type, 713 .irq_ack = bcm2835_gpio_irq_ack, 714 .irq_mask = bcm2835_gpio_irq_mask, 715 .irq_unmask = bcm2835_gpio_irq_unmask, 716 .irq_set_wake = bcm2835_gpio_irq_set_wake, 717 .flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE), 718 GPIOCHIP_IRQ_RESOURCE_HELPERS, 719 }; 720 721 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) 722 { 723 return BCM2835_NUM_GPIOS; 724 } 725 726 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev, 727 unsigned selector) 728 { 729 return bcm2835_gpio_groups[selector]; 730 } 731 732 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev, 733 unsigned selector, 734 const unsigned **pins, 735 unsigned *num_pins) 736 { 737 *pins = &bcm2835_gpio_pins[selector].number; 738 *num_pins = 1; 739 740 return 0; 741 } 742 743 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, 744 struct seq_file *s, 745 unsigned offset) 746 { 747 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 748 struct gpio_chip *chip = &pc->gpio_chip; 749 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 750 const char *fname = bcm2835_functions[fsel]; 751 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset); 752 int irq = irq_find_mapping(chip->irq.domain, offset); 753 754 seq_printf(s, "function %s in %s; irq %d (%s)", 755 fname, value ? "hi" : "lo", 756 irq, irq_type_names[pc->irq_type[offset]]); 757 } 758 759 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev, 760 struct pinctrl_map *maps, unsigned num_maps) 761 { 762 int i; 763 764 for (i = 0; i < num_maps; i++) 765 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 766 kfree(maps[i].data.configs.configs); 767 768 kfree(maps); 769 } 770 771 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, 772 struct device_node *np, u32 pin, u32 fnum, 773 struct pinctrl_map **maps) 774 { 775 struct pinctrl_map *map = *maps; 776 777 if (fnum >= ARRAY_SIZE(bcm2835_functions)) { 778 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum); 779 return -EINVAL; 780 } 781 782 map->type = PIN_MAP_TYPE_MUX_GROUP; 783 map->data.mux.group = bcm2835_gpio_groups[pin]; 784 map->data.mux.function = bcm2835_functions[fnum]; 785 (*maps)++; 786 787 return 0; 788 } 789 790 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, 791 struct device_node *np, u32 pin, u32 pull, 792 struct pinctrl_map **maps) 793 { 794 struct pinctrl_map *map = *maps; 795 unsigned long *configs; 796 797 if (pull > 2) { 798 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull); 799 return -EINVAL; 800 } 801 802 configs = kzalloc(sizeof(*configs), GFP_KERNEL); 803 if (!configs) 804 return -ENOMEM; 805 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull); 806 807 map->type = PIN_MAP_TYPE_CONFIGS_PIN; 808 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name; 809 map->data.configs.configs = configs; 810 map->data.configs.num_configs = 1; 811 (*maps)++; 812 813 return 0; 814 } 815 816 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 817 struct device_node *np, 818 struct pinctrl_map **map, unsigned int *num_maps) 819 { 820 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 821 struct property *pins, *funcs, *pulls; 822 int num_pins, num_funcs, num_pulls, maps_per_pin; 823 struct pinctrl_map *maps, *cur_map; 824 int i, err; 825 u32 pin, func, pull; 826 827 /* Check for generic binding in this node */ 828 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps); 829 if (err || *num_maps) 830 return err; 831 832 /* Generic binding did not find anything continue with legacy parse */ 833 pins = of_find_property(np, "brcm,pins", NULL); 834 if (!pins) { 835 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np); 836 return -EINVAL; 837 } 838 839 funcs = of_find_property(np, "brcm,function", NULL); 840 pulls = of_find_property(np, "brcm,pull", NULL); 841 842 if (!funcs && !pulls) { 843 dev_err(pc->dev, 844 "%pOF: neither brcm,function nor brcm,pull specified\n", 845 np); 846 return -EINVAL; 847 } 848 849 num_pins = pins->length / 4; 850 num_funcs = funcs ? (funcs->length / 4) : 0; 851 num_pulls = pulls ? (pulls->length / 4) : 0; 852 853 if (num_funcs > 1 && num_funcs != num_pins) { 854 dev_err(pc->dev, 855 "%pOF: brcm,function must have 1 or %d entries\n", 856 np, num_pins); 857 return -EINVAL; 858 } 859 860 if (num_pulls > 1 && num_pulls != num_pins) { 861 dev_err(pc->dev, 862 "%pOF: brcm,pull must have 1 or %d entries\n", 863 np, num_pins); 864 return -EINVAL; 865 } 866 867 maps_per_pin = 0; 868 if (num_funcs) 869 maps_per_pin++; 870 if (num_pulls) 871 maps_per_pin++; 872 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps), 873 GFP_KERNEL); 874 if (!maps) 875 return -ENOMEM; 876 877 for (i = 0; i < num_pins; i++) { 878 err = of_property_read_u32_index(np, "brcm,pins", i, &pin); 879 if (err) 880 goto out; 881 if (pin >= pc->pctl_desc.npins) { 882 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n", 883 np, pin); 884 err = -EINVAL; 885 goto out; 886 } 887 888 if (num_funcs) { 889 err = of_property_read_u32_index(np, "brcm,function", 890 (num_funcs > 1) ? i : 0, &func); 891 if (err) 892 goto out; 893 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, 894 func, &cur_map); 895 if (err) 896 goto out; 897 } 898 if (num_pulls) { 899 err = of_property_read_u32_index(np, "brcm,pull", 900 (num_pulls > 1) ? i : 0, &pull); 901 if (err) 902 goto out; 903 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, 904 pull, &cur_map); 905 if (err) 906 goto out; 907 } 908 } 909 910 *map = maps; 911 *num_maps = num_pins * maps_per_pin; 912 913 return 0; 914 915 out: 916 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin); 917 return err; 918 } 919 920 static const struct pinctrl_ops bcm2835_pctl_ops = { 921 .get_groups_count = bcm2835_pctl_get_groups_count, 922 .get_group_name = bcm2835_pctl_get_group_name, 923 .get_group_pins = bcm2835_pctl_get_group_pins, 924 .pin_dbg_show = bcm2835_pctl_pin_dbg_show, 925 .dt_node_to_map = bcm2835_pctl_dt_node_to_map, 926 .dt_free_map = bcm2835_pctl_dt_free_map, 927 }; 928 929 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev, 930 unsigned offset) 931 { 932 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 933 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 934 935 if (fsel == BCM2835_FSEL_GPIO_IN) 936 return 0; 937 938 if (persist_gpio_outputs && fsel == BCM2835_FSEL_GPIO_OUT) 939 return 0; 940 941 /* disable by setting to GPIO_IN */ 942 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 943 return 0; 944 } 945 946 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev) 947 { 948 return BCM2835_FSEL_COUNT; 949 } 950 951 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev, 952 unsigned selector) 953 { 954 return bcm2835_functions[selector]; 955 } 956 957 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, 958 unsigned selector, 959 const char * const **groups, 960 unsigned * const num_groups) 961 { 962 /* every pin can do every function */ 963 *groups = bcm2835_gpio_groups; 964 *num_groups = BCM2835_NUM_GPIOS; 965 966 return 0; 967 } 968 969 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev, 970 unsigned func_selector, 971 unsigned group_selector) 972 { 973 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 974 975 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector); 976 977 return 0; 978 } 979 980 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 981 struct pinctrl_gpio_range *range, 982 unsigned offset) 983 { 984 bcm2835_pmx_free(pctldev, offset); 985 } 986 987 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 988 struct pinctrl_gpio_range *range, 989 unsigned offset, 990 bool input) 991 { 992 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 993 enum bcm2835_fsel fsel = input ? 994 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT; 995 996 bcm2835_pinctrl_fsel_set(pc, offset, fsel); 997 998 return 0; 999 } 1000 1001 static const struct pinmux_ops bcm2835_pmx_ops = { 1002 .free = bcm2835_pmx_free, 1003 .get_functions_count = bcm2835_pmx_get_functions_count, 1004 .get_function_name = bcm2835_pmx_get_function_name, 1005 .get_function_groups = bcm2835_pmx_get_function_groups, 1006 .set_mux = bcm2835_pmx_set, 1007 .gpio_disable_free = bcm2835_pmx_gpio_disable_free, 1008 .gpio_set_direction = bcm2835_pmx_gpio_set_direction, 1009 }; 1010 1011 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, 1012 unsigned pin, unsigned long *config) 1013 { 1014 enum pin_config_param param = pinconf_to_config_param(*config); 1015 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1016 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, pin); 1017 u32 val; 1018 1019 /* No way to read back bias config in HW */ 1020 1021 switch (param) { 1022 case PIN_CONFIG_OUTPUT: 1023 if (fsel != BCM2835_FSEL_GPIO_OUT) 1024 return -EINVAL; 1025 1026 val = bcm2835_gpio_get_bit(pc, GPLEV0, pin); 1027 *config = pinconf_to_config_packed(param, val); 1028 break; 1029 1030 default: 1031 return -ENOTSUPP; 1032 } 1033 1034 return 0; 1035 } 1036 1037 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc, 1038 unsigned int pin, unsigned int arg) 1039 { 1040 u32 off, bit; 1041 1042 off = GPIO_REG_OFFSET(pin); 1043 bit = GPIO_REG_SHIFT(pin); 1044 1045 bcm2835_gpio_wr(pc, GPPUD, arg & 3); 1046 /* 1047 * BCM2835 datasheet say to wait 150 cycles, but not of what. 1048 * But the VideoCore firmware delay for this operation 1049 * based nearly on the same amount of VPU cycles and this clock 1050 * runs at 250 MHz. 1051 */ 1052 udelay(1); 1053 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); 1054 udelay(1); 1055 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); 1056 } 1057 1058 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, 1059 unsigned int pin, unsigned long *configs, 1060 unsigned int num_configs) 1061 { 1062 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1063 u32 param, arg; 1064 int i; 1065 1066 for (i = 0; i < num_configs; i++) { 1067 param = pinconf_to_config_param(configs[i]); 1068 arg = pinconf_to_config_argument(configs[i]); 1069 1070 switch (param) { 1071 /* Set legacy brcm,pull */ 1072 case BCM2835_PINCONF_PARAM_PULL: 1073 bcm2835_pull_config_set(pc, pin, arg); 1074 break; 1075 1076 /* Set pull generic bindings */ 1077 case PIN_CONFIG_BIAS_DISABLE: 1078 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF); 1079 break; 1080 1081 case PIN_CONFIG_BIAS_PULL_DOWN: 1082 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN); 1083 break; 1084 1085 case PIN_CONFIG_BIAS_PULL_UP: 1086 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP); 1087 break; 1088 1089 /* Set output-high or output-low */ 1090 case PIN_CONFIG_OUTPUT: 1091 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); 1092 break; 1093 1094 default: 1095 return -ENOTSUPP; 1096 1097 } /* switch param type */ 1098 } /* for each config */ 1099 1100 return 0; 1101 } 1102 1103 static const struct pinconf_ops bcm2835_pinconf_ops = { 1104 .is_generic = true, 1105 .pin_config_get = bcm2835_pinconf_get, 1106 .pin_config_set = bcm2835_pinconf_set, 1107 }; 1108 1109 static int bcm2711_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, 1110 unsigned long *config) 1111 { 1112 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1113 enum pin_config_param param = pinconf_to_config_param(*config); 1114 u32 offset, shift, val; 1115 1116 offset = PUD_2711_REG_OFFSET(pin); 1117 shift = PUD_2711_REG_SHIFT(pin); 1118 val = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (offset * 4)); 1119 1120 switch (param) { 1121 case PIN_CONFIG_BIAS_DISABLE: 1122 if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_NONE) 1123 return -EINVAL; 1124 1125 break; 1126 1127 case PIN_CONFIG_BIAS_PULL_UP: 1128 if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_UP) 1129 return -EINVAL; 1130 1131 *config = pinconf_to_config_packed(param, 50000); 1132 break; 1133 1134 case PIN_CONFIG_BIAS_PULL_DOWN: 1135 if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_DOWN) 1136 return -EINVAL; 1137 1138 *config = pinconf_to_config_packed(param, 50000); 1139 break; 1140 1141 default: 1142 return bcm2835_pinconf_get(pctldev, pin, config); 1143 } 1144 1145 return 0; 1146 } 1147 1148 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc, 1149 unsigned int pin, unsigned int arg) 1150 { 1151 u32 shifter; 1152 u32 value; 1153 u32 off; 1154 1155 off = PUD_2711_REG_OFFSET(pin); 1156 shifter = PUD_2711_REG_SHIFT(pin); 1157 1158 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4)); 1159 value &= ~(PUD_2711_MASK << shifter); 1160 value |= (arg << shifter); 1161 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value); 1162 } 1163 1164 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev, 1165 unsigned int pin, unsigned long *configs, 1166 unsigned int num_configs) 1167 { 1168 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 1169 u32 param, arg; 1170 int i; 1171 1172 for (i = 0; i < num_configs; i++) { 1173 param = pinconf_to_config_param(configs[i]); 1174 arg = pinconf_to_config_argument(configs[i]); 1175 1176 switch (param) { 1177 /* convert legacy brcm,pull */ 1178 case BCM2835_PINCONF_PARAM_PULL: 1179 if (arg == BCM2835_PUD_UP) 1180 arg = BCM2711_PULL_UP; 1181 else if (arg == BCM2835_PUD_DOWN) 1182 arg = BCM2711_PULL_DOWN; 1183 else 1184 arg = BCM2711_PULL_NONE; 1185 1186 bcm2711_pull_config_set(pc, pin, arg); 1187 break; 1188 1189 /* Set pull generic bindings */ 1190 case PIN_CONFIG_BIAS_DISABLE: 1191 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE); 1192 break; 1193 case PIN_CONFIG_BIAS_PULL_DOWN: 1194 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN); 1195 break; 1196 case PIN_CONFIG_BIAS_PULL_UP: 1197 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP); 1198 break; 1199 1200 /* Set output-high or output-low */ 1201 case PIN_CONFIG_OUTPUT: 1202 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); 1203 break; 1204 1205 default: 1206 return -ENOTSUPP; 1207 } 1208 } /* for each config */ 1209 1210 return 0; 1211 } 1212 1213 static const struct pinconf_ops bcm2711_pinconf_ops = { 1214 .is_generic = true, 1215 .pin_config_get = bcm2711_pinconf_get, 1216 .pin_config_set = bcm2711_pinconf_set, 1217 }; 1218 1219 static const struct pinctrl_desc bcm2835_pinctrl_desc = { 1220 .name = MODULE_NAME, 1221 .pins = bcm2835_gpio_pins, 1222 .npins = BCM2835_NUM_GPIOS, 1223 .pctlops = &bcm2835_pctl_ops, 1224 .pmxops = &bcm2835_pmx_ops, 1225 .confops = &bcm2835_pinconf_ops, 1226 .owner = THIS_MODULE, 1227 }; 1228 1229 static const struct pinctrl_desc bcm2711_pinctrl_desc = { 1230 .name = "pinctrl-bcm2711", 1231 .pins = bcm2835_gpio_pins, 1232 .npins = BCM2711_NUM_GPIOS, 1233 .pctlops = &bcm2835_pctl_ops, 1234 .pmxops = &bcm2835_pmx_ops, 1235 .confops = &bcm2711_pinconf_ops, 1236 .owner = THIS_MODULE, 1237 }; 1238 1239 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { 1240 .name = MODULE_NAME, 1241 .npins = BCM2835_NUM_GPIOS, 1242 }; 1243 1244 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = { 1245 .name = "pinctrl-bcm2711", 1246 .npins = BCM2711_NUM_GPIOS, 1247 }; 1248 1249 struct bcm_plat_data { 1250 const struct gpio_chip *gpio_chip; 1251 const struct pinctrl_desc *pctl_desc; 1252 const struct pinctrl_gpio_range *gpio_range; 1253 }; 1254 1255 static const struct bcm_plat_data bcm2835_plat_data = { 1256 .gpio_chip = &bcm2835_gpio_chip, 1257 .pctl_desc = &bcm2835_pinctrl_desc, 1258 .gpio_range = &bcm2835_pinctrl_gpio_range, 1259 }; 1260 1261 static const struct bcm_plat_data bcm2711_plat_data = { 1262 .gpio_chip = &bcm2711_gpio_chip, 1263 .pctl_desc = &bcm2711_pinctrl_desc, 1264 .gpio_range = &bcm2711_pinctrl_gpio_range, 1265 }; 1266 1267 static const struct of_device_id bcm2835_pinctrl_match[] = { 1268 { 1269 .compatible = "brcm,bcm2835-gpio", 1270 .data = &bcm2835_plat_data, 1271 }, 1272 { 1273 .compatible = "brcm,bcm2711-gpio", 1274 .data = &bcm2711_plat_data, 1275 }, 1276 { 1277 .compatible = "brcm,bcm7211-gpio", 1278 .data = &bcm2711_plat_data, 1279 }, 1280 {} 1281 }; 1282 1283 static int bcm2835_pinctrl_probe(struct platform_device *pdev) 1284 { 1285 struct device *dev = &pdev->dev; 1286 struct device_node *np = dev->of_node; 1287 const struct bcm_plat_data *pdata; 1288 struct bcm2835_pinctrl *pc; 1289 struct gpio_irq_chip *girq; 1290 struct resource iomem; 1291 int err, i; 1292 const struct of_device_id *match; 1293 int is_7211 = 0; 1294 1295 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS); 1296 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS); 1297 1298 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); 1299 if (!pc) 1300 return -ENOMEM; 1301 1302 platform_set_drvdata(pdev, pc); 1303 pc->dev = dev; 1304 1305 err = of_address_to_resource(np, 0, &iomem); 1306 if (err) { 1307 dev_err(dev, "could not get IO memory\n"); 1308 return err; 1309 } 1310 1311 pc->base = devm_ioremap_resource(dev, &iomem); 1312 if (IS_ERR(pc->base)) 1313 return PTR_ERR(pc->base); 1314 1315 match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node); 1316 if (!match) 1317 return -EINVAL; 1318 1319 pdata = match->data; 1320 is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio"); 1321 1322 pc->gpio_chip = *pdata->gpio_chip; 1323 pc->gpio_chip.parent = dev; 1324 1325 spin_lock_init(&pc->fsel_lock); 1326 for (i = 0; i < BCM2835_NUM_BANKS; i++) { 1327 unsigned long events; 1328 unsigned offset; 1329 1330 /* clear event detection flags */ 1331 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); 1332 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0); 1333 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0); 1334 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0); 1335 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0); 1336 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0); 1337 1338 /* clear all the events */ 1339 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4); 1340 for_each_set_bit(offset, &events, 32) 1341 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); 1342 1343 raw_spin_lock_init(&pc->irq_lock[i]); 1344 } 1345 1346 pc->pctl_desc = *pdata->pctl_desc; 1347 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); 1348 if (IS_ERR(pc->pctl_dev)) { 1349 gpiochip_remove(&pc->gpio_chip); 1350 return PTR_ERR(pc->pctl_dev); 1351 } 1352 1353 pc->gpio_range = *pdata->gpio_range; 1354 pc->gpio_range.base = pc->gpio_chip.base; 1355 pc->gpio_range.gc = &pc->gpio_chip; 1356 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range); 1357 1358 girq = &pc->gpio_chip.irq; 1359 gpio_irq_chip_set_chip(girq, &bcm2835_gpio_irq_chip); 1360 girq->parent_handler = bcm2835_gpio_irq_handler; 1361 girq->num_parents = BCM2835_NUM_IRQS; 1362 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS, 1363 sizeof(*girq->parents), 1364 GFP_KERNEL); 1365 if (!girq->parents) { 1366 err = -ENOMEM; 1367 goto out_remove; 1368 } 1369 1370 if (is_7211) { 1371 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS, 1372 sizeof(*pc->wake_irq), 1373 GFP_KERNEL); 1374 if (!pc->wake_irq) { 1375 err = -ENOMEM; 1376 goto out_remove; 1377 } 1378 } 1379 1380 /* 1381 * Use the same handler for all groups: this is necessary 1382 * since we use one gpiochip to cover all lines - the 1383 * irq handler then needs to figure out which group and 1384 * bank that was firing the IRQ and look up the per-group 1385 * and bank data. 1386 */ 1387 for (i = 0; i < BCM2835_NUM_IRQS; i++) { 1388 int len; 1389 char *name; 1390 1391 girq->parents[i] = irq_of_parse_and_map(np, i); 1392 if (!is_7211) { 1393 if (!girq->parents[i]) { 1394 girq->num_parents = i; 1395 break; 1396 } 1397 continue; 1398 } 1399 /* Skip over the all banks interrupts */ 1400 pc->wake_irq[i] = irq_of_parse_and_map(np, i + 1401 BCM2835_NUM_IRQS + 1); 1402 1403 len = strlen(dev_name(pc->dev)) + 16; 1404 name = devm_kzalloc(pc->dev, len, GFP_KERNEL); 1405 if (!name) { 1406 err = -ENOMEM; 1407 goto out_remove; 1408 } 1409 1410 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i); 1411 1412 /* These are optional interrupts */ 1413 err = devm_request_irq(dev, pc->wake_irq[i], 1414 bcm2835_gpio_wake_irq_handler, 1415 IRQF_SHARED, name, pc); 1416 if (err) 1417 dev_warn(dev, "unable to request wake IRQ %d\n", 1418 pc->wake_irq[i]); 1419 } 1420 1421 girq->default_type = IRQ_TYPE_NONE; 1422 girq->handler = handle_level_irq; 1423 1424 err = gpiochip_add_data(&pc->gpio_chip, pc); 1425 if (err) { 1426 dev_err(dev, "could not add GPIO chip\n"); 1427 goto out_remove; 1428 } 1429 1430 dev_info(dev, "GPIO_OUT persistence: %s\n", 1431 persist_gpio_outputs ? "yes" : "no"); 1432 1433 return 0; 1434 1435 out_remove: 1436 pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range); 1437 return err; 1438 } 1439 1440 static struct platform_driver bcm2835_pinctrl_driver = { 1441 .probe = bcm2835_pinctrl_probe, 1442 .driver = { 1443 .name = MODULE_NAME, 1444 .of_match_table = bcm2835_pinctrl_match, 1445 .suppress_bind_attrs = true, 1446 }, 1447 }; 1448 module_platform_driver(bcm2835_pinctrl_driver); 1449 1450 MODULE_AUTHOR("Chris Boot"); 1451 MODULE_AUTHOR("Simon Arlott"); 1452 MODULE_AUTHOR("Stephen Warren"); 1453 MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver"); 1454 MODULE_LICENSE("GPL"); 1455