1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 IBM Corp. 4 */ 5 #include <linux/bitops.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/platform_device.h> 11 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/pinctrl/pinmux.h> 13 #include <linux/pinctrl/pinconf.h> 14 #include <linux/pinctrl/pinconf-generic.h> 15 #include <linux/types.h> 16 17 #include "../core.h" 18 #include "../pinctrl-utils.h" 19 #include "pinmux-aspeed.h" 20 #include "pinctrl-aspeed.h" 21 22 /* Wrap some of the common macros for clarity */ 23 #define SIG_EXPR_DECL_SINGLE(sig, func, ...) \ 24 SIG_EXPR_DECL(sig, func, func, __VA_ARGS__) 25 26 #define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG 27 #define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG 28 29 /* 30 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet 31 * references registers by the device/offset mnemonic. The register macros 32 * below are named the same way to ease transcription and verification (as 33 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions 34 * reference registers beyond those dedicated to pinmux, such as the system 35 * reset control and MAC clock configuration registers. 36 */ 37 #define SCU2C 0x2C /* Misc. Control Register */ 38 #define SCU3C 0x3C /* System Reset Control/Status Register */ 39 #define SCU48 0x48 /* MAC Interface Clock Delay Setting */ 40 #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */ 41 #define HW_REVISION_ID 0x7C /* Silicon revision ID register */ 42 #define SCU80 0x80 /* Multi-function Pin Control #1 */ 43 #define SCU84 0x84 /* Multi-function Pin Control #2 */ 44 #define SCU88 0x88 /* Multi-function Pin Control #3 */ 45 #define SCU8C 0x8C /* Multi-function Pin Control #4 */ 46 #define SCU90 0x90 /* Multi-function Pin Control #5 */ 47 #define SCU94 0x94 /* Multi-function Pin Control #6 */ 48 #define SCUA0 0xA0 /* Multi-function Pin Control #7 */ 49 #define SCUA4 0xA4 /* Multi-function Pin Control #8 */ 50 #define SCUA8 0xA8 /* Multi-function Pin Control #9 */ 51 #define SCUAC 0xAC /* Multi-function Pin Control #10 */ 52 #define HW_STRAP2 0xD0 /* Strapping */ 53 54 /* 55 * Uses undefined macros for symbol naming and references, eg GPIOA0, MAC1LINK, 56 * TIMER3 etc. 57 * 58 * Pins are defined in GPIO bank order: 59 * 60 * GPIOA0: 0 61 * ... 62 * GPIOA7: 7 63 * GPIOB0: 8 64 * ... 65 * GPIOZ7: 207 66 * GPIOAA0: 208 67 * ... 68 * GPIOAB3: 219 69 * 70 * Not all pins have their signals defined (yet). 71 */ 72 73 #define D6 0 74 SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); 75 76 #define B5 1 77 SSSF_PIN_DECL(B5, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1)); 78 79 #define A4 2 80 SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); 81 82 #define E6 3 83 SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); 84 85 #define I2C9_DESC SIG_DESC_SET(SCU90, 22) 86 87 #define C5 4 88 SIG_EXPR_LIST_DECL_SINGLE(C5, SCL9, I2C9, I2C9_DESC); 89 SIG_EXPR_LIST_DECL_SINGLE(C5, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4)); 90 PIN_DECL_2(C5, GPIOA4, SCL9, TIMER5); 91 92 FUNC_GROUP_DECL(TIMER5, C5); 93 94 #define B4 5 95 SIG_EXPR_LIST_DECL_SINGLE(B4, SDA9, I2C9, I2C9_DESC); 96 SIG_EXPR_LIST_DECL_SINGLE(B4, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5)); 97 PIN_DECL_2(B4, GPIOA5, SDA9, TIMER6); 98 99 FUNC_GROUP_DECL(TIMER6, B4); 100 FUNC_GROUP_DECL(I2C9, C5, B4); 101 102 #define MDIO2_DESC SIG_DESC_SET(SCU90, 2) 103 104 #define A3 6 105 SIG_EXPR_LIST_DECL_SINGLE(A3, MDC2, MDIO2, MDIO2_DESC); 106 SIG_EXPR_LIST_DECL_SINGLE(A3, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6)); 107 PIN_DECL_2(A3, GPIOA6, MDC2, TIMER7); 108 109 FUNC_GROUP_DECL(TIMER7, A3); 110 111 #define D5 7 112 SIG_EXPR_LIST_DECL_SINGLE(D5, MDIO2, MDIO2, MDIO2_DESC); 113 SIG_EXPR_LIST_DECL_SINGLE(D5, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7)); 114 PIN_DECL_2(D5, GPIOA7, MDIO2, TIMER8); 115 116 FUNC_GROUP_DECL(TIMER8, D5); 117 FUNC_GROUP_DECL(MDIO2, A3, D5); 118 119 #define J21 8 120 SSSF_PIN_DECL(J21, GPIOB0, SALT1, SIG_DESC_SET(SCU80, 8)); 121 122 #define J20 9 123 SSSF_PIN_DECL(J20, GPIOB1, SALT2, SIG_DESC_SET(SCU80, 9)); 124 125 #define H18 10 126 SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10)); 127 128 #define F18 11 129 SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11)); 130 131 #define E19 12 132 SIG_EXPR_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12)); 133 SIG_EXPR_DECL_SINGLE(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14)); 134 SIG_EXPR_LIST_DECL_DUAL(E19, LPCRST, LPCRST, LPCRSTS); 135 PIN_DECL_1(E19, GPIOB4, LPCRST); 136 137 FUNC_GROUP_DECL(LPCRST, E19); 138 139 #define H19 13 140 #define H19_DESC SIG_DESC_SET(SCU80, 13) 141 SIG_EXPR_LIST_DECL_SINGLE(H19, LPCPD, LPCPD, H19_DESC); 142 SIG_EXPR_LIST_DECL_SINGLE(H19, LPCSMI, LPCSMI, H19_DESC); 143 PIN_DECL_2(H19, GPIOB5, LPCPD, LPCSMI); 144 145 FUNC_GROUP_DECL(LPCPD, H19); 146 FUNC_GROUP_DECL(LPCSMI, H19); 147 148 #define H20 14 149 SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); 150 151 #define E18 15 152 SIG_EXPR_LIST_DECL_SINGLE(E18, EXTRST, EXTRST, 153 SIG_DESC_SET(SCU80, 15), 154 SIG_DESC_BIT(SCU90, 31, 0), 155 SIG_DESC_SET(SCU3C, 3)); 156 SIG_EXPR_LIST_DECL_SINGLE(E18, SPICS1, SPICS1, 157 SIG_DESC_SET(SCU80, 15), 158 SIG_DESC_SET(SCU90, 31)); 159 PIN_DECL_2(E18, GPIOB7, EXTRST, SPICS1); 160 161 FUNC_GROUP_DECL(EXTRST, E18); 162 FUNC_GROUP_DECL(SPICS1, E18); 163 164 #define SD1_DESC SIG_DESC_SET(SCU90, 0) 165 #define I2C10_DESC SIG_DESC_SET(SCU90, 23) 166 167 #define C4 16 168 SIG_EXPR_LIST_DECL_SINGLE(C4, SD1CLK, SD1, SD1_DESC); 169 SIG_EXPR_LIST_DECL_SINGLE(C4, SCL10, I2C10, I2C10_DESC); 170 PIN_DECL_2(C4, GPIOC0, SD1CLK, SCL10); 171 172 #define B3 17 173 SIG_EXPR_LIST_DECL_SINGLE(B3, SD1CMD, SD1, SD1_DESC); 174 SIG_EXPR_LIST_DECL_SINGLE(B3, SDA10, I2C10, I2C10_DESC); 175 PIN_DECL_2(B3, GPIOC1, SD1CMD, SDA10); 176 177 FUNC_GROUP_DECL(I2C10, C4, B3); 178 179 #define I2C11_DESC SIG_DESC_SET(SCU90, 24) 180 181 #define A2 18 182 SIG_EXPR_LIST_DECL_SINGLE(A2, SD1DAT0, SD1, SD1_DESC); 183 SIG_EXPR_LIST_DECL_SINGLE(A2, SCL11, I2C11, I2C11_DESC); 184 PIN_DECL_2(A2, GPIOC2, SD1DAT0, SCL11); 185 186 #define E5 19 187 SIG_EXPR_LIST_DECL_SINGLE(E5, SD1DAT1, SD1, SD1_DESC); 188 SIG_EXPR_LIST_DECL_SINGLE(E5, SDA11, I2C11, I2C11_DESC); 189 PIN_DECL_2(E5, GPIOC3, SD1DAT1, SDA11); 190 191 FUNC_GROUP_DECL(I2C11, A2, E5); 192 193 #define I2C12_DESC SIG_DESC_SET(SCU90, 25) 194 195 #define D4 20 196 SIG_EXPR_LIST_DECL_SINGLE(D4, SD1DAT2, SD1, SD1_DESC); 197 SIG_EXPR_LIST_DECL_SINGLE(D4, SCL12, I2C12, I2C12_DESC); 198 PIN_DECL_2(D4, GPIOC4, SD1DAT2, SCL12); 199 200 #define C3 21 201 SIG_EXPR_LIST_DECL_SINGLE(C3, SD1DAT3, SD1, SD1_DESC); 202 SIG_EXPR_LIST_DECL_SINGLE(C3, SDA12, I2C12, I2C12_DESC); 203 PIN_DECL_2(C3, GPIOC5, SD1DAT3, SDA12); 204 205 FUNC_GROUP_DECL(I2C12, D4, C3); 206 207 #define I2C13_DESC SIG_DESC_SET(SCU90, 26) 208 209 #define B2 22 210 SIG_EXPR_LIST_DECL_SINGLE(B2, SD1CD, SD1, SD1_DESC); 211 SIG_EXPR_LIST_DECL_SINGLE(B2, SCL13, I2C13, I2C13_DESC); 212 PIN_DECL_2(B2, GPIOC6, SD1CD, SCL13); 213 214 #define A1 23 215 SIG_EXPR_LIST_DECL_SINGLE(A1, SD1WP, SD1, SD1_DESC); 216 SIG_EXPR_LIST_DECL_SINGLE(A1, SDA13, I2C13, I2C13_DESC); 217 PIN_DECL_2(A1, GPIOC7, SD1WP, SDA13); 218 219 FUNC_GROUP_DECL(I2C13, B2, A1); 220 FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1); 221 222 #define SD2_DESC SIG_DESC_SET(SCU90, 1) 223 #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) 224 #define GPID0_DESC SIG_DESC_SET(SCU8C, 8) 225 226 #define A18 24 227 SIG_EXPR_LIST_DECL_SINGLE(A18, SD2CLK, SD2, SD2_DESC); 228 SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC); 229 SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC); 230 SIG_EXPR_LIST_DECL_DUAL(A18, GPID0IN, GPID0, GPID); 231 PIN_DECL_2(A18, GPIOD0, SD2CLK, GPID0IN); 232 233 #define D16 25 234 SIG_EXPR_LIST_DECL_SINGLE(D16, SD2CMD, SD2, SD2_DESC); 235 SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC); 236 SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC); 237 SIG_EXPR_LIST_DECL_DUAL(D16, GPID0OUT, GPID0, GPID); 238 PIN_DECL_2(D16, GPIOD1, SD2CMD, GPID0OUT); 239 240 FUNC_GROUP_DECL(GPID0, A18, D16); 241 242 #define GPID2_DESC SIG_DESC_SET(SCU8C, 9) 243 244 #define B17 26 245 SIG_EXPR_LIST_DECL_SINGLE(B17, SD2DAT0, SD2, SD2_DESC); 246 SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC); 247 SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC); 248 SIG_EXPR_LIST_DECL_DUAL(B17, GPID2IN, GPID2, GPID); 249 PIN_DECL_2(B17, GPIOD2, SD2DAT0, GPID2IN); 250 251 #define A17 27 252 SIG_EXPR_LIST_DECL_SINGLE(A17, SD2DAT1, SD2, SD2_DESC); 253 SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC); 254 SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC); 255 SIG_EXPR_LIST_DECL_DUAL(A17, GPID2OUT, GPID2, GPID); 256 PIN_DECL_2(A17, GPIOD3, SD2DAT1, GPID2OUT); 257 258 FUNC_GROUP_DECL(GPID2, B17, A17); 259 260 #define GPID4_DESC SIG_DESC_SET(SCU8C, 10) 261 262 #define C16 28 263 SIG_EXPR_LIST_DECL_SINGLE(C16, SD2DAT2, SD2, SD2_DESC); 264 SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC); 265 SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC); 266 SIG_EXPR_LIST_DECL_DUAL(C16, GPID4IN, GPID4, GPID); 267 PIN_DECL_2(C16, GPIOD4, SD2DAT2, GPID4IN); 268 269 #define B16 29 270 SIG_EXPR_LIST_DECL_SINGLE(B16, SD2DAT3, SD2, SD2_DESC); 271 SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC); 272 SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC); 273 SIG_EXPR_LIST_DECL_DUAL(B16, GPID4OUT, GPID4, GPID); 274 PIN_DECL_2(B16, GPIOD5, SD2DAT3, GPID4OUT); 275 276 FUNC_GROUP_DECL(GPID4, C16, B16); 277 278 #define GPID6_DESC SIG_DESC_SET(SCU8C, 11) 279 280 #define A16 30 281 SIG_EXPR_LIST_DECL_SINGLE(A16, SD2CD, SD2, SD2_DESC); 282 SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC); 283 SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC); 284 SIG_EXPR_LIST_DECL_DUAL(A16, GPID6IN, GPID6, GPID); 285 PIN_DECL_2(A16, GPIOD6, SD2CD, GPID6IN); 286 287 #define E15 31 288 SIG_EXPR_LIST_DECL_SINGLE(E15, SD2WP, SD2, SD2_DESC); 289 SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC); 290 SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC); 291 SIG_EXPR_LIST_DECL_DUAL(E15, GPID6OUT, GPID6, GPID); 292 PIN_DECL_2(E15, GPIOD7, SD2WP, GPID6OUT); 293 294 FUNC_GROUP_DECL(GPID6, A16, E15); 295 FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15); 296 FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15); 297 298 #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) 299 #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) 300 #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) 301 #define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) 302 #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) 303 304 #define D15 32 305 SIG_EXPR_LIST_DECL_SINGLE(D15, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); 306 SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC); 307 SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC); 308 SIG_EXPR_LIST_DECL_DUAL(D15, GPIE0IN, GPIE0, GPIE); 309 PIN_DECL_2(D15, GPIOE0, NCTS3, GPIE0IN); 310 311 FUNC_GROUP_DECL(NCTS3, D15); 312 313 #define C15 33 314 SIG_EXPR_LIST_DECL_SINGLE(C15, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); 315 SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC); 316 SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC); 317 SIG_EXPR_LIST_DECL_DUAL(C15, GPIE0OUT, GPIE0, GPIE); 318 PIN_DECL_2(C15, GPIOE1, NDCD3, GPIE0OUT); 319 320 FUNC_GROUP_DECL(NDCD3, C15); 321 FUNC_GROUP_DECL(GPIE0, D15, C15); 322 323 #define B15 34 324 SIG_EXPR_LIST_DECL_SINGLE(B15, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); 325 SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC); 326 SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC); 327 SIG_EXPR_LIST_DECL_DUAL(B15, GPIE2IN, GPIE2, GPIE); 328 PIN_DECL_2(B15, GPIOE2, NDSR3, GPIE2IN); 329 330 FUNC_GROUP_DECL(NDSR3, B15); 331 332 #define A15 35 333 SIG_EXPR_LIST_DECL_SINGLE(A15, NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); 334 SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC); 335 SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC); 336 SIG_EXPR_LIST_DECL_DUAL(A15, GPIE2OUT, GPIE2, GPIE); 337 PIN_DECL_2(A15, GPIOE3, NRI3, GPIE2OUT); 338 339 FUNC_GROUP_DECL(NRI3, A15); 340 FUNC_GROUP_DECL(GPIE2, B15, A15); 341 342 #define E14 36 343 SIG_EXPR_LIST_DECL_SINGLE(E14, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); 344 SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC); 345 SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC); 346 SIG_EXPR_LIST_DECL_DUAL(E14, GPIE4IN, GPIE4, GPIE); 347 PIN_DECL_2(E14, GPIOE4, NDTR3, GPIE4IN); 348 349 FUNC_GROUP_DECL(NDTR3, E14); 350 351 #define D14 37 352 SIG_EXPR_LIST_DECL_SINGLE(D14, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); 353 SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC); 354 SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC); 355 SIG_EXPR_LIST_DECL_DUAL(D14, GPIE4OUT, GPIE4, GPIE); 356 PIN_DECL_2(D14, GPIOE5, NRTS3, GPIE4OUT); 357 358 FUNC_GROUP_DECL(NRTS3, D14); 359 FUNC_GROUP_DECL(GPIE4, E14, D14); 360 361 #define C14 38 362 SIG_EXPR_LIST_DECL_SINGLE(C14, TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); 363 SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC); 364 SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC); 365 SIG_EXPR_LIST_DECL_DUAL(C14, GPIE6IN, GPIE6, GPIE); 366 PIN_DECL_2(C14, GPIOE6, TXD3, GPIE6IN); 367 368 FUNC_GROUP_DECL(TXD3, C14); 369 370 #define B14 39 371 SIG_EXPR_LIST_DECL_SINGLE(B14, RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); 372 SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC); 373 SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC); 374 SIG_EXPR_LIST_DECL_DUAL(B14, GPIE6OUT, GPIE6, GPIE); 375 PIN_DECL_2(B14, GPIOE7, RXD3, GPIE6OUT); 376 377 FUNC_GROUP_DECL(RXD3, B14); 378 FUNC_GROUP_DECL(GPIE6, C14, B14); 379 380 #define D18 40 381 SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24)); 382 383 #define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0) 384 385 #define B19 41 386 SIG_EXPR_LIST_DECL_SINGLE(B19, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); 387 SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12)); 388 SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, ACPI_DESC); 389 SIG_EXPR_LIST_DECL_DUAL(B19, SIOPBI, SIOPBI, ACPI); 390 PIN_DECL_2(B19, GPIOF1, NDCD4, SIOPBI); 391 FUNC_GROUP_DECL(NDCD4, B19); 392 FUNC_GROUP_DECL(SIOPBI, B19); 393 394 #define A20 42 395 SIG_EXPR_LIST_DECL_SINGLE(A20, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); 396 SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12)); 397 SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, ACPI_DESC); 398 SIG_EXPR_LIST_DECL_DUAL(A20, SIOPWRGD, SIOPWRGD, ACPI); 399 PIN_DECL_2(A20, GPIOF2, NDSR4, SIOPWRGD); 400 FUNC_GROUP_DECL(NDSR4, A20); 401 FUNC_GROUP_DECL(SIOPWRGD, A20); 402 403 #define D17 43 404 SIG_EXPR_LIST_DECL_SINGLE(D17, NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); 405 SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); 406 SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, ACPI_DESC); 407 SIG_EXPR_LIST_DECL_DUAL(D17, SIOPBO, SIOPBO, ACPI); 408 PIN_DECL_2(D17, GPIOF3, NRI4, SIOPBO); 409 FUNC_GROUP_DECL(NRI4, D17); 410 FUNC_GROUP_DECL(SIOPBO, D17); 411 412 #define B18 44 413 SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28)); 414 415 #define A19 45 416 SIG_EXPR_LIST_DECL_SINGLE(A19, NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29)); 417 SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15)); 418 SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, ACPI_DESC); 419 SIG_EXPR_LIST_DECL_DUAL(A19, SIOSCI, SIOSCI, ACPI); 420 PIN_DECL_2(A19, GPIOF5, NDTS4, SIOSCI); 421 FUNC_GROUP_DECL(NDTS4, A19); 422 FUNC_GROUP_DECL(SIOSCI, A19); 423 424 #define E16 46 425 SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30)); 426 427 #define C17 47 428 SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31)); 429 430 #define A14 48 431 SSSF_PIN_DECL(A14, GPIOG0, SGPSCK, SIG_DESC_SET(SCU84, 0)); 432 433 #define E13 49 434 SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1)); 435 436 #define D13 50 437 SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2)); 438 439 #define C13 51 440 SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3)); 441 442 #define B13 52 443 SIG_EXPR_LIST_DECL_SINGLE(B13, OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1)); 444 SIG_EXPR_LIST_DECL_SINGLE(B13, WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4)); 445 PIN_DECL_2(B13, GPIOG4, OSCCLK, WDTRST1); 446 447 FUNC_GROUP_DECL(OSCCLK, B13); 448 FUNC_GROUP_DECL(WDTRST1, B13); 449 450 #define Y21 53 451 SIG_EXPR_LIST_DECL_SINGLE(Y21, USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); 452 SIG_EXPR_LIST_DECL_SINGLE(Y21, WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5)); 453 PIN_DECL_2(Y21, GPIOG5, USBCKI, WDTRST2); 454 455 FUNC_GROUP_DECL(USBCKI, Y21); 456 FUNC_GROUP_DECL(WDTRST2, Y21); 457 458 #define AA22 54 459 SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6)); 460 461 #define U18 55 462 SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7)); 463 464 #define UART6_DESC SIG_DESC_SET(SCU90, 7) 465 #define ROM16_DESC SIG_DESC_SET(SCU90, 6) 466 #define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4) 467 #define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 } 468 469 #define A8 56 470 SIG_EXPR_DECL_SINGLE(ROMD8, ROM16, ROM16_DESC); 471 SIG_EXPR_DECL_SINGLE(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 472 SIG_EXPR_LIST_DECL_DUAL(A8, ROMD8, ROM16, ROM16S); 473 SIG_EXPR_LIST_DECL_SINGLE(A8, NCTS6, NCTS6, UART6_DESC); 474 PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6); 475 476 #define C7 57 477 SIG_EXPR_DECL_SINGLE(ROMD9, ROM16, ROM16_DESC); 478 SIG_EXPR_DECL_SINGLE(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 479 SIG_EXPR_LIST_DECL_DUAL(C7, ROMD9, ROM16, ROM16S); 480 SIG_EXPR_LIST_DECL_SINGLE(C7, NDCD6, NDCD6, UART6_DESC); 481 PIN_DECL_2(C7, GPIOH1, ROMD9, NDCD6); 482 483 #define B7 58 484 SIG_EXPR_DECL_SINGLE(ROMD10, ROM16, ROM16_DESC); 485 SIG_EXPR_DECL_SINGLE(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 486 SIG_EXPR_LIST_DECL_DUAL(B7, ROMD10, ROM16, ROM16S); 487 SIG_EXPR_LIST_DECL_SINGLE(B7, NDSR6, NDSR6, UART6_DESC); 488 PIN_DECL_2(B7, GPIOH2, ROMD10, NDSR6); 489 490 #define A7 59 491 SIG_EXPR_DECL_SINGLE(ROMD11, ROM16, ROM16_DESC); 492 SIG_EXPR_DECL_SINGLE(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 493 SIG_EXPR_LIST_DECL_DUAL(A7, ROMD11, ROM16, ROM16S); 494 SIG_EXPR_LIST_DECL_SINGLE(A7, NRI6, NRI6, UART6_DESC); 495 PIN_DECL_2(A7, GPIOH3, ROMD11, NRI6); 496 497 #define D7 60 498 SIG_EXPR_DECL_SINGLE(ROMD12, ROM16, ROM16_DESC); 499 SIG_EXPR_DECL_SINGLE(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 500 SIG_EXPR_LIST_DECL_DUAL(D7, ROMD12, ROM16, ROM16S); 501 SIG_EXPR_LIST_DECL_SINGLE(D7, NDTR6, NDTR6, UART6_DESC); 502 PIN_DECL_2(D7, GPIOH4, ROMD12, NDTR6); 503 504 #define B6 61 505 SIG_EXPR_DECL_SINGLE(ROMD13, ROM16, ROM16_DESC); 506 SIG_EXPR_DECL_SINGLE(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 507 SIG_EXPR_LIST_DECL_DUAL(B6, ROMD13, ROM16, ROM16S); 508 SIG_EXPR_LIST_DECL_SINGLE(B6, NRTS6, NRTS6, UART6_DESC); 509 PIN_DECL_2(B6, GPIOH5, ROMD13, NRTS6); 510 511 #define A6 62 512 SIG_EXPR_DECL_SINGLE(ROMD14, ROM16, ROM16_DESC); 513 SIG_EXPR_DECL_SINGLE(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 514 SIG_EXPR_LIST_DECL_DUAL(A6, ROMD14, ROM16, ROM16S); 515 SIG_EXPR_LIST_DECL_SINGLE(A6, TXD6, TXD6, UART6_DESC); 516 PIN_DECL_2(A6, GPIOH6, ROMD14, TXD6); 517 518 #define E7 63 519 SIG_EXPR_DECL_SINGLE(ROMD15, ROM16, ROM16_DESC); 520 SIG_EXPR_DECL_SINGLE(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); 521 SIG_EXPR_LIST_DECL_DUAL(E7, ROMD15, ROM16, ROM16S); 522 SIG_EXPR_LIST_DECL_SINGLE(E7, RXD6, RXD6, UART6_DESC); 523 PIN_DECL_2(E7, GPIOH7, ROMD15, RXD6); 524 525 FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); 526 527 #define SPI1_DESC \ 528 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 } 529 #define SPI1DEBUG_DESC \ 530 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 } 531 #define SPI1PASSTHRU_DESC \ 532 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } 533 534 #define C22 64 535 SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC); 536 SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 537 SIG_EXPR_LIST_DECL_DUAL(C22, SYSCS, SPI1DEBUG, SPI1PASSTHRU); 538 PIN_DECL_1(C22, GPIOI0, SYSCS); 539 540 #define G18 65 541 SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC); 542 SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 543 SIG_EXPR_LIST_DECL_DUAL(G18, SYSCK, SPI1DEBUG, SPI1PASSTHRU); 544 PIN_DECL_1(G18, GPIOI1, SYSCK); 545 546 #define D19 66 547 SIG_EXPR_DECL_SINGLE(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC); 548 SIG_EXPR_DECL_SINGLE(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 549 SIG_EXPR_LIST_DECL_DUAL(D19, SYSDO, SPI1DEBUG, SPI1PASSTHRU); 550 PIN_DECL_1(D19, GPIOI2, SYSDO); 551 552 #define C20 67 553 SIG_EXPR_DECL_SINGLE(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC); 554 SIG_EXPR_DECL_SINGLE(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 555 SIG_EXPR_LIST_DECL_DUAL(C20, SYSDI, SPI1DEBUG, SPI1PASSTHRU); 556 PIN_DECL_1(C20, GPIOI3, SYSDI); 557 558 #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) 559 560 #define B22 68 561 SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, SPI1_DESC); 562 SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC); 563 SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 564 SIG_EXPR_LIST_DECL(SPI1CS0, SPI1, 565 SIG_EXPR_PTR(SPI1CS0, SPI1), 566 SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), 567 SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); 568 SIG_EXPR_LIST_ALIAS(B22, SPI1CS0, SPI1); 569 SIG_EXPR_LIST_DECL_SINGLE(B22, VBCS, VGABIOS_ROM, VB_DESC); 570 PIN_DECL_2(B22, GPIOI4, SPI1CS0, VBCS); 571 572 #define G19 69 573 SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, SPI1_DESC); 574 SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC); 575 SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 576 SIG_EXPR_LIST_DECL(SPI1CK, SPI1, 577 SIG_EXPR_PTR(SPI1CK, SPI1), 578 SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), 579 SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); 580 SIG_EXPR_LIST_ALIAS(G19, SPI1CK, SPI1); 581 SIG_EXPR_LIST_DECL_SINGLE(G19, VBCK, VGABIOS_ROM, VB_DESC); 582 PIN_DECL_2(G19, GPIOI5, SPI1CK, VBCK); 583 584 #define C18 70 585 SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1, SPI1_DESC); 586 SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC); 587 SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 588 SIG_EXPR_LIST_DECL(SPI1DO, SPI1, 589 SIG_EXPR_PTR(SPI1DO, SPI1), 590 SIG_EXPR_PTR(SPI1DO, SPI1DEBUG), 591 SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU)); 592 SIG_EXPR_LIST_ALIAS(C18, SPI1DO, SPI1); 593 SIG_EXPR_LIST_DECL_SINGLE(C18, VBDO, VGABIOS_ROM, VB_DESC); 594 PIN_DECL_2(C18, GPIOI6, SPI1DO, VBDO); 595 596 #define E20 71 597 SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1, SPI1_DESC); 598 SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC); 599 SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); 600 SIG_EXPR_LIST_DECL(SPI1DI, SPI1, 601 SIG_EXPR_PTR(SPI1DI, SPI1), 602 SIG_EXPR_PTR(SPI1DI, SPI1DEBUG), 603 SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU)); 604 SIG_EXPR_LIST_ALIAS(E20, SPI1DI, SPI1); 605 SIG_EXPR_LIST_DECL_SINGLE(E20, VBDI, VGABIOS_ROM, VB_DESC); 606 PIN_DECL_2(E20, GPIOI7, SPI1DI, VBDI); 607 608 FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20); 609 FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20); 610 FUNC_GROUP_DECL(SPI1PASSTHRU, C22, G18, D19, C20, B22, G19, C18, E20); 611 FUNC_GROUP_DECL(VGABIOS_ROM, B22, G19, C18, E20); 612 613 #define J5 72 614 SSSF_PIN_DECL(J5, GPIOJ0, SGPMCK, SIG_DESC_SET(SCU84, 8)); 615 616 #define J4 73 617 SSSF_PIN_DECL(J4, GPIOJ1, SGPMLD, SIG_DESC_SET(SCU84, 9)); 618 619 #define K5 74 620 SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10)); 621 622 #define J3 75 623 SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11)); 624 625 #define T4 76 626 SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12)); 627 628 #define U2 77 629 SSSF_PIN_DECL(U2, GPIOJ5, VGAVS, SIG_DESC_SET(SCU84, 13)); 630 631 #define T2 78 632 SSSF_PIN_DECL(T2, GPIOJ6, DDCCLK, SIG_DESC_SET(SCU84, 14)); 633 634 #define T1 79 635 SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15)); 636 637 #define I2C5_DESC SIG_DESC_SET(SCU90, 18) 638 639 #define E3 80 640 SIG_EXPR_LIST_DECL_SINGLE(E3, SCL5, I2C5, I2C5_DESC); 641 PIN_DECL_1(E3, GPIOK0, SCL5); 642 643 #define D2 81 644 SIG_EXPR_LIST_DECL_SINGLE(D2, SDA5, I2C5, I2C5_DESC); 645 PIN_DECL_1(D2, GPIOK1, SDA5); 646 647 FUNC_GROUP_DECL(I2C5, E3, D2); 648 649 #define I2C6_DESC SIG_DESC_SET(SCU90, 19) 650 651 #define C1 82 652 SIG_EXPR_LIST_DECL_SINGLE(C1, SCL6, I2C6, I2C6_DESC); 653 PIN_DECL_1(C1, GPIOK2, SCL6); 654 655 #define F4 83 656 SIG_EXPR_LIST_DECL_SINGLE(F4, SDA6, I2C6, I2C6_DESC); 657 PIN_DECL_1(F4, GPIOK3, SDA6); 658 659 FUNC_GROUP_DECL(I2C6, C1, F4); 660 661 #define I2C7_DESC SIG_DESC_SET(SCU90, 20) 662 663 #define E2 84 664 SIG_EXPR_LIST_DECL_SINGLE(E2, SCL7, I2C7, I2C7_DESC); 665 PIN_DECL_1(E2, GPIOK4, SCL7); 666 667 #define D1 85 668 SIG_EXPR_LIST_DECL_SINGLE(D1, SDA7, I2C7, I2C7_DESC); 669 PIN_DECL_1(D1, GPIOK5, SDA7); 670 671 FUNC_GROUP_DECL(I2C7, E2, D1); 672 673 #define I2C8_DESC SIG_DESC_SET(SCU90, 21) 674 675 #define G5 86 676 SIG_EXPR_LIST_DECL_SINGLE(G5, SCL8, I2C8, I2C8_DESC); 677 PIN_DECL_1(G5, GPIOK6, SCL8); 678 679 #define F3 87 680 SIG_EXPR_LIST_DECL_SINGLE(F3, SDA8, I2C8, I2C8_DESC); 681 PIN_DECL_1(F3, GPIOK7, SDA8); 682 683 FUNC_GROUP_DECL(I2C8, G5, F3); 684 685 #define U1 88 686 SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); 687 688 #define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } 689 #define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } 690 #define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } 691 692 #define T5 89 693 #define T5_DESC SIG_DESC_SET(SCU84, 17) 694 SIG_EXPR_DECL_SINGLE(VPIDE, VPI18, VPI18_DESC, T5_DESC); 695 SIG_EXPR_DECL_SINGLE(VPIDE, VPI24, VPI24_DESC, T5_DESC); 696 SIG_EXPR_DECL_SINGLE(VPIDE, VPI30, VPI30_DESC, T5_DESC); 697 SIG_EXPR_LIST_DECL(VPIDE, VPI, 698 SIG_EXPR_PTR(VPIDE, VPI18), 699 SIG_EXPR_PTR(VPIDE, VPI24), 700 SIG_EXPR_PTR(VPIDE, VPI30)); 701 SIG_EXPR_LIST_ALIAS(T5, VPIDE, VPI); 702 SIG_EXPR_LIST_DECL_SINGLE(T5, NDCD1, NDCD1, T5_DESC); 703 PIN_DECL_2(T5, GPIOL1, VPIDE, NDCD1); 704 FUNC_GROUP_DECL(NDCD1, T5); 705 706 #define U3 90 707 #define U3_DESC SIG_DESC_SET(SCU84, 18) 708 SIG_EXPR_DECL_SINGLE(VPIODD, VPI18, VPI18_DESC, U3_DESC); 709 SIG_EXPR_DECL_SINGLE(VPIODD, VPI24, VPI24_DESC, U3_DESC); 710 SIG_EXPR_DECL_SINGLE(VPIODD, VPI30, VPI30_DESC, U3_DESC); 711 SIG_EXPR_LIST_DECL(VPIODD, VPI, 712 SIG_EXPR_PTR(VPIODD, VPI18), 713 SIG_EXPR_PTR(VPIODD, VPI24), 714 SIG_EXPR_PTR(VPIODD, VPI30)); 715 SIG_EXPR_LIST_ALIAS(U3, VPIODD, VPI); 716 SIG_EXPR_LIST_DECL_SINGLE(U3, NDSR1, NDSR1, U3_DESC); 717 PIN_DECL_2(U3, GPIOL2, VPIODD, NDSR1); 718 FUNC_GROUP_DECL(NDSR1, U3); 719 720 #define V1 91 721 #define V1_DESC SIG_DESC_SET(SCU84, 19) 722 SIG_EXPR_DECL_SINGLE(VPIHS, VPI18, VPI18_DESC, V1_DESC); 723 SIG_EXPR_DECL_SINGLE(VPIHS, VPI24, VPI24_DESC, V1_DESC); 724 SIG_EXPR_DECL_SINGLE(VPIHS, VPI30, VPI30_DESC, V1_DESC); 725 SIG_EXPR_LIST_DECL(VPIHS, VPI, 726 SIG_EXPR_PTR(VPIHS, VPI18), 727 SIG_EXPR_PTR(VPIHS, VPI24), 728 SIG_EXPR_PTR(VPIHS, VPI30)); 729 SIG_EXPR_LIST_ALIAS(V1, VPIHS, VPI); 730 SIG_EXPR_LIST_DECL_SINGLE(V1, NRI1, NRI1, V1_DESC); 731 PIN_DECL_2(V1, GPIOL3, VPIHS, NRI1); 732 FUNC_GROUP_DECL(NRI1, V1); 733 734 #define U4 92 735 #define U4_DESC SIG_DESC_SET(SCU84, 20) 736 SIG_EXPR_DECL_SINGLE(VPIVS, VPI18, VPI18_DESC, U4_DESC); 737 SIG_EXPR_DECL_SINGLE(VPIVS, VPI24, VPI24_DESC, U4_DESC); 738 SIG_EXPR_DECL_SINGLE(VPIVS, VPI30, VPI30_DESC, U4_DESC); 739 SIG_EXPR_LIST_DECL(VPIVS, VPI, 740 SIG_EXPR_PTR(VPIVS, VPI18), 741 SIG_EXPR_PTR(VPIVS, VPI24), 742 SIG_EXPR_PTR(VPIVS, VPI30)); 743 SIG_EXPR_LIST_ALIAS(U4, VPIVS, VPI); 744 SIG_EXPR_LIST_DECL_SINGLE(U4, NDTR1, NDTR1, U4_DESC); 745 PIN_DECL_2(U4, GPIOL4, VPIVS, NDTR1); 746 FUNC_GROUP_DECL(NDTR1, U4); 747 748 #define V2 93 749 #define V2_DESC SIG_DESC_SET(SCU84, 21) 750 SIG_EXPR_DECL_SINGLE(VPICLK, VPI18, VPI18_DESC, V2_DESC); 751 SIG_EXPR_DECL_SINGLE(VPICLK, VPI24, VPI24_DESC, V2_DESC); 752 SIG_EXPR_DECL_SINGLE(VPICLK, VPI30, VPI30_DESC, V2_DESC); 753 SIG_EXPR_LIST_DECL(VPICLK, VPI, 754 SIG_EXPR_PTR(VPICLK, VPI18), 755 SIG_EXPR_PTR(VPICLK, VPI24), 756 SIG_EXPR_PTR(VPICLK, VPI30)); 757 SIG_EXPR_LIST_ALIAS(V2, VPICLK, VPI); 758 SIG_EXPR_LIST_DECL_SINGLE(V2, NRTS1, NRTS1, V2_DESC); 759 PIN_DECL_2(V2, GPIOL5, VPICLK, NRTS1); 760 FUNC_GROUP_DECL(NRTS1, V2); 761 762 #define W1 94 763 #define W1_DESC SIG_DESC_SET(SCU84, 22) 764 SIG_EXPR_LIST_DECL_SINGLE(W1, VPIB0, VPI30, VPI30_DESC, W1_DESC); 765 SIG_EXPR_LIST_DECL_SINGLE(W1, TXD1, TXD1, W1_DESC); 766 PIN_DECL_2(W1, GPIOL6, VPIB0, TXD1); 767 FUNC_GROUP_DECL(TXD1, W1); 768 769 #define U5 95 770 #define U5_DESC SIG_DESC_SET(SCU84, 23) 771 SIG_EXPR_LIST_DECL_SINGLE(U5, VPIB1, VPI30, VPI30_DESC, U5_DESC); 772 SIG_EXPR_LIST_DECL_SINGLE(U5, RXD1, RXD1, U5_DESC); 773 PIN_DECL_2(U5, GPIOL7, VPIB1, RXD1); 774 FUNC_GROUP_DECL(RXD1, U5); 775 776 #define V3 96 777 #define V3_DESC SIG_DESC_SET(SCU84, 24) 778 SIG_EXPR_DECL_SINGLE(VPIOB2, VPI18, VPI18_DESC, V3_DESC); 779 SIG_EXPR_DECL_SINGLE(VPIOB2, VPI24, VPI24_DESC, V3_DESC); 780 SIG_EXPR_DECL_SINGLE(VPIOB2, VPI30, VPI30_DESC, V3_DESC); 781 SIG_EXPR_LIST_DECL(VPIOB2, VPI, 782 SIG_EXPR_PTR(VPIOB2, VPI18), 783 SIG_EXPR_PTR(VPIOB2, VPI24), 784 SIG_EXPR_PTR(VPIOB2, VPI30)); 785 SIG_EXPR_LIST_ALIAS(V3, VPIOB2, VPI); 786 SIG_EXPR_LIST_DECL_SINGLE(V3, NCTS2, NCTS2, V3_DESC); 787 PIN_DECL_2(V3, GPIOM0, VPIOB2, NCTS2); 788 FUNC_GROUP_DECL(NCTS2, V3); 789 790 #define W2 97 791 #define W2_DESC SIG_DESC_SET(SCU84, 25) 792 SIG_EXPR_DECL_SINGLE(VPIOB3, VPI18, VPI18_DESC, W2_DESC); 793 SIG_EXPR_DECL_SINGLE(VPIOB3, VPI24, VPI24_DESC, W2_DESC); 794 SIG_EXPR_DECL_SINGLE(VPIOB3, VPI30, VPI30_DESC, W2_DESC); 795 SIG_EXPR_LIST_DECL(VPIOB3, VPI, 796 SIG_EXPR_PTR(VPIOB3, VPI18), 797 SIG_EXPR_PTR(VPIOB3, VPI24), 798 SIG_EXPR_PTR(VPIOB3, VPI30)); 799 SIG_EXPR_LIST_ALIAS(W2, VPIOB3, VPI); 800 SIG_EXPR_LIST_DECL_SINGLE(W2, NDCD2, NDCD2, W2_DESC); 801 PIN_DECL_2(W2, GPIOM1, VPIOB3, NDCD2); 802 FUNC_GROUP_DECL(NDCD2, W2); 803 804 #define Y1 98 805 #define Y1_DESC SIG_DESC_SET(SCU84, 26) 806 SIG_EXPR_DECL_SINGLE(VPIOB4, VPI18, VPI18_DESC, Y1_DESC); 807 SIG_EXPR_DECL_SINGLE(VPIOB4, VPI24, VPI24_DESC, Y1_DESC); 808 SIG_EXPR_DECL_SINGLE(VPIOB4, VPI30, VPI30_DESC, Y1_DESC); 809 SIG_EXPR_LIST_DECL(VPIOB4, VPI, 810 SIG_EXPR_PTR(VPIOB4, VPI18), 811 SIG_EXPR_PTR(VPIOB4, VPI24), 812 SIG_EXPR_PTR(VPIOB4, VPI30)); 813 SIG_EXPR_LIST_ALIAS(Y1, VPIOB4, VPI); 814 SIG_EXPR_LIST_DECL_SINGLE(Y1, NDSR2, NDSR2, Y1_DESC); 815 PIN_DECL_2(Y1, GPIOM2, VPIOB4, NDSR2); 816 FUNC_GROUP_DECL(NDSR2, Y1); 817 818 #define V4 99 819 #define V4_DESC SIG_DESC_SET(SCU84, 27) 820 SIG_EXPR_DECL_SINGLE(VPIOB5, VPI18, VPI18_DESC, V4_DESC); 821 SIG_EXPR_DECL_SINGLE(VPIOB5, VPI24, VPI24_DESC, V4_DESC); 822 SIG_EXPR_DECL_SINGLE(VPIOB5, VPI30, VPI30_DESC, V4_DESC); 823 SIG_EXPR_LIST_DECL(VPIOB5, VPI, 824 SIG_EXPR_PTR(VPIOB5, VPI18), 825 SIG_EXPR_PTR(VPIOB5, VPI24), 826 SIG_EXPR_PTR(VPIOB5, VPI30)); 827 SIG_EXPR_LIST_ALIAS(V4, VPIOB5, VPI); 828 SIG_EXPR_LIST_DECL_SINGLE(V4, NRI2, NRI2, V4_DESC); 829 PIN_DECL_2(V4, GPIOM3, VPIOB5, NRI2); 830 FUNC_GROUP_DECL(NRI2, V4); 831 832 #define W3 100 833 #define W3_DESC SIG_DESC_SET(SCU84, 28) 834 SIG_EXPR_DECL_SINGLE(VPIOB6, VPI18, VPI18_DESC, W3_DESC); 835 SIG_EXPR_DECL_SINGLE(VPIOB6, VPI24, VPI24_DESC, W3_DESC); 836 SIG_EXPR_DECL_SINGLE(VPIOB6, VPI30, VPI30_DESC, W3_DESC); 837 SIG_EXPR_LIST_DECL(VPIOB6, VPI, 838 SIG_EXPR_PTR(VPIOB6, VPI18), 839 SIG_EXPR_PTR(VPIOB6, VPI24), 840 SIG_EXPR_PTR(VPIOB6, VPI30)); 841 SIG_EXPR_LIST_ALIAS(W3, VPIOB6, VPI); 842 SIG_EXPR_LIST_DECL_SINGLE(W3, NDTR2, NDTR2, W3_DESC); 843 PIN_DECL_2(W3, GPIOM4, VPIOB6, NDTR2); 844 FUNC_GROUP_DECL(NDTR2, W3); 845 846 #define Y2 101 847 #define Y2_DESC SIG_DESC_SET(SCU84, 29) 848 SIG_EXPR_DECL_SINGLE(VPIOB7, VPI18, VPI18_DESC, Y2_DESC); 849 SIG_EXPR_DECL_SINGLE(VPIOB7, VPI24, VPI24_DESC, Y2_DESC); 850 SIG_EXPR_DECL_SINGLE(VPIOB7, VPI30, VPI30_DESC, Y2_DESC); 851 SIG_EXPR_LIST_DECL(VPIOB7, VPI, 852 SIG_EXPR_PTR(VPIOB7, VPI18), 853 SIG_EXPR_PTR(VPIOB7, VPI24), 854 SIG_EXPR_PTR(VPIOB7, VPI30)); 855 SIG_EXPR_LIST_ALIAS(Y2, VPIOB7, VPI); 856 SIG_EXPR_LIST_DECL_SINGLE(Y2, NRTS2, NRTS2, Y2_DESC); 857 PIN_DECL_2(Y2, GPIOM5, VPIOB7, NRTS2); 858 FUNC_GROUP_DECL(NRTS2, Y2); 859 860 #define AA1 102 861 #define AA1_DESC SIG_DESC_SET(SCU84, 30) 862 SIG_EXPR_DECL_SINGLE(VPIOB8, VPI18, VPI18_DESC, AA1_DESC); 863 SIG_EXPR_DECL_SINGLE(VPIOB8, VPI24, VPI24_DESC, AA1_DESC); 864 SIG_EXPR_DECL_SINGLE(VPIOB8, VPI30, VPI30_DESC, AA1_DESC); 865 SIG_EXPR_LIST_DECL(VPIOB8, VPI, 866 SIG_EXPR_PTR(VPIOB8, VPI18), 867 SIG_EXPR_PTR(VPIOB8, VPI24), 868 SIG_EXPR_PTR(VPIOB8, VPI30)); 869 SIG_EXPR_LIST_ALIAS(AA1, VPIOB8, VPI); 870 SIG_EXPR_LIST_DECL_SINGLE(AA1, TXD2, TXD2, AA1_DESC); 871 PIN_DECL_2(AA1, GPIOM6, VPIOB8, TXD2); 872 FUNC_GROUP_DECL(TXD2, AA1); 873 874 #define V5 103 875 #define V5_DESC SIG_DESC_SET(SCU84, 31) 876 SIG_EXPR_DECL_SINGLE(VPIOB9, VPI18, VPI18_DESC, V5_DESC); 877 SIG_EXPR_DECL_SINGLE(VPIOB9, VPI24, VPI24_DESC, V5_DESC); 878 SIG_EXPR_DECL_SINGLE(VPIOB9, VPI30, VPI30_DESC, V5_DESC); 879 SIG_EXPR_LIST_DECL(VPIOB9, VPI, 880 SIG_EXPR_PTR(VPIOB9, VPI18), 881 SIG_EXPR_PTR(VPIOB9, VPI24), 882 SIG_EXPR_PTR(VPIOB9, VPI30)); 883 SIG_EXPR_LIST_ALIAS(V5, VPIOB9, VPI); 884 SIG_EXPR_LIST_DECL_SINGLE(V5, RXD2, RXD2, V5_DESC); 885 PIN_DECL_2(V5, GPIOM7, VPIOB9, RXD2); 886 FUNC_GROUP_DECL(RXD2, V5); 887 888 #define W4 104 889 #define W4_DESC SIG_DESC_SET(SCU88, 0) 890 SIG_EXPR_LIST_DECL_SINGLE(W4, VPIG0, VPI30, VPI30_DESC, W4_DESC); 891 SIG_EXPR_LIST_DECL_SINGLE(W4, PWM0, PWM0, W4_DESC); 892 PIN_DECL_2(W4, GPION0, VPIG0, PWM0); 893 FUNC_GROUP_DECL(PWM0, W4); 894 895 #define Y3 105 896 #define Y3_DESC SIG_DESC_SET(SCU88, 1) 897 SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG1, VPI30, VPI30_DESC, Y3_DESC); 898 SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM1, PWM1, Y3_DESC); 899 PIN_DECL_2(Y3, GPION1, VPIG1, PWM1); 900 FUNC_GROUP_DECL(PWM1, Y3); 901 902 #define AA2 106 903 #define AA2_DESC SIG_DESC_SET(SCU88, 2) 904 SIG_EXPR_DECL_SINGLE(VPIG2, VPI18, VPI18_DESC, AA2_DESC); 905 SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, AA2_DESC); 906 SIG_EXPR_DECL_SINGLE(VPIG2, VPI30, VPI30_DESC, AA2_DESC); 907 SIG_EXPR_LIST_DECL(VPIG2, VPI, 908 SIG_EXPR_PTR(VPIG2, VPI18), 909 SIG_EXPR_PTR(VPIG2, VPI24), 910 SIG_EXPR_PTR(VPIG2, VPI30)); 911 SIG_EXPR_LIST_ALIAS(AA2, VPIG2, VPI); 912 SIG_EXPR_LIST_DECL_SINGLE(AA2, PWM2, PWM2, AA2_DESC); 913 PIN_DECL_2(AA2, GPION2, VPIG2, PWM2); 914 FUNC_GROUP_DECL(PWM2, AA2); 915 916 #define AB1 107 917 #define AB1_DESC SIG_DESC_SET(SCU88, 3) 918 SIG_EXPR_DECL_SINGLE(VPIG3, VPI18, VPI18_DESC, AB1_DESC); 919 SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, AB1_DESC); 920 SIG_EXPR_DECL_SINGLE(VPIG3, VPI30, VPI30_DESC, AB1_DESC); 921 SIG_EXPR_LIST_DECL(VPIG3, VPI, 922 SIG_EXPR_PTR(VPIG3, VPI18), 923 SIG_EXPR_PTR(VPIG3, VPI24), 924 SIG_EXPR_PTR(VPIG3, VPI30)); 925 SIG_EXPR_LIST_ALIAS(AB1, VPIG3, VPI); 926 SIG_EXPR_LIST_DECL_SINGLE(AB1, PWM3, PWM3, AB1_DESC); 927 PIN_DECL_2(AB1, GPION3, VPIG3, PWM3); 928 FUNC_GROUP_DECL(PWM3, AB1); 929 930 #define W5 108 931 #define W5_DESC SIG_DESC_SET(SCU88, 4) 932 SIG_EXPR_DECL_SINGLE(VPIG4, VPI18, VPI18_DESC, W5_DESC); 933 SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W5_DESC); 934 SIG_EXPR_DECL_SINGLE(VPIG4, VPI30, VPI30_DESC, W5_DESC); 935 SIG_EXPR_LIST_DECL(VPIG4, VPI, 936 SIG_EXPR_PTR(VPIG4, VPI18), 937 SIG_EXPR_PTR(VPIG4, VPI24), 938 SIG_EXPR_PTR(VPIG4, VPI30)); 939 SIG_EXPR_LIST_ALIAS(W5, VPIG4, VPI); 940 SIG_EXPR_LIST_DECL_SINGLE(W5, PWM4, PWM4, W5_DESC); 941 PIN_DECL_2(W5, GPION4, VPIG4, PWM4); 942 FUNC_GROUP_DECL(PWM4, W5); 943 944 #define Y4 109 945 #define Y4_DESC SIG_DESC_SET(SCU88, 5) 946 SIG_EXPR_DECL_SINGLE(VPIG5, VPI18, VPI18_DESC, Y4_DESC); 947 SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, Y4_DESC); 948 SIG_EXPR_DECL_SINGLE(VPIG5, VPI30, VPI30_DESC, Y4_DESC); 949 SIG_EXPR_LIST_DECL(VPIG5, VPI, 950 SIG_EXPR_PTR(VPIG5, VPI18), 951 SIG_EXPR_PTR(VPIG5, VPI24), 952 SIG_EXPR_PTR(VPIG5, VPI30)); 953 SIG_EXPR_LIST_ALIAS(Y4, VPIG5, VPI); 954 SIG_EXPR_LIST_DECL_SINGLE(Y4, PWM5, PWM5, Y4_DESC); 955 PIN_DECL_2(Y4, GPION5, VPIG5, PWM5); 956 FUNC_GROUP_DECL(PWM5, Y4); 957 958 #define AA3 110 959 #define AA3_DESC SIG_DESC_SET(SCU88, 6) 960 SIG_EXPR_LIST_DECL_SINGLE(AA3, VPIG6, VPI30, VPI30_DESC, AA3_DESC); 961 SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM6, PWM6, AA3_DESC); 962 PIN_DECL_2(AA3, GPION6, VPIG6, PWM6); 963 FUNC_GROUP_DECL(PWM6, AA3); 964 965 #define AB2 111 966 #define AB2_DESC SIG_DESC_SET(SCU88, 7) 967 SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIG7, VPI30, VPI30_DESC, AB2_DESC); 968 SIG_EXPR_LIST_DECL_SINGLE(AB2, PWM7, PWM7, AB2_DESC); 969 PIN_DECL_2(AB2, GPION7, VPIG7, PWM7); 970 FUNC_GROUP_DECL(PWM7, AB2); 971 972 #define V6 112 973 SIG_EXPR_LIST_DECL_SINGLE(V6, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8)); 974 PIN_DECL_1(V6, GPIOO0, VPIG8); 975 976 #define Y5 113 977 SIG_EXPR_LIST_DECL_SINGLE(Y5, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9)); 978 PIN_DECL_1(Y5, GPIOO1, VPIG9); 979 980 #define AA4 114 981 SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR0, VPI30, VPI30_DESC, 982 SIG_DESC_SET(SCU88, 10)); 983 PIN_DECL_1(AA4, GPIOO2, VPIR0); 984 985 #define AB3 115 986 SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR1, VPI30, VPI30_DESC, 987 SIG_DESC_SET(SCU88, 11)); 988 PIN_DECL_1(AB3, GPIOO3, VPIR1); 989 990 #define W6 116 991 SIG_EXPR_LIST_DECL_SINGLE(W6, VPIR2, VPI24, VPI24_DESC, 992 SIG_DESC_SET(SCU88, 12)); 993 PIN_DECL_1(W6, GPIOO4, VPIR2); 994 995 #define AA5 117 996 SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR3, VPI24, VPI24_DESC, 997 SIG_DESC_SET(SCU88, 13)); 998 PIN_DECL_1(AA5, GPIOO5, VPIR3); 999 1000 #define AB4 118 1001 SIG_EXPR_LIST_DECL_SINGLE(AB4, VPIR4, VPI24, VPI24_DESC, 1002 SIG_DESC_SET(SCU88, 14)); 1003 PIN_DECL_1(AB4, GPIOO6, VPIR4); 1004 1005 #define V7 119 1006 SIG_EXPR_LIST_DECL_SINGLE(V7, VPIR5, VPI24, VPI24_DESC, 1007 SIG_DESC_SET(SCU88, 15)); 1008 PIN_DECL_1(V7, GPIOO7, VPIR5); 1009 1010 #define Y6 120 1011 SIG_EXPR_LIST_DECL_SINGLE(Y6, VPIR6, VPI24, VPI24_DESC, 1012 SIG_DESC_SET(SCU88, 16)); 1013 PIN_DECL_1(Y6, GPIOP0, VPIR6); 1014 1015 #define AB5 121 1016 SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR7, VPI24, VPI24_DESC, 1017 SIG_DESC_SET(SCU88, 17)); 1018 PIN_DECL_1(AB5, GPIOP1, VPIR7); 1019 1020 #define W7 122 1021 SIG_EXPR_LIST_DECL_SINGLE(W7, VPIR8, VPI24, VPI24_DESC, 1022 SIG_DESC_SET(SCU88, 18)); 1023 PIN_DECL_1(W7, GPIOP2, VPIR8); 1024 1025 #define AA6 123 1026 SIG_EXPR_LIST_DECL_SINGLE(AA6, VPIR9, VPI24, VPI24_DESC, 1027 SIG_DESC_SET(SCU88, 19)); 1028 PIN_DECL_1(AA6, GPIOP3, VPIR9); 1029 1030 FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, 1031 AA22, W5, Y4, AA3, AB2); 1032 FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, 1033 AA22, W5, Y4, AA3, AB2, V6, Y5, W6, AA5, AB4, V7, Y6, AB5, W7, 1034 AA6); 1035 FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1, 1036 V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3); 1037 1038 #define AB6 124 1039 SIG_EXPR_LIST_DECL_SINGLE(AB6, GPIOP4, GPIOP4); 1040 PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(AB6, GPIOP4)); 1041 1042 #define Y7 125 1043 SIG_EXPR_LIST_DECL_SINGLE(Y7, GPIOP5, GPIOP5); 1044 PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(Y7, GPIOP5)); 1045 1046 #define AA7 126 1047 SSSF_PIN_DECL(AA7, GPIOP6, BMCINT, SIG_DESC_SET(SCU88, 22)); 1048 1049 #define AB7 127 1050 SSSF_PIN_DECL(AB7, GPIOP7, FLACK, SIG_DESC_SET(SCU88, 23)); 1051 1052 #define I2C3_DESC SIG_DESC_SET(SCU90, 16) 1053 1054 #define D3 128 1055 SIG_EXPR_LIST_DECL_SINGLE(D3, SCL3, I2C3, I2C3_DESC); 1056 PIN_DECL_1(D3, GPIOQ0, SCL3); 1057 1058 #define C2 129 1059 SIG_EXPR_LIST_DECL_SINGLE(C2, SDA3, I2C3, I2C3_DESC); 1060 PIN_DECL_1(C2, GPIOQ1, SDA3); 1061 1062 FUNC_GROUP_DECL(I2C3, D3, C2); 1063 1064 #define I2C4_DESC SIG_DESC_SET(SCU90, 17) 1065 1066 #define B1 130 1067 SIG_EXPR_LIST_DECL_SINGLE(B1, SCL4, I2C4, I2C4_DESC); 1068 PIN_DECL_1(B1, GPIOQ2, SCL4); 1069 1070 #define F5 131 1071 SIG_EXPR_LIST_DECL_SINGLE(F5, SDA4, I2C4, I2C4_DESC); 1072 PIN_DECL_1(F5, GPIOQ3, SDA4); 1073 1074 FUNC_GROUP_DECL(I2C4, B1, F5); 1075 1076 #define I2C14_DESC SIG_DESC_SET(SCU90, 27) 1077 1078 #define H4 132 1079 SIG_EXPR_LIST_DECL_SINGLE(H4, SCL14, I2C14, I2C14_DESC); 1080 PIN_DECL_1(H4, GPIOQ4, SCL14); 1081 1082 #define H3 133 1083 SIG_EXPR_LIST_DECL_SINGLE(H3, SDA14, I2C14, I2C14_DESC); 1084 PIN_DECL_1(H3, GPIOQ5, SDA14); 1085 1086 FUNC_GROUP_DECL(I2C14, H4, H3); 1087 1088 /* 1089 * There are several opportunities to document USB port 4 in the datasheet, but 1090 * it is only mentioned in one location. Particularly, the Multi-function Pins 1091 * Mapping and Control table in the datasheet elides the signal names, 1092 * suggesting that port 4 may not actually be functional. As such we define the 1093 * signal names and control bit, but don't export the capability's function or 1094 * group. 1095 */ 1096 #define USB11H3_DESC SIG_DESC_SET(SCU90, 28) 1097 1098 #define H2 134 1099 SIG_EXPR_LIST_DECL_SINGLE(H2, USB11HDP3, USB11H3, USB11H3_DESC); 1100 PIN_DECL_1(H2, GPIOQ6, USB11HDP3); 1101 1102 #define H1 135 1103 SIG_EXPR_LIST_DECL_SINGLE(H1, USB11HDN3, USB11H3, USB11H3_DESC); 1104 PIN_DECL_1(H1, GPIOQ7, USB11HDN3); 1105 1106 #define V20 136 1107 SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24)); 1108 1109 #define W21 137 1110 SSSF_PIN_DECL(W21, GPIOR1, ROMCS2, SIG_DESC_SET(SCU88, 25)); 1111 1112 #define Y22 138 1113 SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26)); 1114 1115 #define U19 139 1116 SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27)); 1117 1118 #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } 1119 #define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 } 1120 #define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 } 1121 #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 } 1122 #define VPO_OFF_12 { ASPEED_IP_SCU, SCU94, 0x2, 0, 0 } 1123 #define VPO_24_OFF SIG_DESC_SET(SCU94, 1) 1124 1125 #define V21 140 1126 #define V21_DESC SIG_DESC_SET(SCU88, 28) 1127 SIG_EXPR_DECL_SINGLE(ROMA24, ROM8, V21_DESC, VPO_OFF_12); 1128 SIG_EXPR_DECL_SINGLE(ROMA24, ROM16, V21_DESC, VPO_OFF_12); 1129 SIG_EXPR_DECL_SINGLE(ROMA24, ROM16S, V21_DESC, VPO_OFF_12); 1130 SIG_EXPR_LIST_DECL(ROMA24, ROM, 1131 SIG_EXPR_PTR(ROMA24, ROM8), 1132 SIG_EXPR_PTR(ROMA24, ROM16), 1133 SIG_EXPR_PTR(ROMA24, ROM16S)); 1134 SIG_EXPR_LIST_ALIAS(V21, ROMA24, ROM); 1135 SIG_EXPR_LIST_DECL_SINGLE(V21, VPOR6, VPO24, V21_DESC, VPO_24_OFF); 1136 PIN_DECL_2(V21, GPIOR4, ROMA24, VPOR6); 1137 1138 #define W22 141 1139 #define W22_DESC SIG_DESC_SET(SCU88, 29) 1140 SIG_EXPR_DECL_SINGLE(ROMA25, ROM8, W22_DESC, VPO_OFF_12); 1141 SIG_EXPR_DECL_SINGLE(ROMA25, ROM16, W22_DESC, VPO_OFF_12); 1142 SIG_EXPR_DECL_SINGLE(ROMA25, ROM16S, W22_DESC, VPO_OFF_12); 1143 SIG_EXPR_LIST_DECL(ROMA25, ROM, 1144 SIG_EXPR_PTR(ROMA25, ROM8), 1145 SIG_EXPR_PTR(ROMA25, ROM16), 1146 SIG_EXPR_PTR(ROMA25, ROM16S)); 1147 SIG_EXPR_LIST_ALIAS(W22, ROMA25, ROM); 1148 SIG_EXPR_LIST_DECL_SINGLE(W22, VPOR7, VPO24, W22_DESC, VPO_24_OFF); 1149 PIN_DECL_2(W22, GPIOR5, ROMA25, VPOR7); 1150 1151 #define C6 142 1152 SIG_EXPR_LIST_DECL_SINGLE(C6, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); 1153 PIN_DECL_1(C6, GPIOR6, MDC1); 1154 1155 #define A5 143 1156 SIG_EXPR_LIST_DECL_SINGLE(A5, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); 1157 PIN_DECL_1(A5, GPIOR7, MDIO1); 1158 1159 FUNC_GROUP_DECL(MDIO1, C6, A5); 1160 1161 #define U21 144 1162 #define U21_DESC SIG_DESC_SET(SCU8C, 0) 1163 SIG_EXPR_DECL_SINGLE(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC); 1164 SIG_EXPR_DECL_SINGLE(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC); 1165 SIG_EXPR_DECL_SINGLE(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC); 1166 SIG_EXPR_LIST_DECL(ROMD4, ROM, 1167 SIG_EXPR_PTR(ROMD4, ROM8), 1168 SIG_EXPR_PTR(ROMD4, ROM16), 1169 SIG_EXPR_PTR(ROMD4, ROM16S)); 1170 SIG_EXPR_LIST_ALIAS(U21, ROMD4, ROM); 1171 SIG_EXPR_DECL_SINGLE(VPODE, VPO12, U21_DESC, VPO12_DESC); 1172 SIG_EXPR_DECL_SINGLE(VPODE, VPO24, U21_DESC, VPO12_DESC); 1173 SIG_EXPR_LIST_DECL_DUAL(U21, VPODE, VPO12, VPO24); 1174 PIN_DECL_2(U21, GPIOS0, ROMD4, VPODE); 1175 1176 #define T19 145 1177 #define T19_DESC SIG_DESC_SET(SCU8C, 1) 1178 SIG_EXPR_DECL_SINGLE(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC); 1179 SIG_EXPR_DECL_SINGLE(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC); 1180 SIG_EXPR_DECL_SINGLE(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC); 1181 SIG_EXPR_LIST_DECL(ROMD5, ROM, 1182 SIG_EXPR_PTR(ROMD5, ROM8), 1183 SIG_EXPR_PTR(ROMD5, ROM16), 1184 SIG_EXPR_PTR(ROMD5, ROM16S)); 1185 SIG_EXPR_LIST_ALIAS(T19, ROMD5, ROM); 1186 SIG_EXPR_DECL_SINGLE(VPOHS, VPO12, T19_DESC, VPO12_DESC); 1187 SIG_EXPR_DECL_SINGLE(VPOHS, VPO24, T19_DESC, VPO24_DESC); 1188 SIG_EXPR_LIST_DECL_DUAL(T19, VPOHS, VPO12, VPO24); 1189 PIN_DECL_2(T19, GPIOS1, ROMD5, VPOHS); 1190 1191 #define V22 146 1192 #define V22_DESC SIG_DESC_SET(SCU8C, 2) 1193 SIG_EXPR_DECL_SINGLE(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC); 1194 SIG_EXPR_DECL_SINGLE(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC); 1195 SIG_EXPR_DECL_SINGLE(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC); 1196 SIG_EXPR_LIST_DECL(ROMD6, ROM, 1197 SIG_EXPR_PTR(ROMD6, ROM8), 1198 SIG_EXPR_PTR(ROMD6, ROM16), 1199 SIG_EXPR_PTR(ROMD6, ROM16S)); 1200 SIG_EXPR_LIST_ALIAS(V22, ROMD6, ROM); 1201 SIG_EXPR_DECL_SINGLE(VPOVS, VPO12, V22_DESC, VPO12_DESC); 1202 SIG_EXPR_DECL_SINGLE(VPOVS, VPO24, V22_DESC, VPO24_DESC); 1203 SIG_EXPR_LIST_DECL_DUAL(V22, VPOVS, VPO12, VPO24); 1204 PIN_DECL_2(V22, GPIOS2, ROMD6, VPOVS); 1205 1206 #define U20 147 1207 #define U20_DESC SIG_DESC_SET(SCU8C, 3) 1208 SIG_EXPR_DECL_SINGLE(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC); 1209 SIG_EXPR_DECL_SINGLE(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC); 1210 SIG_EXPR_DECL_SINGLE(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC); 1211 SIG_EXPR_LIST_DECL(ROMD7, ROM, 1212 SIG_EXPR_PTR(ROMD7, ROM8), 1213 SIG_EXPR_PTR(ROMD7, ROM16), 1214 SIG_EXPR_PTR(ROMD7, ROM16S)); 1215 SIG_EXPR_LIST_ALIAS(U20, ROMD7, ROM); 1216 SIG_EXPR_DECL_SINGLE(VPOCLK, VPO12, U20_DESC, VPO12_DESC); 1217 SIG_EXPR_DECL_SINGLE(VPOCLK, VPO24, U20_DESC, VPO24_DESC); 1218 SIG_EXPR_LIST_DECL_DUAL(U20, VPOCLK, VPO12, VPO24); 1219 PIN_DECL_2(U20, GPIOS3, ROMD7, VPOCLK); 1220 1221 #define R18 148 1222 #define ROMOE_DESC SIG_DESC_SET(SCU8C, 4) 1223 SIG_EXPR_LIST_DECL_SINGLE(R18, GPIOS4, GPIOS4); 1224 SIG_EXPR_DECL_SINGLE(ROMOE, ROM8, ROMOE_DESC); 1225 SIG_EXPR_DECL_SINGLE(ROMOE, ROM16, ROMOE_DESC); 1226 SIG_EXPR_DECL_SINGLE(ROMOE, ROM16S, ROMOE_DESC); 1227 SIG_EXPR_LIST_DECL(ROMOE, ROM, 1228 SIG_EXPR_PTR(ROMOE, ROM8), 1229 SIG_EXPR_PTR(ROMOE, ROM16), 1230 SIG_EXPR_PTR(ROMOE, ROM16S)); 1231 SIG_EXPR_LIST_ALIAS(R18, ROMOE, ROM); 1232 PIN_DECL_(R18, SIG_EXPR_LIST_PTR(R18, ROMOE), SIG_EXPR_LIST_PTR(R18, GPIOS4)); 1233 1234 #define N21 149 1235 #define ROMWE_DESC SIG_DESC_SET(SCU8C, 5) 1236 SIG_EXPR_LIST_DECL_SINGLE(N21, GPIOS5, GPIOS5); 1237 SIG_EXPR_DECL_SINGLE(ROMWE, ROM8, ROMWE_DESC); 1238 SIG_EXPR_DECL_SINGLE(ROMWE, ROM16, ROMWE_DESC); 1239 SIG_EXPR_DECL_SINGLE(ROMWE, ROM16S, ROMWE_DESC); 1240 SIG_EXPR_LIST_DECL(ROMWE, ROM, 1241 SIG_EXPR_PTR(ROMWE, ROM8), 1242 SIG_EXPR_PTR(ROMWE, ROM16), 1243 SIG_EXPR_PTR(ROMWE, ROM16S)); 1244 SIG_EXPR_LIST_ALIAS(N21, ROMWE, ROM); 1245 PIN_DECL_(N21, SIG_EXPR_LIST_PTR(N21, ROMWE), SIG_EXPR_LIST_PTR(N21, GPIOS5)); 1246 1247 #define L22 150 1248 #define L22_DESC SIG_DESC_SET(SCU8C, 6) 1249 SIG_EXPR_DECL_SINGLE(ROMA22, ROM8, L22_DESC, VPO_OFF_12); 1250 SIG_EXPR_DECL_SINGLE(ROMA22, ROM16, L22_DESC, VPO_OFF_12); 1251 SIG_EXPR_DECL_SINGLE(ROMA22, ROM16S, L22_DESC, VPO_OFF_12); 1252 SIG_EXPR_LIST_DECL(ROMA22, ROM, 1253 SIG_EXPR_PTR(ROMA22, ROM8), 1254 SIG_EXPR_PTR(ROMA22, ROM16), 1255 SIG_EXPR_PTR(ROMA22, ROM16S)); 1256 SIG_EXPR_LIST_ALIAS(L22, ROMA22, ROM); 1257 SIG_EXPR_LIST_DECL_SINGLE(L22, VPOR4, VPO24, L22_DESC, VPO_24_OFF); 1258 PIN_DECL_2(L22, GPIOS6, ROMA22, VPOR4); 1259 1260 #define K18 151 1261 #define K18_DESC SIG_DESC_SET(SCU8C, 7) 1262 SIG_EXPR_DECL_SINGLE(ROMA23, ROM8, K18_DESC, VPO_OFF_12); 1263 SIG_EXPR_DECL_SINGLE(ROMA23, ROM16, K18_DESC, VPO_OFF_12); 1264 SIG_EXPR_DECL_SINGLE(ROMA23, ROM16S, K18_DESC, VPO_OFF_12); 1265 SIG_EXPR_LIST_DECL(ROMA23, ROM, 1266 SIG_EXPR_PTR(ROMA23, ROM8), 1267 SIG_EXPR_PTR(ROMA23, ROM16), 1268 SIG_EXPR_PTR(ROMA23, ROM16S)); 1269 SIG_EXPR_LIST_ALIAS(K18, ROMA23, ROM); 1270 SIG_EXPR_LIST_DECL_SINGLE(K18, VPOR5, VPO24, K18_DESC, VPO_24_OFF); 1271 PIN_DECL_2(K18, GPIOS7, ROMA23, VPOR5); 1272 1273 #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) 1274 1275 #define A12 152 1276 SIG_EXPR_LIST_DECL_SINGLE(A12, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); 1277 SIG_EXPR_LIST_DECL_SINGLE(A12, RMII1TXEN, RMII1, RMII1_DESC); 1278 SIG_EXPR_LIST_DECL_SINGLE(A12, RGMII1TXCK, RGMII1); 1279 PIN_DECL_(A12, SIG_EXPR_LIST_PTR(A12, GPIOT0), 1280 SIG_EXPR_LIST_PTR(A12, RMII1TXEN), 1281 SIG_EXPR_LIST_PTR(A12, RGMII1TXCK)); 1282 1283 #define B12 153 1284 SIG_EXPR_LIST_DECL_SINGLE(B12, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); 1285 SIG_EXPR_LIST_DECL_SINGLE(B12, DASHB12, RMII1, RMII1_DESC); 1286 SIG_EXPR_LIST_DECL_SINGLE(B12, RGMII1TXCTL, RGMII1); 1287 PIN_DECL_(B12, SIG_EXPR_LIST_PTR(B12, GPIOT1), SIG_EXPR_LIST_PTR(B12, DASHB12), 1288 SIG_EXPR_LIST_PTR(B12, RGMII1TXCTL)); 1289 1290 #define C12 154 1291 SIG_EXPR_LIST_DECL_SINGLE(C12, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); 1292 SIG_EXPR_LIST_DECL_SINGLE(C12, RMII1TXD0, RMII1, RMII1_DESC); 1293 SIG_EXPR_LIST_DECL_SINGLE(C12, RGMII1TXD0, RGMII1); 1294 PIN_DECL_(C12, SIG_EXPR_LIST_PTR(C12, GPIOT2), 1295 SIG_EXPR_LIST_PTR(C12, RMII1TXD0), 1296 SIG_EXPR_LIST_PTR(C12, RGMII1TXD0)); 1297 1298 #define D12 155 1299 SIG_EXPR_LIST_DECL_SINGLE(D12, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); 1300 SIG_EXPR_LIST_DECL_SINGLE(D12, RMII1TXD1, RMII1, RMII1_DESC); 1301 SIG_EXPR_LIST_DECL_SINGLE(D12, RGMII1TXD1, RGMII1); 1302 PIN_DECL_(D12, SIG_EXPR_LIST_PTR(D12, GPIOT3), 1303 SIG_EXPR_LIST_PTR(D12, RMII1TXD1), 1304 SIG_EXPR_LIST_PTR(D12, RGMII1TXD1)); 1305 1306 #define E12 156 1307 SIG_EXPR_LIST_DECL_SINGLE(E12, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); 1308 SIG_EXPR_LIST_DECL_SINGLE(E12, DASHE12, RMII1, RMII1_DESC); 1309 SIG_EXPR_LIST_DECL_SINGLE(E12, RGMII1TXD2, RGMII1); 1310 PIN_DECL_(E12, SIG_EXPR_LIST_PTR(E12, GPIOT4), SIG_EXPR_LIST_PTR(E12, DASHE12), 1311 SIG_EXPR_LIST_PTR(E12, RGMII1TXD2)); 1312 1313 #define A13 157 1314 SIG_EXPR_LIST_DECL_SINGLE(A13, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); 1315 SIG_EXPR_LIST_DECL_SINGLE(A13, DASHA13, RMII1, RMII1_DESC); 1316 SIG_EXPR_LIST_DECL_SINGLE(A13, RGMII1TXD3, RGMII1); 1317 PIN_DECL_(A13, SIG_EXPR_LIST_PTR(A13, GPIOT5), SIG_EXPR_LIST_PTR(A13, DASHA13), 1318 SIG_EXPR_LIST_PTR(A13, RGMII1TXD3)); 1319 1320 #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) 1321 1322 #define D9 158 1323 SIG_EXPR_LIST_DECL_SINGLE(D9, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); 1324 SIG_EXPR_LIST_DECL_SINGLE(D9, RMII2TXEN, RMII2, RMII2_DESC); 1325 SIG_EXPR_LIST_DECL_SINGLE(D9, RGMII2TXCK, RGMII2); 1326 PIN_DECL_(D9, SIG_EXPR_LIST_PTR(D9, GPIOT6), SIG_EXPR_LIST_PTR(D9, RMII2TXEN), 1327 SIG_EXPR_LIST_PTR(D9, RGMII2TXCK)); 1328 1329 #define E9 159 1330 SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); 1331 SIG_EXPR_LIST_DECL_SINGLE(E9, DASHE9, RMII2, RMII2_DESC); 1332 SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII2TXCTL, RGMII2); 1333 PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT7), SIG_EXPR_LIST_PTR(E9, DASHE9), 1334 SIG_EXPR_LIST_PTR(E9, RGMII2TXCTL)); 1335 1336 #define A10 160 1337 SIG_EXPR_LIST_DECL_SINGLE(A10, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); 1338 SIG_EXPR_LIST_DECL_SINGLE(A10, RMII2TXD0, RMII2, RMII2_DESC); 1339 SIG_EXPR_LIST_DECL_SINGLE(A10, RGMII2TXD0, RGMII2); 1340 PIN_DECL_(A10, SIG_EXPR_LIST_PTR(A10, GPIOU0), 1341 SIG_EXPR_LIST_PTR(A10, RMII2TXD0), 1342 SIG_EXPR_LIST_PTR(A10, RGMII2TXD0)); 1343 1344 #define B10 161 1345 SIG_EXPR_LIST_DECL_SINGLE(B10, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); 1346 SIG_EXPR_LIST_DECL_SINGLE(B10, RMII2TXD1, RMII2, RMII2_DESC); 1347 SIG_EXPR_LIST_DECL_SINGLE(B10, RGMII2TXD1, RGMII2); 1348 PIN_DECL_(B10, SIG_EXPR_LIST_PTR(B10, GPIOU1), 1349 SIG_EXPR_LIST_PTR(B10, RMII2TXD1), 1350 SIG_EXPR_LIST_PTR(B10, RGMII2TXD1)); 1351 1352 #define C10 162 1353 SIG_EXPR_LIST_DECL_SINGLE(C10, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); 1354 SIG_EXPR_LIST_DECL_SINGLE(C10, DASHC10, RMII2, RMII2_DESC); 1355 SIG_EXPR_LIST_DECL_SINGLE(C10, RGMII2TXD2, RGMII2); 1356 PIN_DECL_(C10, SIG_EXPR_LIST_PTR(C10, GPIOU2), SIG_EXPR_LIST_PTR(C10, DASHC10), 1357 SIG_EXPR_LIST_PTR(C10, RGMII2TXD2)); 1358 1359 #define D10 163 1360 SIG_EXPR_LIST_DECL_SINGLE(D10, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); 1361 SIG_EXPR_LIST_DECL_SINGLE(D10, DASHD10, RMII2, RMII2_DESC); 1362 SIG_EXPR_LIST_DECL_SINGLE(D10, RGMII2TXD3, RGMII2); 1363 PIN_DECL_(D10, SIG_EXPR_LIST_PTR(D10, GPIOU3), SIG_EXPR_LIST_PTR(D10, DASHD10), 1364 SIG_EXPR_LIST_PTR(D10, RGMII2TXD3)); 1365 1366 #define E11 164 1367 SIG_EXPR_LIST_DECL_SINGLE(E11, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); 1368 SIG_EXPR_LIST_DECL_SINGLE(E11, RMII1RCLK, RMII1, RMII1_DESC); 1369 SIG_EXPR_LIST_DECL_SINGLE(E11, RGMII1RXCK, RGMII1); 1370 PIN_DECL_(E11, SIG_EXPR_LIST_PTR(E11, GPIOU4), 1371 SIG_EXPR_LIST_PTR(E11, RMII1RCLK), 1372 SIG_EXPR_LIST_PTR(E11, RGMII1RXCK)); 1373 1374 #define D11 165 1375 SIG_EXPR_LIST_DECL_SINGLE(D11, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); 1376 SIG_EXPR_LIST_DECL_SINGLE(D11, DASHD11, RMII1, RMII1_DESC); 1377 SIG_EXPR_LIST_DECL_SINGLE(D11, RGMII1RXCTL, RGMII1); 1378 PIN_DECL_(D11, SIG_EXPR_LIST_PTR(D11, GPIOU5), SIG_EXPR_LIST_PTR(D11, DASHD11), 1379 SIG_EXPR_LIST_PTR(D11, RGMII1RXCTL)); 1380 1381 #define C11 166 1382 SIG_EXPR_LIST_DECL_SINGLE(C11, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); 1383 SIG_EXPR_LIST_DECL_SINGLE(C11, RMII1RXD0, RMII1, RMII1_DESC); 1384 SIG_EXPR_LIST_DECL_SINGLE(C11, RGMII1RXD0, RGMII1); 1385 PIN_DECL_(C11, SIG_EXPR_LIST_PTR(C11, GPIOU6), 1386 SIG_EXPR_LIST_PTR(C11, RMII1RXD0), 1387 SIG_EXPR_LIST_PTR(C11, RGMII1RXD0)); 1388 1389 #define B11 167 1390 SIG_EXPR_LIST_DECL_SINGLE(B11, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); 1391 SIG_EXPR_LIST_DECL_SINGLE(B11, RMII1RXD1, RMII1, RMII1_DESC); 1392 SIG_EXPR_LIST_DECL_SINGLE(B11, RGMII1RXD1, RGMII1); 1393 PIN_DECL_(B11, SIG_EXPR_LIST_PTR(B11, GPIOU7), 1394 SIG_EXPR_LIST_PTR(B11, RMII1RXD1), 1395 SIG_EXPR_LIST_PTR(B11, RGMII1RXD1)); 1396 1397 #define A11 168 1398 SIG_EXPR_LIST_DECL_SINGLE(A11, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); 1399 SIG_EXPR_LIST_DECL_SINGLE(A11, RMII1CRSDV, RMII1, RMII1_DESC); 1400 SIG_EXPR_LIST_DECL_SINGLE(A11, RGMII1RXD2, RGMII1); 1401 PIN_DECL_(A11, SIG_EXPR_LIST_PTR(A11, GPIOV0), 1402 SIG_EXPR_LIST_PTR(A11, RMII1CRSDV), 1403 SIG_EXPR_LIST_PTR(A11, RGMII1RXD2)); 1404 1405 #define E10 169 1406 SIG_EXPR_LIST_DECL_SINGLE(E10, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); 1407 SIG_EXPR_LIST_DECL_SINGLE(E10, RMII1RXER, RMII1, RMII1_DESC); 1408 SIG_EXPR_LIST_DECL_SINGLE(E10, RGMII1RXD3, RGMII1); 1409 PIN_DECL_(E10, SIG_EXPR_LIST_PTR(E10, GPIOV1), 1410 SIG_EXPR_LIST_PTR(E10, RMII1RXER), 1411 SIG_EXPR_LIST_PTR(E10, RGMII1RXD3)); 1412 1413 #define C9 170 1414 SIG_EXPR_LIST_DECL_SINGLE(C9, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); 1415 SIG_EXPR_LIST_DECL_SINGLE(C9, RMII2RCLK, RMII2, RMII2_DESC); 1416 SIG_EXPR_LIST_DECL_SINGLE(C9, RGMII2RXCK, RGMII2); 1417 PIN_DECL_(C9, SIG_EXPR_LIST_PTR(C9, GPIOV2), SIG_EXPR_LIST_PTR(C9, RMII2RCLK), 1418 SIG_EXPR_LIST_PTR(C9, RGMII2RXCK)); 1419 1420 #define B9 171 1421 SIG_EXPR_LIST_DECL_SINGLE(B9, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); 1422 SIG_EXPR_LIST_DECL_SINGLE(B9, DASHB9, RMII2, RMII2_DESC); 1423 SIG_EXPR_LIST_DECL_SINGLE(B9, RGMII2RXCTL, RGMII2); 1424 PIN_DECL_(B9, SIG_EXPR_LIST_PTR(B9, GPIOV3), SIG_EXPR_LIST_PTR(B9, DASHB9), 1425 SIG_EXPR_LIST_PTR(B9, RGMII2RXCTL)); 1426 1427 #define A9 172 1428 SIG_EXPR_LIST_DECL_SINGLE(A9, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); 1429 SIG_EXPR_LIST_DECL_SINGLE(A9, RMII2RXD0, RMII2, RMII2_DESC); 1430 SIG_EXPR_LIST_DECL_SINGLE(A9, RGMII2RXD0, RGMII2); 1431 PIN_DECL_(A9, SIG_EXPR_LIST_PTR(A9, GPIOV4), SIG_EXPR_LIST_PTR(A9, RMII2RXD0), 1432 SIG_EXPR_LIST_PTR(A9, RGMII2RXD0)); 1433 1434 #define E8 173 1435 SIG_EXPR_LIST_DECL_SINGLE(E8, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); 1436 SIG_EXPR_LIST_DECL_SINGLE(E8, RMII2RXD1, RMII2, RMII2_DESC); 1437 SIG_EXPR_LIST_DECL_SINGLE(E8, RGMII2RXD1, RGMII2); 1438 PIN_DECL_(E8, SIG_EXPR_LIST_PTR(E8, GPIOV5), SIG_EXPR_LIST_PTR(E8, RMII2RXD1), 1439 SIG_EXPR_LIST_PTR(E8, RGMII2RXD1)); 1440 1441 #define D8 174 1442 SIG_EXPR_LIST_DECL_SINGLE(D8, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); 1443 SIG_EXPR_LIST_DECL_SINGLE(D8, RMII2CRSDV, RMII2, RMII2_DESC); 1444 SIG_EXPR_LIST_DECL_SINGLE(D8, RGMII2RXD2, RGMII2); 1445 PIN_DECL_(D8, SIG_EXPR_LIST_PTR(D8, GPIOV6), SIG_EXPR_LIST_PTR(D8, RMII2CRSDV), 1446 SIG_EXPR_LIST_PTR(D8, RGMII2RXD2)); 1447 1448 #define C8 175 1449 SIG_EXPR_LIST_DECL_SINGLE(C8, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); 1450 SIG_EXPR_LIST_DECL_SINGLE(C8, RMII2RXER, RMII2, RMII2_DESC); 1451 SIG_EXPR_LIST_DECL_SINGLE(C8, RGMII2RXD3, RGMII2); 1452 PIN_DECL_(C8, SIG_EXPR_LIST_PTR(C8, GPIOV7), SIG_EXPR_LIST_PTR(C8, RMII2RXER), 1453 SIG_EXPR_LIST_PTR(C8, RGMII2RXD3)); 1454 1455 FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, 1456 E10); 1457 FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, 1458 E10); 1459 1460 FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); 1461 FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); 1462 1463 #define L5 176 1464 SIG_EXPR_LIST_DECL_SINGLE(L5, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); 1465 SIG_EXPR_LIST_DECL_SINGLE(L5, ADC0, ADC0); 1466 PIN_DECL_(L5, SIG_EXPR_LIST_PTR(L5, GPIOW0), SIG_EXPR_LIST_PTR(L5, ADC0)); 1467 FUNC_GROUP_DECL(ADC0, L5); 1468 1469 #define L4 177 1470 SIG_EXPR_LIST_DECL_SINGLE(L4, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); 1471 SIG_EXPR_LIST_DECL_SINGLE(L4, ADC1, ADC1); 1472 PIN_DECL_(L4, SIG_EXPR_LIST_PTR(L4, GPIOW1), SIG_EXPR_LIST_PTR(L4, ADC1)); 1473 FUNC_GROUP_DECL(ADC1, L4); 1474 1475 #define L3 178 1476 SIG_EXPR_LIST_DECL_SINGLE(L3, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); 1477 SIG_EXPR_LIST_DECL_SINGLE(L3, ADC2, ADC2); 1478 PIN_DECL_(L3, SIG_EXPR_LIST_PTR(L3, GPIOW2), SIG_EXPR_LIST_PTR(L3, ADC2)); 1479 FUNC_GROUP_DECL(ADC2, L3); 1480 1481 #define L2 179 1482 SIG_EXPR_LIST_DECL_SINGLE(L2, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); 1483 SIG_EXPR_LIST_DECL_SINGLE(L2, ADC3, ADC3); 1484 PIN_DECL_(L2, SIG_EXPR_LIST_PTR(L2, GPIOW3), SIG_EXPR_LIST_PTR(L2, ADC3)); 1485 FUNC_GROUP_DECL(ADC3, L2); 1486 1487 #define L1 180 1488 SIG_EXPR_LIST_DECL_SINGLE(L1, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); 1489 SIG_EXPR_LIST_DECL_SINGLE(L1, ADC4, ADC4); 1490 PIN_DECL_(L1, SIG_EXPR_LIST_PTR(L1, GPIOW4), SIG_EXPR_LIST_PTR(L1, ADC4)); 1491 FUNC_GROUP_DECL(ADC4, L1); 1492 1493 #define M5 181 1494 SIG_EXPR_LIST_DECL_SINGLE(M5, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); 1495 SIG_EXPR_LIST_DECL_SINGLE(M5, ADC5, ADC5); 1496 PIN_DECL_(M5, SIG_EXPR_LIST_PTR(M5, GPIOW5), SIG_EXPR_LIST_PTR(M5, ADC5)); 1497 FUNC_GROUP_DECL(ADC5, M5); 1498 1499 #define M4 182 1500 SIG_EXPR_LIST_DECL_SINGLE(M4, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); 1501 SIG_EXPR_LIST_DECL_SINGLE(M4, ADC6, ADC6); 1502 PIN_DECL_(M4, SIG_EXPR_LIST_PTR(M4, GPIOW6), SIG_EXPR_LIST_PTR(M4, ADC6)); 1503 FUNC_GROUP_DECL(ADC6, M4); 1504 1505 #define M3 183 1506 SIG_EXPR_LIST_DECL_SINGLE(M3, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); 1507 SIG_EXPR_LIST_DECL_SINGLE(M3, ADC7, ADC7); 1508 PIN_DECL_(M3, SIG_EXPR_LIST_PTR(M3, GPIOW7), SIG_EXPR_LIST_PTR(M3, ADC7)); 1509 FUNC_GROUP_DECL(ADC7, M3); 1510 1511 #define M2 184 1512 SIG_EXPR_LIST_DECL_SINGLE(M2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); 1513 SIG_EXPR_LIST_DECL_SINGLE(M2, ADC8, ADC8); 1514 PIN_DECL_(M2, SIG_EXPR_LIST_PTR(M2, GPIOX0), SIG_EXPR_LIST_PTR(M2, ADC8)); 1515 FUNC_GROUP_DECL(ADC8, M2); 1516 1517 #define M1 185 1518 SIG_EXPR_LIST_DECL_SINGLE(M1, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); 1519 SIG_EXPR_LIST_DECL_SINGLE(M1, ADC9, ADC9); 1520 PIN_DECL_(M1, SIG_EXPR_LIST_PTR(M1, GPIOX1), SIG_EXPR_LIST_PTR(M1, ADC9)); 1521 FUNC_GROUP_DECL(ADC9, M1); 1522 1523 #define N5 186 1524 SIG_EXPR_LIST_DECL_SINGLE(N5, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); 1525 SIG_EXPR_LIST_DECL_SINGLE(N5, ADC10, ADC10); 1526 PIN_DECL_(N5, SIG_EXPR_LIST_PTR(N5, GPIOX2), SIG_EXPR_LIST_PTR(N5, ADC10)); 1527 FUNC_GROUP_DECL(ADC10, N5); 1528 1529 #define N4 187 1530 SIG_EXPR_LIST_DECL_SINGLE(N4, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); 1531 SIG_EXPR_LIST_DECL_SINGLE(N4, ADC11, ADC11); 1532 PIN_DECL_(N4, SIG_EXPR_LIST_PTR(N4, GPIOX3), SIG_EXPR_LIST_PTR(N4, ADC11)); 1533 FUNC_GROUP_DECL(ADC11, N4); 1534 1535 #define N3 188 1536 SIG_EXPR_LIST_DECL_SINGLE(N3, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); 1537 SIG_EXPR_LIST_DECL_SINGLE(N3, ADC12, ADC12); 1538 PIN_DECL_(N3, SIG_EXPR_LIST_PTR(N3, GPIOX4), SIG_EXPR_LIST_PTR(N3, ADC12)); 1539 FUNC_GROUP_DECL(ADC12, N3); 1540 1541 #define N2 189 1542 SIG_EXPR_LIST_DECL_SINGLE(N2, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); 1543 SIG_EXPR_LIST_DECL_SINGLE(N2, ADC13, ADC13); 1544 PIN_DECL_(N2, SIG_EXPR_LIST_PTR(N2, GPIOX5), SIG_EXPR_LIST_PTR(N2, ADC13)); 1545 FUNC_GROUP_DECL(ADC13, N2); 1546 1547 #define N1 190 1548 SIG_EXPR_LIST_DECL_SINGLE(N1, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); 1549 SIG_EXPR_LIST_DECL_SINGLE(N1, ADC14, ADC14); 1550 PIN_DECL_(N1, SIG_EXPR_LIST_PTR(N1, GPIOX6), SIG_EXPR_LIST_PTR(N1, ADC14)); 1551 FUNC_GROUP_DECL(ADC14, N1); 1552 1553 #define P5 191 1554 SIG_EXPR_LIST_DECL_SINGLE(P5, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); 1555 SIG_EXPR_LIST_DECL_SINGLE(P5, ADC15, ADC15); 1556 PIN_DECL_(P5, SIG_EXPR_LIST_PTR(P5, GPIOX7), SIG_EXPR_LIST_PTR(P5, ADC15)); 1557 FUNC_GROUP_DECL(ADC15, P5); 1558 1559 #define C21 192 1560 SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); 1561 SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC); 1562 SIG_EXPR_LIST_DECL_DUAL(C21, SIOS3, SIOS3, ACPI); 1563 PIN_DECL_1(C21, GPIOY0, SIOS3); 1564 FUNC_GROUP_DECL(SIOS3, C21); 1565 1566 #define F20 193 1567 SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); 1568 SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC); 1569 SIG_EXPR_LIST_DECL_DUAL(F20, SIOS5, SIOS5, ACPI); 1570 PIN_DECL_1(F20, GPIOY1, SIOS5); 1571 FUNC_GROUP_DECL(SIOS5, F20); 1572 1573 #define G20 194 1574 SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); 1575 SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC); 1576 SIG_EXPR_LIST_DECL_DUAL(G20, SIOPWREQ, SIOPWREQ, ACPI); 1577 PIN_DECL_1(G20, GPIOY2, SIOPWREQ); 1578 FUNC_GROUP_DECL(SIOPWREQ, G20); 1579 1580 #define K20 195 1581 SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); 1582 SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC); 1583 SIG_EXPR_LIST_DECL_DUAL(K20, SIOONCTRL, SIOONCTRL, ACPI); 1584 PIN_DECL_1(K20, GPIOY3, SIOONCTRL); 1585 FUNC_GROUP_DECL(SIOONCTRL, K20); 1586 1587 FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20); 1588 1589 #define R22 200 1590 #define R22_DESC SIG_DESC_SET(SCUA4, 16) 1591 SIG_EXPR_DECL_SINGLE(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC); 1592 SIG_EXPR_DECL_SINGLE(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC); 1593 SIG_EXPR_LIST_DECL_DUAL(R22, ROMA2, ROM8, ROM16); 1594 SIG_EXPR_DECL_SINGLE(VPOB0, VPO12, R22_DESC, VPO12_DESC); 1595 SIG_EXPR_DECL_SINGLE(VPOB0, VPO24, R22_DESC, VPO24_DESC); 1596 SIG_EXPR_DECL_SINGLE(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC); 1597 SIG_EXPR_LIST_DECL(VPOB0, VPO, 1598 SIG_EXPR_PTR(VPOB0, VPO12), 1599 SIG_EXPR_PTR(VPOB0, VPO24), 1600 SIG_EXPR_PTR(VPOB0, VPOOFF1)); 1601 SIG_EXPR_LIST_ALIAS(R22, VPOB0, VPO); 1602 PIN_DECL_2(R22, GPIOZ0, ROMA2, VPOB0); 1603 1604 #define P18 201 1605 #define P18_DESC SIG_DESC_SET(SCUA4, 17) 1606 SIG_EXPR_DECL_SINGLE(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC); 1607 SIG_EXPR_DECL_SINGLE(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC); 1608 SIG_EXPR_LIST_DECL_DUAL(P18, ROMA3, ROM8, ROM16); 1609 SIG_EXPR_DECL_SINGLE(VPOB1, VPO12, P18_DESC, VPO12_DESC); 1610 SIG_EXPR_DECL_SINGLE(VPOB1, VPO24, P18_DESC, VPO24_DESC); 1611 SIG_EXPR_DECL_SINGLE(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC); 1612 SIG_EXPR_LIST_DECL(VPOB1, VPO, 1613 SIG_EXPR_PTR(VPOB1, VPO12), 1614 SIG_EXPR_PTR(VPOB1, VPO24), 1615 SIG_EXPR_PTR(VPOB1, VPOOFF1)); 1616 SIG_EXPR_LIST_ALIAS(P18, VPOB1, VPO); 1617 PIN_DECL_2(P18, GPIOZ1, ROMA3, VPOB1); 1618 1619 #define P19 202 1620 #define P19_DESC SIG_DESC_SET(SCUA4, 18) 1621 SIG_EXPR_DECL_SINGLE(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC); 1622 SIG_EXPR_DECL_SINGLE(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC); 1623 SIG_EXPR_LIST_DECL_DUAL(P19, ROMA4, ROM8, ROM16); 1624 SIG_EXPR_DECL_SINGLE(VPOB2, VPO12, P19_DESC, VPO12_DESC); 1625 SIG_EXPR_DECL_SINGLE(VPOB2, VPO24, P19_DESC, VPO24_DESC); 1626 SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC); 1627 SIG_EXPR_LIST_DECL(VPOB2, VPO, 1628 SIG_EXPR_PTR(VPOB2, VPO12), 1629 SIG_EXPR_PTR(VPOB2, VPO24), 1630 SIG_EXPR_PTR(VPOB2, VPOOFF1)); 1631 SIG_EXPR_LIST_ALIAS(P19, VPOB2, VPO); 1632 PIN_DECL_2(P19, GPIOZ2, ROMA4, VPOB2); 1633 1634 #define P20 203 1635 #define P20_DESC SIG_DESC_SET(SCUA4, 19) 1636 SIG_EXPR_DECL_SINGLE(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC); 1637 SIG_EXPR_DECL_SINGLE(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC); 1638 SIG_EXPR_LIST_DECL_DUAL(P20, ROMA5, ROM8, ROM16); 1639 SIG_EXPR_DECL_SINGLE(VPOB3, VPO12, P20_DESC, VPO12_DESC); 1640 SIG_EXPR_DECL_SINGLE(VPOB3, VPO24, P20_DESC, VPO24_DESC); 1641 SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC); 1642 SIG_EXPR_LIST_DECL(VPOB3, VPO, 1643 SIG_EXPR_PTR(VPOB3, VPO12), 1644 SIG_EXPR_PTR(VPOB3, VPO24), 1645 SIG_EXPR_PTR(VPOB3, VPOOFF1)); 1646 SIG_EXPR_LIST_ALIAS(P20, VPOB3, VPO); 1647 PIN_DECL_2(P20, GPIOZ3, ROMA5, VPOB3); 1648 1649 #define P21 204 1650 #define P21_DESC SIG_DESC_SET(SCUA4, 20) 1651 SIG_EXPR_DECL_SINGLE(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC); 1652 SIG_EXPR_DECL_SINGLE(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC); 1653 SIG_EXPR_LIST_DECL_DUAL(P21, ROMA6, ROM8, ROM16); 1654 SIG_EXPR_DECL_SINGLE(VPOB4, VPO12, P21_DESC, VPO12_DESC); 1655 SIG_EXPR_DECL_SINGLE(VPOB4, VPO24, P21_DESC, VPO24_DESC); 1656 SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC); 1657 SIG_EXPR_LIST_DECL(VPOB4, VPO, 1658 SIG_EXPR_PTR(VPOB4, VPO12), 1659 SIG_EXPR_PTR(VPOB4, VPO24), 1660 SIG_EXPR_PTR(VPOB4, VPOOFF1)); 1661 SIG_EXPR_LIST_ALIAS(P21, VPOB4, VPO); 1662 PIN_DECL_2(P21, GPIOZ4, ROMA6, VPOB4); 1663 1664 #define P22 205 1665 #define P22_DESC SIG_DESC_SET(SCUA4, 21) 1666 SIG_EXPR_DECL_SINGLE(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC); 1667 SIG_EXPR_DECL_SINGLE(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC); 1668 SIG_EXPR_LIST_DECL_DUAL(P22, ROMA7, ROM8, ROM16); 1669 SIG_EXPR_DECL_SINGLE(VPOB5, VPO12, P22_DESC, VPO12_DESC); 1670 SIG_EXPR_DECL_SINGLE(VPOB5, VPO24, P22_DESC, VPO24_DESC); 1671 SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC); 1672 SIG_EXPR_LIST_DECL(VPOB5, VPO, 1673 SIG_EXPR_PTR(VPOB5, VPO12), 1674 SIG_EXPR_PTR(VPOB5, VPO24), 1675 SIG_EXPR_PTR(VPOB5, VPOOFF1)); 1676 SIG_EXPR_LIST_ALIAS(P22, VPOB5, VPO); 1677 PIN_DECL_2(P22, GPIOZ5, ROMA7, VPOB5); 1678 1679 #define M19 206 1680 #define M19_DESC SIG_DESC_SET(SCUA4, 22) 1681 SIG_EXPR_DECL_SINGLE(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC); 1682 SIG_EXPR_DECL_SINGLE(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC); 1683 SIG_EXPR_LIST_DECL_DUAL(M19, ROMA8, ROM8, ROM16); 1684 SIG_EXPR_DECL_SINGLE(VPOB6, VPO12, M19_DESC, VPO12_DESC); 1685 SIG_EXPR_DECL_SINGLE(VPOB6, VPO24, M19_DESC, VPO24_DESC); 1686 SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC); 1687 SIG_EXPR_LIST_DECL(VPOB6, VPO, 1688 SIG_EXPR_PTR(VPOB6, VPO12), 1689 SIG_EXPR_PTR(VPOB6, VPO24), 1690 SIG_EXPR_PTR(VPOB6, VPOOFF1)); 1691 SIG_EXPR_LIST_ALIAS(M19, VPOB6, VPO); 1692 PIN_DECL_2(M19, GPIOZ6, ROMA8, VPOB6); 1693 1694 #define M20 207 1695 #define M20_DESC SIG_DESC_SET(SCUA4, 23) 1696 SIG_EXPR_DECL_SINGLE(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC); 1697 SIG_EXPR_DECL_SINGLE(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC); 1698 SIG_EXPR_LIST_DECL_DUAL(M20, ROMA9, ROM8, ROM16); 1699 SIG_EXPR_DECL_SINGLE(VPOB7, VPO12, M20_DESC, VPO12_DESC); 1700 SIG_EXPR_DECL_SINGLE(VPOB7, VPO24, M20_DESC, VPO24_DESC); 1701 SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC); 1702 SIG_EXPR_LIST_DECL(VPOB7, VPO, 1703 SIG_EXPR_PTR(VPOB7, VPO12), 1704 SIG_EXPR_PTR(VPOB7, VPO24), 1705 SIG_EXPR_PTR(VPOB7, VPOOFF1)); 1706 SIG_EXPR_LIST_ALIAS(M20, VPOB7, VPO); 1707 PIN_DECL_2(M20, GPIOZ7, ROMA9, VPOB7); 1708 1709 #define M21 208 1710 #define M21_DESC SIG_DESC_SET(SCUA4, 24) 1711 SIG_EXPR_DECL_SINGLE(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC); 1712 SIG_EXPR_DECL_SINGLE(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC); 1713 SIG_EXPR_LIST_DECL_DUAL(M21, ROMA10, ROM8, ROM16); 1714 SIG_EXPR_DECL_SINGLE(VPOG0, VPO12, M21_DESC, VPO12_DESC); 1715 SIG_EXPR_DECL_SINGLE(VPOG0, VPO24, M21_DESC, VPO24_DESC); 1716 SIG_EXPR_DECL_SINGLE(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC); 1717 SIG_EXPR_LIST_DECL(VPOG0, VPO, 1718 SIG_EXPR_PTR(VPOG0, VPO12), 1719 SIG_EXPR_PTR(VPOG0, VPO24), 1720 SIG_EXPR_PTR(VPOG0, VPOOFF1)); 1721 SIG_EXPR_LIST_ALIAS(M21, VPOG0, VPO); 1722 PIN_DECL_2(M21, GPIOAA0, ROMA10, VPOG0); 1723 1724 #define M22 209 1725 #define M22_DESC SIG_DESC_SET(SCUA4, 25) 1726 SIG_EXPR_DECL_SINGLE(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC); 1727 SIG_EXPR_DECL_SINGLE(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC); 1728 SIG_EXPR_LIST_DECL_DUAL(M22, ROMA11, ROM8, ROM16); 1729 SIG_EXPR_DECL_SINGLE(VPOG1, VPO12, M22_DESC, VPO12_DESC); 1730 SIG_EXPR_DECL_SINGLE(VPOG1, VPO24, M22_DESC, VPO24_DESC); 1731 SIG_EXPR_DECL_SINGLE(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC); 1732 SIG_EXPR_LIST_DECL(VPOG1, VPO, 1733 SIG_EXPR_PTR(VPOG1, VPO12), 1734 SIG_EXPR_PTR(VPOG1, VPO24), 1735 SIG_EXPR_PTR(VPOG1, VPOOFF1)); 1736 SIG_EXPR_LIST_ALIAS(M22, VPOG1, VPO); 1737 PIN_DECL_2(M22, GPIOAA1, ROMA11, VPOG1); 1738 1739 #define L18 210 1740 #define L18_DESC SIG_DESC_SET(SCUA4, 26) 1741 SIG_EXPR_DECL_SINGLE(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC); 1742 SIG_EXPR_DECL_SINGLE(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC); 1743 SIG_EXPR_LIST_DECL_DUAL(L18, ROMA12, ROM8, ROM16); 1744 SIG_EXPR_DECL_SINGLE(VPOG2, VPO12, L18_DESC, VPO12_DESC); 1745 SIG_EXPR_DECL_SINGLE(VPOG2, VPO24, L18_DESC, VPO24_DESC); 1746 SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC); 1747 SIG_EXPR_LIST_DECL(VPOG2, VPO, 1748 SIG_EXPR_PTR(VPOG2, VPO12), 1749 SIG_EXPR_PTR(VPOG2, VPO24), 1750 SIG_EXPR_PTR(VPOG2, VPOOFF1)); 1751 SIG_EXPR_LIST_ALIAS(L18, VPOG2, VPO); 1752 PIN_DECL_2(L18, GPIOAA2, ROMA12, VPOG2); 1753 1754 #define L19 211 1755 #define L19_DESC SIG_DESC_SET(SCUA4, 27) 1756 SIG_EXPR_DECL_SINGLE(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC); 1757 SIG_EXPR_DECL_SINGLE(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC); 1758 SIG_EXPR_LIST_DECL_DUAL(L19, ROMA13, ROM8, ROM16); 1759 SIG_EXPR_DECL_SINGLE(VPOG3, VPO12, L19_DESC, VPO12_DESC); 1760 SIG_EXPR_DECL_SINGLE(VPOG3, VPO24, L19_DESC, VPO24_DESC); 1761 SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC); 1762 SIG_EXPR_LIST_DECL(VPOG3, VPO, 1763 SIG_EXPR_PTR(VPOG3, VPO12), 1764 SIG_EXPR_PTR(VPOG3, VPO24), 1765 SIG_EXPR_PTR(VPOG3, VPOOFF1)); 1766 SIG_EXPR_LIST_ALIAS(L19, VPOG3, VPO); 1767 PIN_DECL_2(L19, GPIOAA3, ROMA13, VPOG3); 1768 1769 #define L20 212 1770 #define L20_DESC SIG_DESC_SET(SCUA4, 28) 1771 SIG_EXPR_DECL_SINGLE(ROMA14, ROM8, L20_DESC, VPO_OFF_12); 1772 SIG_EXPR_DECL_SINGLE(ROMA14, ROM16, L20_DESC, VPO_OFF_12); 1773 SIG_EXPR_LIST_DECL_DUAL(L20, ROMA14, ROM8, ROM16); 1774 SIG_EXPR_DECL_SINGLE(VPOG4, VPO24, L20_DESC, VPO24_DESC); 1775 SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC); 1776 SIG_EXPR_LIST_DECL_DUAL(L20, VPOG4, VPO24, VPOOFF1); 1777 PIN_DECL_2(L20, GPIOAA4, ROMA14, VPOG4); 1778 1779 #define L21 213 1780 #define L21_DESC SIG_DESC_SET(SCUA4, 29) 1781 SIG_EXPR_DECL_SINGLE(ROMA15, ROM8, L21_DESC, VPO_OFF_12); 1782 SIG_EXPR_DECL_SINGLE(ROMA15, ROM16, L21_DESC, VPO_OFF_12); 1783 SIG_EXPR_LIST_DECL_DUAL(L21, ROMA15, ROM8, ROM16); 1784 SIG_EXPR_DECL_SINGLE(VPOG5, VPO24, L21_DESC, VPO24_DESC); 1785 SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC); 1786 SIG_EXPR_LIST_DECL_DUAL(L21, VPOG5, VPO24, VPOOFF1); 1787 PIN_DECL_2(L21, GPIOAA5, ROMA15, VPOG5); 1788 1789 #define T18 214 1790 #define T18_DESC SIG_DESC_SET(SCUA4, 30) 1791 SIG_EXPR_DECL_SINGLE(ROMA16, ROM8, T18_DESC, VPO_OFF_12); 1792 SIG_EXPR_DECL_SINGLE(ROMA16, ROM16, T18_DESC, VPO_OFF_12); 1793 SIG_EXPR_LIST_DECL_DUAL(T18, ROMA16, ROM8, ROM16); 1794 SIG_EXPR_DECL_SINGLE(VPOG6, VPO24, T18_DESC, VPO24_DESC); 1795 SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC); 1796 SIG_EXPR_LIST_DECL_DUAL(T18, VPOG6, VPO24, VPOOFF1); 1797 PIN_DECL_2(T18, GPIOAA6, ROMA16, VPOG6); 1798 1799 #define N18 215 1800 #define N18_DESC SIG_DESC_SET(SCUA4, 31) 1801 SIG_EXPR_DECL_SINGLE(ROMA17, ROM8, N18_DESC, VPO_OFF_12); 1802 SIG_EXPR_DECL_SINGLE(ROMA17, ROM16, N18_DESC, VPO_OFF_12); 1803 SIG_EXPR_LIST_DECL_DUAL(N18, ROMA17, ROM8, ROM16); 1804 SIG_EXPR_DECL_SINGLE(VPOG7, VPO24, N18_DESC, VPO24_DESC); 1805 SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC); 1806 SIG_EXPR_LIST_DECL_DUAL(N18, VPOG7, VPO24, VPOOFF1); 1807 PIN_DECL_2(N18, GPIOAA7, ROMA17, VPOG7); 1808 1809 #define N19 216 1810 #define N19_DESC SIG_DESC_SET(SCUA8, 0) 1811 SIG_EXPR_DECL_SINGLE(ROMA18, ROM8, N19_DESC, VPO_OFF_12); 1812 SIG_EXPR_DECL_SINGLE(ROMA18, ROM16, N19_DESC, VPO_OFF_12); 1813 SIG_EXPR_LIST_DECL_DUAL(N19, ROMA18, ROM8, ROM16); 1814 SIG_EXPR_DECL_SINGLE(VPOR0, VPO24, N19_DESC, VPO24_DESC); 1815 SIG_EXPR_DECL_SINGLE(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC); 1816 SIG_EXPR_LIST_DECL_DUAL(N19, VPOR0, VPO24, VPOOFF1); 1817 PIN_DECL_2(N19, GPIOAB0, ROMA18, VPOR0); 1818 1819 #define M18 217 1820 #define M18_DESC SIG_DESC_SET(SCUA8, 1) 1821 SIG_EXPR_DECL_SINGLE(ROMA19, ROM8, M18_DESC, VPO_OFF_12); 1822 SIG_EXPR_DECL_SINGLE(ROMA19, ROM16, M18_DESC, VPO_OFF_12); 1823 SIG_EXPR_LIST_DECL_DUAL(M18, ROMA19, ROM8, ROM16); 1824 SIG_EXPR_DECL_SINGLE(VPOR1, VPO24, M18_DESC, VPO24_DESC); 1825 SIG_EXPR_DECL_SINGLE(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC); 1826 SIG_EXPR_LIST_DECL_DUAL(M18, VPOR1, VPO24, VPOOFF1); 1827 PIN_DECL_2(M18, GPIOAB1, ROMA19, VPOR1); 1828 1829 #define N22 218 1830 #define N22_DESC SIG_DESC_SET(SCUA8, 2) 1831 SIG_EXPR_DECL_SINGLE(ROMA20, ROM8, N22_DESC, VPO_OFF_12); 1832 SIG_EXPR_DECL_SINGLE(ROMA20, ROM16, N22_DESC, VPO_OFF_12); 1833 SIG_EXPR_LIST_DECL_DUAL(N22, ROMA20, ROM8, ROM16); 1834 SIG_EXPR_DECL_SINGLE(VPOR2, VPO24, N22_DESC, VPO24_DESC); 1835 SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC); 1836 SIG_EXPR_LIST_DECL_DUAL(N22, VPOR2, VPO24, VPOOFF1); 1837 PIN_DECL_2(N22, GPIOAB2, ROMA20, VPOR2); 1838 1839 #define N20 219 1840 #define N20_DESC SIG_DESC_SET(SCUA8, 3) 1841 SIG_EXPR_DECL_SINGLE(ROMA21, ROM8, N20_DESC, VPO_OFF_12); 1842 SIG_EXPR_DECL_SINGLE(ROMA21, ROM16, N20_DESC, VPO_OFF_12); 1843 SIG_EXPR_LIST_DECL_DUAL(N20, ROMA21, ROM8, ROM16); 1844 SIG_EXPR_DECL_SINGLE(VPOR3, VPO24, N20_DESC, VPO24_DESC); 1845 SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC); 1846 SIG_EXPR_LIST_DECL_DUAL(N20, VPOR3, VPO24, VPOOFF1); 1847 PIN_DECL_2(N20, GPIOAB3, ROMA21, VPOR3); 1848 1849 FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22, 1850 U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18, 1851 L19, L20, L21, T18, N18, N19, M18, N22, N20); 1852 FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18, 1853 A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19, 1854 P20, P21, P22, M19, M20, M21, M22, L18, L19, L20, L21, T18, 1855 N18, N19, M18, N22, N20); 1856 FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19, 1857 M20, M21, M22, L18, L19, L20, L21, T18, N18, N19, M18, N22, 1858 N20); 1859 FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19, 1860 P20, P21, P22, M19, M20, M21, M22, L18, L19); 1861 1862 #define USB11H2_DESC SIG_DESC_SET(SCU90, 3) 1863 #define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0) 1864 1865 #define K4 220 1866 SIG_EXPR_LIST_DECL_SINGLE(K4, USB11HDP2, USB11H2, USB11H2_DESC); 1867 SIG_EXPR_LIST_DECL_SINGLE(K4, USB11DP1, USB11D1, USB11D1_DESC); 1868 PIN_DECL_(K4, SIG_EXPR_LIST_PTR(K4, USB11HDP2), 1869 SIG_EXPR_LIST_PTR(K4, USB11DP1)); 1870 1871 #define K3 221 1872 SIG_EXPR_LIST_DECL_SINGLE(K3, USB11HDN1, USB11H2, USB11H2_DESC); 1873 SIG_EXPR_LIST_DECL_SINGLE(K3, USB11DDN1, USB11D1, USB11D1_DESC); 1874 PIN_DECL_(K3, SIG_EXPR_LIST_PTR(K3, USB11HDN1), 1875 SIG_EXPR_LIST_PTR(K3, USB11DDN1)); 1876 1877 FUNC_GROUP_DECL(USB11H2, K4, K3); 1878 FUNC_GROUP_DECL(USB11D1, K4, K3); 1879 1880 #define USB2H1_DESC SIG_DESC_SET(SCU90, 29) 1881 #define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0) 1882 1883 #define AB21 222 1884 SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2HDP1, USB2H1, USB2H1_DESC); 1885 SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2DDP1, USB2D1, USB2D1_DESC); 1886 PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, USB2HDP1), 1887 SIG_EXPR_LIST_PTR(AB21, USB2DDP1)); 1888 1889 #define AB20 223 1890 SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2HDN1, USB2H1, USB2H1_DESC); 1891 SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2DDN1, USB2D1, USB2D1_DESC); 1892 PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, USB2HDN1), 1893 SIG_EXPR_LIST_PTR(AB20, USB2DDN1)); 1894 1895 FUNC_GROUP_DECL(USB2H1, AB21, AB20); 1896 FUNC_GROUP_DECL(USB2D1, AB21, AB20); 1897 1898 /* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216 1899 * pins becomes 220. Four additional non-GPIO-capable pins are present for USB. 1900 */ 1901 #define ASPEED_G4_NR_PINS 224 1902 1903 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ 1904 1905 static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { 1906 ASPEED_PINCTRL_PIN(A1), 1907 ASPEED_PINCTRL_PIN(A10), 1908 ASPEED_PINCTRL_PIN(A11), 1909 ASPEED_PINCTRL_PIN(A12), 1910 ASPEED_PINCTRL_PIN(A13), 1911 ASPEED_PINCTRL_PIN(A14), 1912 ASPEED_PINCTRL_PIN(A15), 1913 ASPEED_PINCTRL_PIN(A16), 1914 ASPEED_PINCTRL_PIN(A17), 1915 ASPEED_PINCTRL_PIN(A18), 1916 ASPEED_PINCTRL_PIN(A19), 1917 ASPEED_PINCTRL_PIN(A2), 1918 ASPEED_PINCTRL_PIN(A20), 1919 ASPEED_PINCTRL_PIN(A3), 1920 ASPEED_PINCTRL_PIN(A4), 1921 ASPEED_PINCTRL_PIN(A5), 1922 ASPEED_PINCTRL_PIN(A6), 1923 ASPEED_PINCTRL_PIN(A7), 1924 ASPEED_PINCTRL_PIN(A8), 1925 ASPEED_PINCTRL_PIN(A9), 1926 ASPEED_PINCTRL_PIN(AA1), 1927 ASPEED_PINCTRL_PIN(AA2), 1928 ASPEED_PINCTRL_PIN(AA22), 1929 ASPEED_PINCTRL_PIN(AA3), 1930 ASPEED_PINCTRL_PIN(AA4), 1931 ASPEED_PINCTRL_PIN(AA5), 1932 ASPEED_PINCTRL_PIN(AA6), 1933 ASPEED_PINCTRL_PIN(AA7), 1934 ASPEED_PINCTRL_PIN(AB1), 1935 ASPEED_PINCTRL_PIN(AB2), 1936 ASPEED_PINCTRL_PIN(AB3), 1937 ASPEED_PINCTRL_PIN(AB4), 1938 ASPEED_PINCTRL_PIN(AB5), 1939 ASPEED_PINCTRL_PIN(AB6), 1940 ASPEED_PINCTRL_PIN(AB7), 1941 ASPEED_PINCTRL_PIN(AB20), 1942 ASPEED_PINCTRL_PIN(AB21), 1943 ASPEED_PINCTRL_PIN(B1), 1944 ASPEED_PINCTRL_PIN(B10), 1945 ASPEED_PINCTRL_PIN(B11), 1946 ASPEED_PINCTRL_PIN(B12), 1947 ASPEED_PINCTRL_PIN(B13), 1948 ASPEED_PINCTRL_PIN(B14), 1949 ASPEED_PINCTRL_PIN(B15), 1950 ASPEED_PINCTRL_PIN(B16), 1951 ASPEED_PINCTRL_PIN(B17), 1952 ASPEED_PINCTRL_PIN(B18), 1953 ASPEED_PINCTRL_PIN(B19), 1954 ASPEED_PINCTRL_PIN(B2), 1955 ASPEED_PINCTRL_PIN(B22), 1956 ASPEED_PINCTRL_PIN(B3), 1957 ASPEED_PINCTRL_PIN(B4), 1958 ASPEED_PINCTRL_PIN(B5), 1959 ASPEED_PINCTRL_PIN(B6), 1960 ASPEED_PINCTRL_PIN(B7), 1961 ASPEED_PINCTRL_PIN(B9), 1962 ASPEED_PINCTRL_PIN(C1), 1963 ASPEED_PINCTRL_PIN(C10), 1964 ASPEED_PINCTRL_PIN(C11), 1965 ASPEED_PINCTRL_PIN(C12), 1966 ASPEED_PINCTRL_PIN(C13), 1967 ASPEED_PINCTRL_PIN(C14), 1968 ASPEED_PINCTRL_PIN(C15), 1969 ASPEED_PINCTRL_PIN(C16), 1970 ASPEED_PINCTRL_PIN(C17), 1971 ASPEED_PINCTRL_PIN(C18), 1972 ASPEED_PINCTRL_PIN(C2), 1973 ASPEED_PINCTRL_PIN(C20), 1974 ASPEED_PINCTRL_PIN(C21), 1975 ASPEED_PINCTRL_PIN(C22), 1976 ASPEED_PINCTRL_PIN(C3), 1977 ASPEED_PINCTRL_PIN(C4), 1978 ASPEED_PINCTRL_PIN(C5), 1979 ASPEED_PINCTRL_PIN(C6), 1980 ASPEED_PINCTRL_PIN(C7), 1981 ASPEED_PINCTRL_PIN(C8), 1982 ASPEED_PINCTRL_PIN(C9), 1983 ASPEED_PINCTRL_PIN(D1), 1984 ASPEED_PINCTRL_PIN(D10), 1985 ASPEED_PINCTRL_PIN(D11), 1986 ASPEED_PINCTRL_PIN(D12), 1987 ASPEED_PINCTRL_PIN(D13), 1988 ASPEED_PINCTRL_PIN(D14), 1989 ASPEED_PINCTRL_PIN(D15), 1990 ASPEED_PINCTRL_PIN(D16), 1991 ASPEED_PINCTRL_PIN(D17), 1992 ASPEED_PINCTRL_PIN(D18), 1993 ASPEED_PINCTRL_PIN(D19), 1994 ASPEED_PINCTRL_PIN(D2), 1995 ASPEED_PINCTRL_PIN(D3), 1996 ASPEED_PINCTRL_PIN(D4), 1997 ASPEED_PINCTRL_PIN(D5), 1998 ASPEED_PINCTRL_PIN(D6), 1999 ASPEED_PINCTRL_PIN(D7), 2000 ASPEED_PINCTRL_PIN(D8), 2001 ASPEED_PINCTRL_PIN(D9), 2002 ASPEED_PINCTRL_PIN(E10), 2003 ASPEED_PINCTRL_PIN(E11), 2004 ASPEED_PINCTRL_PIN(E12), 2005 ASPEED_PINCTRL_PIN(E13), 2006 ASPEED_PINCTRL_PIN(E14), 2007 ASPEED_PINCTRL_PIN(E15), 2008 ASPEED_PINCTRL_PIN(E16), 2009 ASPEED_PINCTRL_PIN(E18), 2010 ASPEED_PINCTRL_PIN(E19), 2011 ASPEED_PINCTRL_PIN(E2), 2012 ASPEED_PINCTRL_PIN(E20), 2013 ASPEED_PINCTRL_PIN(E3), 2014 ASPEED_PINCTRL_PIN(E5), 2015 ASPEED_PINCTRL_PIN(E6), 2016 ASPEED_PINCTRL_PIN(E7), 2017 ASPEED_PINCTRL_PIN(E8), 2018 ASPEED_PINCTRL_PIN(E9), 2019 ASPEED_PINCTRL_PIN(F18), 2020 ASPEED_PINCTRL_PIN(F20), 2021 ASPEED_PINCTRL_PIN(F3), 2022 ASPEED_PINCTRL_PIN(F4), 2023 ASPEED_PINCTRL_PIN(F5), 2024 ASPEED_PINCTRL_PIN(G18), 2025 ASPEED_PINCTRL_PIN(G19), 2026 ASPEED_PINCTRL_PIN(G20), 2027 ASPEED_PINCTRL_PIN(G5), 2028 ASPEED_PINCTRL_PIN(H1), 2029 ASPEED_PINCTRL_PIN(H18), 2030 ASPEED_PINCTRL_PIN(H19), 2031 ASPEED_PINCTRL_PIN(H2), 2032 ASPEED_PINCTRL_PIN(H20), 2033 ASPEED_PINCTRL_PIN(H3), 2034 ASPEED_PINCTRL_PIN(H4), 2035 ASPEED_PINCTRL_PIN(J20), 2036 ASPEED_PINCTRL_PIN(J21), 2037 ASPEED_PINCTRL_PIN(J3), 2038 ASPEED_PINCTRL_PIN(J4), 2039 ASPEED_PINCTRL_PIN(J5), 2040 ASPEED_PINCTRL_PIN(K18), 2041 ASPEED_PINCTRL_PIN(K20), 2042 ASPEED_PINCTRL_PIN(K3), 2043 ASPEED_PINCTRL_PIN(K4), 2044 ASPEED_PINCTRL_PIN(K5), 2045 ASPEED_PINCTRL_PIN(L1), 2046 ASPEED_PINCTRL_PIN(L18), 2047 ASPEED_PINCTRL_PIN(L19), 2048 ASPEED_PINCTRL_PIN(L2), 2049 ASPEED_PINCTRL_PIN(L20), 2050 ASPEED_PINCTRL_PIN(L21), 2051 ASPEED_PINCTRL_PIN(L22), 2052 ASPEED_PINCTRL_PIN(L3), 2053 ASPEED_PINCTRL_PIN(L4), 2054 ASPEED_PINCTRL_PIN(L5), 2055 ASPEED_PINCTRL_PIN(M1), 2056 ASPEED_PINCTRL_PIN(M18), 2057 ASPEED_PINCTRL_PIN(M19), 2058 ASPEED_PINCTRL_PIN(M2), 2059 ASPEED_PINCTRL_PIN(M20), 2060 ASPEED_PINCTRL_PIN(M21), 2061 ASPEED_PINCTRL_PIN(M22), 2062 ASPEED_PINCTRL_PIN(M3), 2063 ASPEED_PINCTRL_PIN(M4), 2064 ASPEED_PINCTRL_PIN(M5), 2065 ASPEED_PINCTRL_PIN(N1), 2066 ASPEED_PINCTRL_PIN(N18), 2067 ASPEED_PINCTRL_PIN(N19), 2068 ASPEED_PINCTRL_PIN(N2), 2069 ASPEED_PINCTRL_PIN(N20), 2070 ASPEED_PINCTRL_PIN(N21), 2071 ASPEED_PINCTRL_PIN(N22), 2072 ASPEED_PINCTRL_PIN(N3), 2073 ASPEED_PINCTRL_PIN(N4), 2074 ASPEED_PINCTRL_PIN(N5), 2075 ASPEED_PINCTRL_PIN(P18), 2076 ASPEED_PINCTRL_PIN(P19), 2077 ASPEED_PINCTRL_PIN(P20), 2078 ASPEED_PINCTRL_PIN(P21), 2079 ASPEED_PINCTRL_PIN(P22), 2080 ASPEED_PINCTRL_PIN(P5), 2081 ASPEED_PINCTRL_PIN(R18), 2082 ASPEED_PINCTRL_PIN(R22), 2083 ASPEED_PINCTRL_PIN(T1), 2084 ASPEED_PINCTRL_PIN(T18), 2085 ASPEED_PINCTRL_PIN(T19), 2086 ASPEED_PINCTRL_PIN(T2), 2087 ASPEED_PINCTRL_PIN(T4), 2088 ASPEED_PINCTRL_PIN(T5), 2089 ASPEED_PINCTRL_PIN(U1), 2090 ASPEED_PINCTRL_PIN(U18), 2091 ASPEED_PINCTRL_PIN(U19), 2092 ASPEED_PINCTRL_PIN(U2), 2093 ASPEED_PINCTRL_PIN(U20), 2094 ASPEED_PINCTRL_PIN(U21), 2095 ASPEED_PINCTRL_PIN(U3), 2096 ASPEED_PINCTRL_PIN(U4), 2097 ASPEED_PINCTRL_PIN(U5), 2098 ASPEED_PINCTRL_PIN(V1), 2099 ASPEED_PINCTRL_PIN(V2), 2100 ASPEED_PINCTRL_PIN(V20), 2101 ASPEED_PINCTRL_PIN(V21), 2102 ASPEED_PINCTRL_PIN(V22), 2103 ASPEED_PINCTRL_PIN(V3), 2104 ASPEED_PINCTRL_PIN(V4), 2105 ASPEED_PINCTRL_PIN(V5), 2106 ASPEED_PINCTRL_PIN(V6), 2107 ASPEED_PINCTRL_PIN(V7), 2108 ASPEED_PINCTRL_PIN(W1), 2109 ASPEED_PINCTRL_PIN(W2), 2110 ASPEED_PINCTRL_PIN(W21), 2111 ASPEED_PINCTRL_PIN(W22), 2112 ASPEED_PINCTRL_PIN(W3), 2113 ASPEED_PINCTRL_PIN(W4), 2114 ASPEED_PINCTRL_PIN(W5), 2115 ASPEED_PINCTRL_PIN(W6), 2116 ASPEED_PINCTRL_PIN(W7), 2117 ASPEED_PINCTRL_PIN(Y1), 2118 ASPEED_PINCTRL_PIN(Y2), 2119 ASPEED_PINCTRL_PIN(Y21), 2120 ASPEED_PINCTRL_PIN(Y22), 2121 ASPEED_PINCTRL_PIN(Y3), 2122 ASPEED_PINCTRL_PIN(Y4), 2123 ASPEED_PINCTRL_PIN(Y5), 2124 ASPEED_PINCTRL_PIN(Y6), 2125 ASPEED_PINCTRL_PIN(Y7), 2126 }; 2127 2128 static const struct aspeed_pin_group aspeed_g4_groups[] = { 2129 ASPEED_PINCTRL_GROUP(ACPI), 2130 ASPEED_PINCTRL_GROUP(ADC0), 2131 ASPEED_PINCTRL_GROUP(ADC1), 2132 ASPEED_PINCTRL_GROUP(ADC10), 2133 ASPEED_PINCTRL_GROUP(ADC11), 2134 ASPEED_PINCTRL_GROUP(ADC12), 2135 ASPEED_PINCTRL_GROUP(ADC13), 2136 ASPEED_PINCTRL_GROUP(ADC14), 2137 ASPEED_PINCTRL_GROUP(ADC15), 2138 ASPEED_PINCTRL_GROUP(ADC2), 2139 ASPEED_PINCTRL_GROUP(ADC3), 2140 ASPEED_PINCTRL_GROUP(ADC4), 2141 ASPEED_PINCTRL_GROUP(ADC5), 2142 ASPEED_PINCTRL_GROUP(ADC6), 2143 ASPEED_PINCTRL_GROUP(ADC7), 2144 ASPEED_PINCTRL_GROUP(ADC8), 2145 ASPEED_PINCTRL_GROUP(ADC9), 2146 ASPEED_PINCTRL_GROUP(BMCINT), 2147 ASPEED_PINCTRL_GROUP(DDCCLK), 2148 ASPEED_PINCTRL_GROUP(DDCDAT), 2149 ASPEED_PINCTRL_GROUP(EXTRST), 2150 ASPEED_PINCTRL_GROUP(FLACK), 2151 ASPEED_PINCTRL_GROUP(FLBUSY), 2152 ASPEED_PINCTRL_GROUP(FLWP), 2153 ASPEED_PINCTRL_GROUP(GPID), 2154 ASPEED_PINCTRL_GROUP(GPID0), 2155 ASPEED_PINCTRL_GROUP(GPID2), 2156 ASPEED_PINCTRL_GROUP(GPID4), 2157 ASPEED_PINCTRL_GROUP(GPID6), 2158 ASPEED_PINCTRL_GROUP(GPIE0), 2159 ASPEED_PINCTRL_GROUP(GPIE2), 2160 ASPEED_PINCTRL_GROUP(GPIE4), 2161 ASPEED_PINCTRL_GROUP(GPIE6), 2162 ASPEED_PINCTRL_GROUP(I2C10), 2163 ASPEED_PINCTRL_GROUP(I2C11), 2164 ASPEED_PINCTRL_GROUP(I2C12), 2165 ASPEED_PINCTRL_GROUP(I2C13), 2166 ASPEED_PINCTRL_GROUP(I2C14), 2167 ASPEED_PINCTRL_GROUP(I2C3), 2168 ASPEED_PINCTRL_GROUP(I2C4), 2169 ASPEED_PINCTRL_GROUP(I2C5), 2170 ASPEED_PINCTRL_GROUP(I2C6), 2171 ASPEED_PINCTRL_GROUP(I2C7), 2172 ASPEED_PINCTRL_GROUP(I2C8), 2173 ASPEED_PINCTRL_GROUP(I2C9), 2174 ASPEED_PINCTRL_GROUP(LPCPD), 2175 ASPEED_PINCTRL_GROUP(LPCPME), 2176 ASPEED_PINCTRL_GROUP(LPCRST), 2177 ASPEED_PINCTRL_GROUP(LPCSMI), 2178 ASPEED_PINCTRL_GROUP(MAC1LINK), 2179 ASPEED_PINCTRL_GROUP(MAC2LINK), 2180 ASPEED_PINCTRL_GROUP(MDIO1), 2181 ASPEED_PINCTRL_GROUP(MDIO2), 2182 ASPEED_PINCTRL_GROUP(NCTS1), 2183 ASPEED_PINCTRL_GROUP(NCTS2), 2184 ASPEED_PINCTRL_GROUP(NCTS3), 2185 ASPEED_PINCTRL_GROUP(NCTS4), 2186 ASPEED_PINCTRL_GROUP(NDCD1), 2187 ASPEED_PINCTRL_GROUP(NDCD2), 2188 ASPEED_PINCTRL_GROUP(NDCD3), 2189 ASPEED_PINCTRL_GROUP(NDCD4), 2190 ASPEED_PINCTRL_GROUP(NDSR1), 2191 ASPEED_PINCTRL_GROUP(NDSR2), 2192 ASPEED_PINCTRL_GROUP(NDSR3), 2193 ASPEED_PINCTRL_GROUP(NDSR4), 2194 ASPEED_PINCTRL_GROUP(NDTR1), 2195 ASPEED_PINCTRL_GROUP(NDTR2), 2196 ASPEED_PINCTRL_GROUP(NDTR3), 2197 ASPEED_PINCTRL_GROUP(NDTR4), 2198 ASPEED_PINCTRL_GROUP(NDTS4), 2199 ASPEED_PINCTRL_GROUP(NRI1), 2200 ASPEED_PINCTRL_GROUP(NRI2), 2201 ASPEED_PINCTRL_GROUP(NRI3), 2202 ASPEED_PINCTRL_GROUP(NRI4), 2203 ASPEED_PINCTRL_GROUP(NRTS1), 2204 ASPEED_PINCTRL_GROUP(NRTS2), 2205 ASPEED_PINCTRL_GROUP(NRTS3), 2206 ASPEED_PINCTRL_GROUP(OSCCLK), 2207 ASPEED_PINCTRL_GROUP(PWM0), 2208 ASPEED_PINCTRL_GROUP(PWM1), 2209 ASPEED_PINCTRL_GROUP(PWM2), 2210 ASPEED_PINCTRL_GROUP(PWM3), 2211 ASPEED_PINCTRL_GROUP(PWM4), 2212 ASPEED_PINCTRL_GROUP(PWM5), 2213 ASPEED_PINCTRL_GROUP(PWM6), 2214 ASPEED_PINCTRL_GROUP(PWM7), 2215 ASPEED_PINCTRL_GROUP(RGMII1), 2216 ASPEED_PINCTRL_GROUP(RGMII2), 2217 ASPEED_PINCTRL_GROUP(RMII1), 2218 ASPEED_PINCTRL_GROUP(RMII2), 2219 ASPEED_PINCTRL_GROUP(ROM16), 2220 ASPEED_PINCTRL_GROUP(ROM8), 2221 ASPEED_PINCTRL_GROUP(ROMCS1), 2222 ASPEED_PINCTRL_GROUP(ROMCS2), 2223 ASPEED_PINCTRL_GROUP(ROMCS3), 2224 ASPEED_PINCTRL_GROUP(ROMCS4), 2225 ASPEED_PINCTRL_GROUP(RXD1), 2226 ASPEED_PINCTRL_GROUP(RXD2), 2227 ASPEED_PINCTRL_GROUP(RXD3), 2228 ASPEED_PINCTRL_GROUP(RXD4), 2229 ASPEED_PINCTRL_GROUP(SALT1), 2230 ASPEED_PINCTRL_GROUP(SALT2), 2231 ASPEED_PINCTRL_GROUP(SALT3), 2232 ASPEED_PINCTRL_GROUP(SALT4), 2233 ASPEED_PINCTRL_GROUP(SD1), 2234 ASPEED_PINCTRL_GROUP(SD2), 2235 ASPEED_PINCTRL_GROUP(SGPMCK), 2236 ASPEED_PINCTRL_GROUP(SGPMI), 2237 ASPEED_PINCTRL_GROUP(SGPMLD), 2238 ASPEED_PINCTRL_GROUP(SGPMO), 2239 ASPEED_PINCTRL_GROUP(SGPSCK), 2240 ASPEED_PINCTRL_GROUP(SGPSI0), 2241 ASPEED_PINCTRL_GROUP(SGPSI1), 2242 ASPEED_PINCTRL_GROUP(SGPSLD), 2243 ASPEED_PINCTRL_GROUP(SIOONCTRL), 2244 ASPEED_PINCTRL_GROUP(SIOPBI), 2245 ASPEED_PINCTRL_GROUP(SIOPBO), 2246 ASPEED_PINCTRL_GROUP(SIOPWREQ), 2247 ASPEED_PINCTRL_GROUP(SIOPWRGD), 2248 ASPEED_PINCTRL_GROUP(SIOS3), 2249 ASPEED_PINCTRL_GROUP(SIOS5), 2250 ASPEED_PINCTRL_GROUP(SIOSCI), 2251 ASPEED_PINCTRL_GROUP(SPI1), 2252 ASPEED_PINCTRL_GROUP(SPI1DEBUG), 2253 ASPEED_PINCTRL_GROUP(SPI1PASSTHRU), 2254 ASPEED_PINCTRL_GROUP(SPICS1), 2255 ASPEED_PINCTRL_GROUP(TIMER3), 2256 ASPEED_PINCTRL_GROUP(TIMER4), 2257 ASPEED_PINCTRL_GROUP(TIMER5), 2258 ASPEED_PINCTRL_GROUP(TIMER6), 2259 ASPEED_PINCTRL_GROUP(TIMER7), 2260 ASPEED_PINCTRL_GROUP(TIMER8), 2261 ASPEED_PINCTRL_GROUP(TXD1), 2262 ASPEED_PINCTRL_GROUP(TXD2), 2263 ASPEED_PINCTRL_GROUP(TXD3), 2264 ASPEED_PINCTRL_GROUP(TXD4), 2265 ASPEED_PINCTRL_GROUP(UART6), 2266 ASPEED_PINCTRL_GROUP(USB11D1), 2267 ASPEED_PINCTRL_GROUP(USB11H2), 2268 ASPEED_PINCTRL_GROUP(USB2D1), 2269 ASPEED_PINCTRL_GROUP(USB2H1), 2270 ASPEED_PINCTRL_GROUP(USBCKI), 2271 ASPEED_PINCTRL_GROUP(VGABIOS_ROM), 2272 ASPEED_PINCTRL_GROUP(VGAHS), 2273 ASPEED_PINCTRL_GROUP(VGAVS), 2274 ASPEED_PINCTRL_GROUP(VPI18), 2275 ASPEED_PINCTRL_GROUP(VPI24), 2276 ASPEED_PINCTRL_GROUP(VPI30), 2277 ASPEED_PINCTRL_GROUP(VPO12), 2278 ASPEED_PINCTRL_GROUP(VPO24), 2279 ASPEED_PINCTRL_GROUP(WDTRST1), 2280 ASPEED_PINCTRL_GROUP(WDTRST2), 2281 }; 2282 2283 static const struct aspeed_pin_function aspeed_g4_functions[] = { 2284 ASPEED_PINCTRL_FUNC(ACPI), 2285 ASPEED_PINCTRL_FUNC(ADC0), 2286 ASPEED_PINCTRL_FUNC(ADC1), 2287 ASPEED_PINCTRL_FUNC(ADC10), 2288 ASPEED_PINCTRL_FUNC(ADC11), 2289 ASPEED_PINCTRL_FUNC(ADC12), 2290 ASPEED_PINCTRL_FUNC(ADC13), 2291 ASPEED_PINCTRL_FUNC(ADC14), 2292 ASPEED_PINCTRL_FUNC(ADC15), 2293 ASPEED_PINCTRL_FUNC(ADC2), 2294 ASPEED_PINCTRL_FUNC(ADC3), 2295 ASPEED_PINCTRL_FUNC(ADC4), 2296 ASPEED_PINCTRL_FUNC(ADC5), 2297 ASPEED_PINCTRL_FUNC(ADC6), 2298 ASPEED_PINCTRL_FUNC(ADC7), 2299 ASPEED_PINCTRL_FUNC(ADC8), 2300 ASPEED_PINCTRL_FUNC(ADC9), 2301 ASPEED_PINCTRL_FUNC(BMCINT), 2302 ASPEED_PINCTRL_FUNC(DDCCLK), 2303 ASPEED_PINCTRL_FUNC(DDCDAT), 2304 ASPEED_PINCTRL_FUNC(EXTRST), 2305 ASPEED_PINCTRL_FUNC(FLACK), 2306 ASPEED_PINCTRL_FUNC(FLBUSY), 2307 ASPEED_PINCTRL_FUNC(FLWP), 2308 ASPEED_PINCTRL_FUNC(GPID), 2309 ASPEED_PINCTRL_FUNC(GPID0), 2310 ASPEED_PINCTRL_FUNC(GPID2), 2311 ASPEED_PINCTRL_FUNC(GPID4), 2312 ASPEED_PINCTRL_FUNC(GPID6), 2313 ASPEED_PINCTRL_FUNC(GPIE0), 2314 ASPEED_PINCTRL_FUNC(GPIE2), 2315 ASPEED_PINCTRL_FUNC(GPIE4), 2316 ASPEED_PINCTRL_FUNC(GPIE6), 2317 ASPEED_PINCTRL_FUNC(I2C10), 2318 ASPEED_PINCTRL_FUNC(I2C11), 2319 ASPEED_PINCTRL_FUNC(I2C12), 2320 ASPEED_PINCTRL_FUNC(I2C13), 2321 ASPEED_PINCTRL_FUNC(I2C14), 2322 ASPEED_PINCTRL_FUNC(I2C3), 2323 ASPEED_PINCTRL_FUNC(I2C4), 2324 ASPEED_PINCTRL_FUNC(I2C5), 2325 ASPEED_PINCTRL_FUNC(I2C6), 2326 ASPEED_PINCTRL_FUNC(I2C7), 2327 ASPEED_PINCTRL_FUNC(I2C8), 2328 ASPEED_PINCTRL_FUNC(I2C9), 2329 ASPEED_PINCTRL_FUNC(LPCPD), 2330 ASPEED_PINCTRL_FUNC(LPCPME), 2331 ASPEED_PINCTRL_FUNC(LPCRST), 2332 ASPEED_PINCTRL_FUNC(LPCSMI), 2333 ASPEED_PINCTRL_FUNC(MAC1LINK), 2334 ASPEED_PINCTRL_FUNC(MAC2LINK), 2335 ASPEED_PINCTRL_FUNC(MDIO1), 2336 ASPEED_PINCTRL_FUNC(MDIO2), 2337 ASPEED_PINCTRL_FUNC(NCTS1), 2338 ASPEED_PINCTRL_FUNC(NCTS2), 2339 ASPEED_PINCTRL_FUNC(NCTS3), 2340 ASPEED_PINCTRL_FUNC(NCTS4), 2341 ASPEED_PINCTRL_FUNC(NDCD1), 2342 ASPEED_PINCTRL_FUNC(NDCD2), 2343 ASPEED_PINCTRL_FUNC(NDCD3), 2344 ASPEED_PINCTRL_FUNC(NDCD4), 2345 ASPEED_PINCTRL_FUNC(NDSR1), 2346 ASPEED_PINCTRL_FUNC(NDSR2), 2347 ASPEED_PINCTRL_FUNC(NDSR3), 2348 ASPEED_PINCTRL_FUNC(NDSR4), 2349 ASPEED_PINCTRL_FUNC(NDTR1), 2350 ASPEED_PINCTRL_FUNC(NDTR2), 2351 ASPEED_PINCTRL_FUNC(NDTR3), 2352 ASPEED_PINCTRL_FUNC(NDTR4), 2353 ASPEED_PINCTRL_FUNC(NDTS4), 2354 ASPEED_PINCTRL_FUNC(NRI1), 2355 ASPEED_PINCTRL_FUNC(NRI2), 2356 ASPEED_PINCTRL_FUNC(NRI3), 2357 ASPEED_PINCTRL_FUNC(NRI4), 2358 ASPEED_PINCTRL_FUNC(NRTS1), 2359 ASPEED_PINCTRL_FUNC(NRTS2), 2360 ASPEED_PINCTRL_FUNC(NRTS3), 2361 ASPEED_PINCTRL_FUNC(OSCCLK), 2362 ASPEED_PINCTRL_FUNC(PWM0), 2363 ASPEED_PINCTRL_FUNC(PWM1), 2364 ASPEED_PINCTRL_FUNC(PWM2), 2365 ASPEED_PINCTRL_FUNC(PWM3), 2366 ASPEED_PINCTRL_FUNC(PWM4), 2367 ASPEED_PINCTRL_FUNC(PWM5), 2368 ASPEED_PINCTRL_FUNC(PWM6), 2369 ASPEED_PINCTRL_FUNC(PWM7), 2370 ASPEED_PINCTRL_FUNC(RGMII1), 2371 ASPEED_PINCTRL_FUNC(RGMII2), 2372 ASPEED_PINCTRL_FUNC(RMII1), 2373 ASPEED_PINCTRL_FUNC(RMII2), 2374 ASPEED_PINCTRL_FUNC(ROM16), 2375 ASPEED_PINCTRL_FUNC(ROM8), 2376 ASPEED_PINCTRL_FUNC(ROMCS1), 2377 ASPEED_PINCTRL_FUNC(ROMCS2), 2378 ASPEED_PINCTRL_FUNC(ROMCS3), 2379 ASPEED_PINCTRL_FUNC(ROMCS4), 2380 ASPEED_PINCTRL_FUNC(RXD1), 2381 ASPEED_PINCTRL_FUNC(RXD2), 2382 ASPEED_PINCTRL_FUNC(RXD3), 2383 ASPEED_PINCTRL_FUNC(RXD4), 2384 ASPEED_PINCTRL_FUNC(SALT1), 2385 ASPEED_PINCTRL_FUNC(SALT2), 2386 ASPEED_PINCTRL_FUNC(SALT3), 2387 ASPEED_PINCTRL_FUNC(SALT4), 2388 ASPEED_PINCTRL_FUNC(SD1), 2389 ASPEED_PINCTRL_FUNC(SD2), 2390 ASPEED_PINCTRL_FUNC(SGPMCK), 2391 ASPEED_PINCTRL_FUNC(SGPMI), 2392 ASPEED_PINCTRL_FUNC(SGPMLD), 2393 ASPEED_PINCTRL_FUNC(SGPMO), 2394 ASPEED_PINCTRL_FUNC(SGPSCK), 2395 ASPEED_PINCTRL_FUNC(SGPSI0), 2396 ASPEED_PINCTRL_FUNC(SGPSI1), 2397 ASPEED_PINCTRL_FUNC(SGPSLD), 2398 ASPEED_PINCTRL_FUNC(SIOONCTRL), 2399 ASPEED_PINCTRL_FUNC(SIOPBI), 2400 ASPEED_PINCTRL_FUNC(SIOPBO), 2401 ASPEED_PINCTRL_FUNC(SIOPWREQ), 2402 ASPEED_PINCTRL_FUNC(SIOPWRGD), 2403 ASPEED_PINCTRL_FUNC(SIOS3), 2404 ASPEED_PINCTRL_FUNC(SIOS5), 2405 ASPEED_PINCTRL_FUNC(SIOSCI), 2406 ASPEED_PINCTRL_FUNC(SPI1), 2407 ASPEED_PINCTRL_FUNC(SPI1DEBUG), 2408 ASPEED_PINCTRL_FUNC(SPI1PASSTHRU), 2409 ASPEED_PINCTRL_FUNC(SPICS1), 2410 ASPEED_PINCTRL_FUNC(TIMER3), 2411 ASPEED_PINCTRL_FUNC(TIMER4), 2412 ASPEED_PINCTRL_FUNC(TIMER5), 2413 ASPEED_PINCTRL_FUNC(TIMER6), 2414 ASPEED_PINCTRL_FUNC(TIMER7), 2415 ASPEED_PINCTRL_FUNC(TIMER8), 2416 ASPEED_PINCTRL_FUNC(TXD1), 2417 ASPEED_PINCTRL_FUNC(TXD2), 2418 ASPEED_PINCTRL_FUNC(TXD3), 2419 ASPEED_PINCTRL_FUNC(TXD4), 2420 ASPEED_PINCTRL_FUNC(UART6), 2421 ASPEED_PINCTRL_FUNC(USB11D1), 2422 ASPEED_PINCTRL_FUNC(USB11H2), 2423 ASPEED_PINCTRL_FUNC(USB2D1), 2424 ASPEED_PINCTRL_FUNC(USB2H1), 2425 ASPEED_PINCTRL_FUNC(USBCKI), 2426 ASPEED_PINCTRL_FUNC(VGABIOS_ROM), 2427 ASPEED_PINCTRL_FUNC(VGAHS), 2428 ASPEED_PINCTRL_FUNC(VGAVS), 2429 ASPEED_PINCTRL_FUNC(VPI18), 2430 ASPEED_PINCTRL_FUNC(VPI24), 2431 ASPEED_PINCTRL_FUNC(VPI30), 2432 ASPEED_PINCTRL_FUNC(VPO12), 2433 ASPEED_PINCTRL_FUNC(VPO24), 2434 ASPEED_PINCTRL_FUNC(WDTRST1), 2435 ASPEED_PINCTRL_FUNC(WDTRST2), 2436 }; 2437 2438 static const struct aspeed_pin_config aspeed_g4_configs[] = { 2439 /* GPIO banks ranges [A, B], [D, J], [M, R] */ 2440 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16), 2441 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16), 2442 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J21, E18, SCU8C, 17), 2443 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J21, E18, SCU8C, 17), 2444 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, E15, SCU8C, 19), 2445 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, E15, SCU8C, 19), 2446 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20), 2447 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20), 2448 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D18, C17, SCU8C, 21), 2449 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D18, C17, SCU8C, 21), 2450 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A14, U18, SCU8C, 22), 2451 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A14, U18, SCU8C, 22), 2452 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23), 2453 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23), 2454 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C22, E20, SCU8C, 24), 2455 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C22, E20, SCU8C, 24), 2456 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25), 2457 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25), 2458 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U1, U5, SCU8C, 26), 2459 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U1, U5, SCU8C, 26), 2460 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V3, V5, SCU8C, 27), 2461 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V3, V5, SCU8C, 27), 2462 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, W4, AB2, SCU8C, 28), 2463 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, W4, AB2, SCU8C, 28), 2464 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V6, V7, SCU8C, 29), 2465 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V6, V7, SCU8C, 29), 2466 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y6, AB7, SCU8C, 30), 2467 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y6, AB7, SCU8C, 30), 2468 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, A5, SCU8C, 31), 2469 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, A5, SCU8C, 31), 2470 2471 /* GPIOs T[0-5] (RGMII1 Tx pins) */ 2472 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9), 2473 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12), 2474 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A12, A13, SCU90, 12), 2475 2476 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */ 2477 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, D9, D10, SCU90, 11), 2478 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D9, D10, SCU90, 14), 2479 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D9, D10, SCU90, 14), 2480 2481 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */ 2482 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13), 2483 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13), 2484 2485 /* GPIOs V[2-7] (RGMII2 Rx pins) */ 2486 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15), 2487 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15), 2488 2489 /* ADC pull-downs (SCUA8[19:4]) */ 2490 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L5, L5, SCUA8, 4), 2491 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L5, L5, SCUA8, 4), 2492 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L4, L4, SCUA8, 5), 2493 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L4, L4, SCUA8, 5), 2494 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, L3, SCUA8, 6), 2495 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, L3, SCUA8, 6), 2496 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7), 2497 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7), 2498 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8), 2499 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8), 2500 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M5, M5, SCUA8, 9), 2501 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M5, M5, SCUA8, 9), 2502 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M4, M4, SCUA8, 10), 2503 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M4, M4, SCUA8, 10), 2504 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M3, M3, SCUA8, 11), 2505 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M3, M3, SCUA8, 11), 2506 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12), 2507 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12), 2508 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13), 2509 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13), 2510 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N5, N5, SCUA8, 14), 2511 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N5, N5, SCUA8, 14), 2512 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15), 2513 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15), 2514 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N3, N3, SCUA8, 16), 2515 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N3, N3, SCUA8, 16), 2516 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17), 2517 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17), 2518 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18), 2519 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18), 2520 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, P5, P5, SCUA8, 19), 2521 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, P5, P5, SCUA8, 19), 2522 2523 /* 2524 * Debounce settings for GPIOs D and E passthrough mode are in 2525 * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for 2526 * banks D and E is handled by the GPIO driver - GPIO passthrough is 2527 * treated like any other non-GPIO mux function. There is a catch 2528 * however, in that the debounce period is configured in the GPIO 2529 * controller. Due to this tangle between GPIO and pinctrl we don't yet 2530 * fully support pass-through debounce. 2531 */ 2532 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A18, D16, SCUA8, 20), 2533 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B17, A17, SCUA8, 21), 2534 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C16, B16, SCUA8, 22), 2535 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A16, E15, SCUA8, 23), 2536 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24), 2537 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25), 2538 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E14, D14, SCUA8, 26), 2539 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C14, B14, SCUA8, 27), 2540 }; 2541 2542 static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, 2543 const struct aspeed_sig_expr *expr, 2544 bool enable) 2545 { 2546 int ret; 2547 int i; 2548 2549 for (i = 0; i < expr->ndescs; i++) { 2550 const struct aspeed_sig_desc *desc = &expr->descs[i]; 2551 u32 pattern = enable ? desc->enable : desc->disable; 2552 u32 val = (pattern << __ffs(desc->mask)); 2553 2554 if (!ctx->maps[desc->ip]) 2555 return -ENODEV; 2556 2557 /* 2558 * Strap registers are configured in hardware or by early-boot 2559 * firmware. Treat them as read-only despite that we can write 2560 * them. This may mean that certain functions cannot be 2561 * deconfigured and is the reason we re-evaluate after writing 2562 * all descriptor bits. 2563 * 2564 * We make two exceptions to the read-only rule: 2565 * 2566 * - The passthrough mode of GPIO ports D and E are commonly 2567 * used with front-panel buttons to allow normal operation 2568 * of the host if the BMC is powered off or fails to boot. 2569 * Once the BMC has booted, the loopback mode must be 2570 * disabled for the BMC to control host power-on and reset. 2571 * 2572 * - The operating mode of the SPI1 interface is simply 2573 * strapped incorrectly on some systems and requires a 2574 * software fixup, which we allow to be done via pinctrl. 2575 */ 2576 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 && 2577 !(desc->mask & (BIT(22) | BIT(21) | BIT(13) | BIT(12)))) 2578 continue; 2579 2580 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) 2581 continue; 2582 2583 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, 2584 desc->mask, val); 2585 2586 if (ret) 2587 return ret; 2588 } 2589 2590 ret = aspeed_sig_expr_eval(ctx, expr, enable); 2591 if (ret < 0) 2592 return ret; 2593 2594 if (!ret) 2595 return -EPERM; 2596 2597 return 0; 2598 } 2599 2600 static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = { 2601 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, 2602 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, 2603 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, 2604 { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)}, 2605 { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)}, 2606 }; 2607 2608 static const struct aspeed_pinmux_ops aspeed_g4_ops = { 2609 .set = aspeed_g4_sig_expr_set, 2610 }; 2611 2612 static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { 2613 .pins = aspeed_g4_pins, 2614 .npins = ARRAY_SIZE(aspeed_g4_pins), 2615 .pinmux = { 2616 .ops = &aspeed_g4_ops, 2617 .groups = aspeed_g4_groups, 2618 .ngroups = ARRAY_SIZE(aspeed_g4_groups), 2619 .functions = aspeed_g4_functions, 2620 .nfunctions = ARRAY_SIZE(aspeed_g4_functions), 2621 }, 2622 .configs = aspeed_g4_configs, 2623 .nconfigs = ARRAY_SIZE(aspeed_g4_configs), 2624 .confmaps = aspeed_g4_pin_config_map, 2625 .nconfmaps = ARRAY_SIZE(aspeed_g4_pin_config_map), 2626 }; 2627 2628 static const struct pinmux_ops aspeed_g4_pinmux_ops = { 2629 .get_functions_count = aspeed_pinmux_get_fn_count, 2630 .get_function_name = aspeed_pinmux_get_fn_name, 2631 .get_function_groups = aspeed_pinmux_get_fn_groups, 2632 .set_mux = aspeed_pinmux_set_mux, 2633 .gpio_request_enable = aspeed_gpio_request_enable, 2634 .strict = true, 2635 }; 2636 2637 static const struct pinctrl_ops aspeed_g4_pinctrl_ops = { 2638 .get_groups_count = aspeed_pinctrl_get_groups_count, 2639 .get_group_name = aspeed_pinctrl_get_group_name, 2640 .get_group_pins = aspeed_pinctrl_get_group_pins, 2641 .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, 2642 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 2643 .dt_free_map = pinctrl_utils_free_map, 2644 }; 2645 2646 static const struct pinconf_ops aspeed_g4_conf_ops = { 2647 .is_generic = true, 2648 .pin_config_get = aspeed_pin_config_get, 2649 .pin_config_set = aspeed_pin_config_set, 2650 .pin_config_group_get = aspeed_pin_config_group_get, 2651 .pin_config_group_set = aspeed_pin_config_group_set, 2652 }; 2653 2654 static const struct pinctrl_desc aspeed_g4_pinctrl_desc = { 2655 .name = "aspeed-g4-pinctrl", 2656 .pins = aspeed_g4_pins, 2657 .npins = ARRAY_SIZE(aspeed_g4_pins), 2658 .pctlops = &aspeed_g4_pinctrl_ops, 2659 .pmxops = &aspeed_g4_pinmux_ops, 2660 .confops = &aspeed_g4_conf_ops, 2661 }; 2662 2663 static int aspeed_g4_pinctrl_probe(struct platform_device *pdev) 2664 { 2665 int i; 2666 2667 for (i = 0; i < ARRAY_SIZE(aspeed_g4_pins); i++) 2668 aspeed_g4_pins[i].number = i; 2669 2670 return aspeed_pinctrl_probe(pdev, &aspeed_g4_pinctrl_desc, 2671 &aspeed_g4_pinctrl_data); 2672 } 2673 2674 static const struct of_device_id aspeed_g4_pinctrl_of_match[] = { 2675 { .compatible = "aspeed,ast2400-pinctrl", }, 2676 /* 2677 * The aspeed,g4-pinctrl compatible has been removed the from the 2678 * bindings, but keep the match in case of old devicetrees. 2679 */ 2680 { .compatible = "aspeed,g4-pinctrl", }, 2681 { }, 2682 }; 2683 2684 static struct platform_driver aspeed_g4_pinctrl_driver = { 2685 .probe = aspeed_g4_pinctrl_probe, 2686 .driver = { 2687 .name = "aspeed-g4-pinctrl", 2688 .of_match_table = aspeed_g4_pinctrl_of_match, 2689 }, 2690 }; 2691 2692 static int aspeed_g4_pinctrl_init(void) 2693 { 2694 return platform_driver_register(&aspeed_g4_pinctrl_driver); 2695 } 2696 2697 arch_initcall(aspeed_g4_pinctrl_init); 2698