14d3d0e42SAndrew Jefferyconfig PINCTRL_ASPEED 24d3d0e42SAndrew Jeffery bool 34d3d0e42SAndrew Jeffery depends on (ARCH_ASPEED || COMPILE_TEST) && OF 44d3d0e42SAndrew Jeffery depends on MFD_SYSCON 54d3d0e42SAndrew Jeffery select PINMUX 64d3d0e42SAndrew Jeffery select PINCONF 74d3d0e42SAndrew Jeffery select GENERIC_PINCONF 84d3d0e42SAndrew Jeffery select REGMAP_MMIO 9*524594d4SAndrew Jeffery 10*524594d4SAndrew Jefferyconfig PINCTRL_ASPEED_G4 11*524594d4SAndrew Jeffery bool "Aspeed G4 SoC pin control" 12*524594d4SAndrew Jeffery depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF 13*524594d4SAndrew Jeffery select PINCTRL_ASPEED 14*524594d4SAndrew Jeffery help 15*524594d4SAndrew Jeffery Say Y here to enable pin controller support for Aspeed's 4th 16*524594d4SAndrew Jeffery generation SoCs. GPIO is provided by a separate GPIO driver. 17