1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OWL S900 Pinctrl driver 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Copyright (c) 2018 Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pinctrl/pinctrl.h> 16 #include "pinctrl-owl.h" 17 18 /* Pinctrl registers offset */ 19 #define MFCTL0 (0x0040) 20 #define MFCTL1 (0x0044) 21 #define MFCTL2 (0x0048) 22 #define MFCTL3 (0x004C) 23 #define PAD_PULLCTL0 (0x0060) 24 #define PAD_PULLCTL1 (0x0064) 25 #define PAD_PULLCTL2 (0x0068) 26 #define PAD_ST0 (0x006C) 27 #define PAD_ST1 (0x0070) 28 #define PAD_CTL (0x0074) 29 #define PAD_DRV0 (0x0080) 30 #define PAD_DRV1 (0x0084) 31 #define PAD_DRV2 (0x0088) 32 #define PAD_SR0 (0x0270) 33 #define PAD_SR1 (0x0274) 34 #define PAD_SR2 (0x0278) 35 36 #define _GPIOA(offset) (offset) 37 #define _GPIOB(offset) (32 + (offset)) 38 #define _GPIOC(offset) (64 + (offset)) 39 #define _GPIOD(offset) (76 + (offset)) 40 #define _GPIOE(offset) (106 + (offset)) 41 #define _GPIOF(offset) (138 + (offset)) 42 43 #define NUM_GPIOS (_GPIOF(7) + 1) 44 #define _PIN(offset) (NUM_GPIOS + (offset)) 45 46 #define ETH_TXD0 _GPIOA(0) 47 #define ETH_TXD1 _GPIOA(1) 48 #define ETH_TXEN _GPIOA(2) 49 #define ETH_RXER _GPIOA(3) 50 #define ETH_CRS_DV _GPIOA(4) 51 #define ETH_RXD1 _GPIOA(5) 52 #define ETH_RXD0 _GPIOA(6) 53 #define ETH_REF_CLK _GPIOA(7) 54 #define ETH_MDC _GPIOA(8) 55 #define ETH_MDIO _GPIOA(9) 56 #define SIRQ0 _GPIOA(10) 57 #define SIRQ1 _GPIOA(11) 58 #define SIRQ2 _GPIOA(12) 59 #define I2S_D0 _GPIOA(13) 60 #define I2S_BCLK0 _GPIOA(14) 61 #define I2S_LRCLK0 _GPIOA(15) 62 #define I2S_MCLK0 _GPIOA(16) 63 #define I2S_D1 _GPIOA(17) 64 #define I2S_BCLK1 _GPIOA(18) 65 #define I2S_LRCLK1 _GPIOA(19) 66 #define I2S_MCLK1 _GPIOA(20) 67 #define ERAM_A5 _GPIOA(21) 68 #define ERAM_A6 _GPIOA(22) 69 #define ERAM_A7 _GPIOA(23) 70 #define ERAM_A8 _GPIOA(24) 71 #define ERAM_A9 _GPIOA(25) 72 #define ERAM_A10 _GPIOA(26) 73 #define ERAM_A11 _GPIOA(27) 74 #define SD0_D0 _GPIOA(28) 75 #define SD0_D1 _GPIOA(29) 76 #define SD0_D2 _GPIOA(30) 77 #define SD0_D3 _GPIOA(31) 78 79 #define SD1_D0 _GPIOB(0) 80 #define SD1_D1 _GPIOB(1) 81 #define SD1_D2 _GPIOB(2) 82 #define SD1_D3 _GPIOB(3) 83 #define SD0_CMD _GPIOB(4) 84 #define SD0_CLK _GPIOB(5) 85 #define SD1_CMD _GPIOB(6) 86 #define SD1_CLK _GPIOB(7) 87 #define SPI0_SCLK _GPIOB(8) 88 #define SPI0_SS _GPIOB(9) 89 #define SPI0_MISO _GPIOB(10) 90 #define SPI0_MOSI _GPIOB(11) 91 #define UART0_RX _GPIOB(12) 92 #define UART0_TX _GPIOB(13) 93 #define UART2_RX _GPIOB(14) 94 #define UART2_TX _GPIOB(15) 95 #define UART2_RTSB _GPIOB(16) 96 #define UART2_CTSB _GPIOB(17) 97 #define UART4_RX _GPIOB(18) 98 #define UART4_TX _GPIOB(19) 99 #define I2C0_SCLK _GPIOB(20) 100 #define I2C0_SDATA _GPIOB(21) 101 #define I2C1_SCLK _GPIOB(22) 102 #define I2C1_SDATA _GPIOB(23) 103 #define I2C2_SCLK _GPIOB(24) 104 #define I2C2_SDATA _GPIOB(25) 105 #define CSI0_DN0 _GPIOB(26) 106 #define CSI0_DP0 _GPIOB(27) 107 #define CSI0_DN1 _GPIOB(28) 108 #define CSI0_DP1 _GPIOB(29) 109 #define CSI0_CN _GPIOB(30) 110 #define CSI0_CP _GPIOB(31) 111 112 #define CSI0_DN2 _GPIOC(0) 113 #define CSI0_DP2 _GPIOC(1) 114 #define CSI0_DN3 _GPIOC(2) 115 #define CSI0_DP3 _GPIOC(3) 116 #define SENSOR0_PCLK _GPIOC(4) 117 #define CSI1_DN0 _GPIOC(5) 118 #define CSI1_DP0 _GPIOC(6) 119 #define CSI1_DN1 _GPIOC(7) 120 #define CSI1_DP1 _GPIOC(8) 121 #define CSI1_CN _GPIOC(9) 122 #define CSI1_CP _GPIOC(10) 123 #define SENSOR0_CKOUT _GPIOC(11) 124 125 #define LVDS_OEP _GPIOD(0) 126 #define LVDS_OEN _GPIOD(1) 127 #define LVDS_ODP _GPIOD(2) 128 #define LVDS_ODN _GPIOD(3) 129 #define LVDS_OCP _GPIOD(4) 130 #define LVDS_OCN _GPIOD(5) 131 #define LVDS_OBP _GPIOD(6) 132 #define LVDS_OBN _GPIOD(7) 133 #define LVDS_OAP _GPIOD(8) 134 #define LVDS_OAN _GPIOD(9) 135 #define LVDS_EEP _GPIOD(10) 136 #define LVDS_EEN _GPIOD(11) 137 #define LVDS_EDP _GPIOD(12) 138 #define LVDS_EDN _GPIOD(13) 139 #define LVDS_ECP _GPIOD(14) 140 #define LVDS_ECN _GPIOD(15) 141 #define LVDS_EBP _GPIOD(16) 142 #define LVDS_EBN _GPIOD(17) 143 #define LVDS_EAP _GPIOD(18) 144 #define LVDS_EAN _GPIOD(19) 145 #define DSI_DP3 _GPIOD(20) 146 #define DSI_DN3 _GPIOD(21) 147 #define DSI_DP1 _GPIOD(22) 148 #define DSI_DN1 _GPIOD(23) 149 #define DSI_CP _GPIOD(24) 150 #define DSI_CN _GPIOD(25) 151 #define DSI_DP0 _GPIOD(26) 152 #define DSI_DN0 _GPIOD(27) 153 #define DSI_DP2 _GPIOD(28) 154 #define DSI_DN2 _GPIOD(29) 155 156 #define NAND0_D0 _GPIOE(0) 157 #define NAND0_D1 _GPIOE(1) 158 #define NAND0_D2 _GPIOE(2) 159 #define NAND0_D3 _GPIOE(3) 160 #define NAND0_D4 _GPIOE(4) 161 #define NAND0_D5 _GPIOE(5) 162 #define NAND0_D6 _GPIOE(6) 163 #define NAND0_D7 _GPIOE(7) 164 #define NAND0_DQS _GPIOE(8) 165 #define NAND0_DQSN _GPIOE(9) 166 #define NAND0_ALE _GPIOE(10) 167 #define NAND0_CLE _GPIOE(11) 168 #define NAND0_CEB0 _GPIOE(12) 169 #define NAND0_CEB1 _GPIOE(13) 170 #define NAND0_CEB2 _GPIOE(14) 171 #define NAND0_CEB3 _GPIOE(15) 172 #define NAND1_D0 _GPIOE(16) 173 #define NAND1_D1 _GPIOE(17) 174 #define NAND1_D2 _GPIOE(18) 175 #define NAND1_D3 _GPIOE(19) 176 #define NAND1_D4 _GPIOE(20) 177 #define NAND1_D5 _GPIOE(21) 178 #define NAND1_D6 _GPIOE(22) 179 #define NAND1_D7 _GPIOE(23) 180 #define NAND1_DQS _GPIOE(24) 181 #define NAND1_DQSN _GPIOE(25) 182 #define NAND1_ALE _GPIOE(26) 183 #define NAND1_CLE _GPIOE(27) 184 #define NAND1_CEB0 _GPIOE(28) 185 #define NAND1_CEB1 _GPIOE(29) 186 #define NAND1_CEB2 _GPIOE(30) 187 #define NAND1_CEB3 _GPIOE(31) 188 189 #define PCM1_IN _GPIOF(0) 190 #define PCM1_CLK _GPIOF(1) 191 #define PCM1_SYNC _GPIOF(2) 192 #define PCM1_OUT _GPIOF(3) 193 #define UART3_RX _GPIOF(4) 194 #define UART3_TX _GPIOF(5) 195 #define UART3_RTSB _GPIOF(6) 196 #define UART3_CTSB _GPIOF(7) 197 198 /* System */ 199 #define SGPIO0 _PIN(0) 200 #define SGPIO1 _PIN(1) 201 #define SGPIO2 _PIN(2) 202 #define SGPIO3 _PIN(3) 203 204 #define NUM_PADS (_PIN(3) + 1) 205 206 /* Pad names as specified in datasheet */ 207 static const struct pinctrl_pin_desc s900_pads[] = { 208 PINCTRL_PIN(ETH_TXD0, "eth_txd0"), 209 PINCTRL_PIN(ETH_TXD1, "eth_txd1"), 210 PINCTRL_PIN(ETH_TXEN, "eth_txen"), 211 PINCTRL_PIN(ETH_RXER, "eth_rxer"), 212 PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"), 213 PINCTRL_PIN(ETH_RXD1, "eth_rxd1"), 214 PINCTRL_PIN(ETH_RXD0, "eth_rxd0"), 215 PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"), 216 PINCTRL_PIN(ETH_MDC, "eth_mdc"), 217 PINCTRL_PIN(ETH_MDIO, "eth_mdio"), 218 PINCTRL_PIN(SIRQ0, "sirq0"), 219 PINCTRL_PIN(SIRQ1, "sirq1"), 220 PINCTRL_PIN(SIRQ2, "sirq2"), 221 PINCTRL_PIN(I2S_D0, "i2s_d0"), 222 PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"), 223 PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"), 224 PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"), 225 PINCTRL_PIN(I2S_D1, "i2s_d1"), 226 PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"), 227 PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"), 228 PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"), 229 PINCTRL_PIN(PCM1_IN, "pcm1_in"), 230 PINCTRL_PIN(PCM1_CLK, "pcm1_clk"), 231 PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"), 232 PINCTRL_PIN(PCM1_OUT, "pcm1_out"), 233 PINCTRL_PIN(ERAM_A5, "eram_a5"), 234 PINCTRL_PIN(ERAM_A6, "eram_a6"), 235 PINCTRL_PIN(ERAM_A7, "eram_a7"), 236 PINCTRL_PIN(ERAM_A8, "eram_a8"), 237 PINCTRL_PIN(ERAM_A9, "eram_a9"), 238 PINCTRL_PIN(ERAM_A10, "eram_a10"), 239 PINCTRL_PIN(ERAM_A11, "eram_a11"), 240 PINCTRL_PIN(LVDS_OEP, "lvds_oep"), 241 PINCTRL_PIN(LVDS_OEN, "lvds_oen"), 242 PINCTRL_PIN(LVDS_ODP, "lvds_odp"), 243 PINCTRL_PIN(LVDS_ODN, "lvds_odn"), 244 PINCTRL_PIN(LVDS_OCP, "lvds_ocp"), 245 PINCTRL_PIN(LVDS_OCN, "lvds_ocn"), 246 PINCTRL_PIN(LVDS_OBP, "lvds_obp"), 247 PINCTRL_PIN(LVDS_OBN, "lvds_obn"), 248 PINCTRL_PIN(LVDS_OAP, "lvds_oap"), 249 PINCTRL_PIN(LVDS_OAN, "lvds_oan"), 250 PINCTRL_PIN(LVDS_EEP, "lvds_eep"), 251 PINCTRL_PIN(LVDS_EEN, "lvds_een"), 252 PINCTRL_PIN(LVDS_EDP, "lvds_edp"), 253 PINCTRL_PIN(LVDS_EDN, "lvds_edn"), 254 PINCTRL_PIN(LVDS_ECP, "lvds_ecp"), 255 PINCTRL_PIN(LVDS_ECN, "lvds_ecn"), 256 PINCTRL_PIN(LVDS_EBP, "lvds_ebp"), 257 PINCTRL_PIN(LVDS_EBN, "lvds_ebn"), 258 PINCTRL_PIN(LVDS_EAP, "lvds_eap"), 259 PINCTRL_PIN(LVDS_EAN, "lvds_ean"), 260 PINCTRL_PIN(SD0_D0, "sd0_d0"), 261 PINCTRL_PIN(SD0_D1, "sd0_d1"), 262 PINCTRL_PIN(SD0_D2, "sd0_d2"), 263 PINCTRL_PIN(SD0_D3, "sd0_d3"), 264 PINCTRL_PIN(SD1_D0, "sd1_d0"), 265 PINCTRL_PIN(SD1_D1, "sd1_d1"), 266 PINCTRL_PIN(SD1_D2, "sd1_d2"), 267 PINCTRL_PIN(SD1_D3, "sd1_d3"), 268 PINCTRL_PIN(SD0_CMD, "sd0_cmd"), 269 PINCTRL_PIN(SD0_CLK, "sd0_clk"), 270 PINCTRL_PIN(SD1_CMD, "sd1_cmd"), 271 PINCTRL_PIN(SD1_CLK, "sd1_clk"), 272 PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"), 273 PINCTRL_PIN(SPI0_SS, "spi0_ss"), 274 PINCTRL_PIN(SPI0_MISO, "spi0_miso"), 275 PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"), 276 PINCTRL_PIN(UART0_RX, "uart0_rx"), 277 PINCTRL_PIN(UART0_TX, "uart0_tx"), 278 PINCTRL_PIN(UART2_RX, "uart2_rx"), 279 PINCTRL_PIN(UART2_TX, "uart2_tx"), 280 PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"), 281 PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"), 282 PINCTRL_PIN(UART3_RX, "uart3_rx"), 283 PINCTRL_PIN(UART3_TX, "uart3_tx"), 284 PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"), 285 PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"), 286 PINCTRL_PIN(UART4_RX, "uart4_rx"), 287 PINCTRL_PIN(UART4_TX, "uart4_tx"), 288 PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"), 289 PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"), 290 PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"), 291 PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"), 292 PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"), 293 PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"), 294 PINCTRL_PIN(CSI0_DN0, "csi0_dn0"), 295 PINCTRL_PIN(CSI0_DP0, "csi0_dp0"), 296 PINCTRL_PIN(CSI0_DN1, "csi0_dn1"), 297 PINCTRL_PIN(CSI0_DP1, "csi0_dp1"), 298 PINCTRL_PIN(CSI0_CN, "csi0_cn"), 299 PINCTRL_PIN(CSI0_CP, "csi0_cp"), 300 PINCTRL_PIN(CSI0_DN2, "csi0_dn2"), 301 PINCTRL_PIN(CSI0_DP2, "csi0_dp2"), 302 PINCTRL_PIN(CSI0_DN3, "csi0_dn3"), 303 PINCTRL_PIN(CSI0_DP3, "csi0_dp3"), 304 PINCTRL_PIN(DSI_DP3, "dsi_dp3"), 305 PINCTRL_PIN(DSI_DN3, "dsi_dn3"), 306 PINCTRL_PIN(DSI_DP1, "dsi_dp1"), 307 PINCTRL_PIN(DSI_DN1, "dsi_dn1"), 308 PINCTRL_PIN(DSI_CP, "dsi_cp"), 309 PINCTRL_PIN(DSI_CN, "dsi_cn"), 310 PINCTRL_PIN(DSI_DP0, "dsi_dp0"), 311 PINCTRL_PIN(DSI_DN0, "dsi_dn0"), 312 PINCTRL_PIN(DSI_DP2, "dsi_dp2"), 313 PINCTRL_PIN(DSI_DN2, "dsi_dn2"), 314 PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"), 315 PINCTRL_PIN(CSI1_DN0, "csi1_dn0"), 316 PINCTRL_PIN(CSI1_DP0, "csi1_dp0"), 317 PINCTRL_PIN(CSI1_DN1, "csi1_dn1"), 318 PINCTRL_PIN(CSI1_DP1, "csi1_dp1"), 319 PINCTRL_PIN(CSI1_CN, "csi1_cn"), 320 PINCTRL_PIN(CSI1_CP, "csi1_cp"), 321 PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"), 322 PINCTRL_PIN(NAND0_D0, "nand0_d0"), 323 PINCTRL_PIN(NAND0_D1, "nand0_d1"), 324 PINCTRL_PIN(NAND0_D2, "nand0_d2"), 325 PINCTRL_PIN(NAND0_D3, "nand0_d3"), 326 PINCTRL_PIN(NAND0_D4, "nand0_d4"), 327 PINCTRL_PIN(NAND0_D5, "nand0_d5"), 328 PINCTRL_PIN(NAND0_D6, "nand0_d6"), 329 PINCTRL_PIN(NAND0_D7, "nand0_d7"), 330 PINCTRL_PIN(NAND0_DQS, "nand0_dqs"), 331 PINCTRL_PIN(NAND0_DQSN, "nand0_dqsn"), 332 PINCTRL_PIN(NAND0_ALE, "nand0_ale"), 333 PINCTRL_PIN(NAND0_CLE, "nand0_cle"), 334 PINCTRL_PIN(NAND0_CEB0, "nand0_ceb0"), 335 PINCTRL_PIN(NAND0_CEB1, "nand0_ceb1"), 336 PINCTRL_PIN(NAND0_CEB2, "nand0_ceb2"), 337 PINCTRL_PIN(NAND0_CEB3, "nand0_ceb3"), 338 PINCTRL_PIN(NAND1_D0, "nand1_d0"), 339 PINCTRL_PIN(NAND1_D1, "nand1_d1"), 340 PINCTRL_PIN(NAND1_D2, "nand1_d2"), 341 PINCTRL_PIN(NAND1_D3, "nand1_d3"), 342 PINCTRL_PIN(NAND1_D4, "nand1_d4"), 343 PINCTRL_PIN(NAND1_D5, "nand1_d5"), 344 PINCTRL_PIN(NAND1_D6, "nand1_d6"), 345 PINCTRL_PIN(NAND1_D7, "nand1_d7"), 346 PINCTRL_PIN(NAND1_DQS, "nand1_dqs"), 347 PINCTRL_PIN(NAND1_DQSN, "nand1_dqsn"), 348 PINCTRL_PIN(NAND1_ALE, "nand1_ale"), 349 PINCTRL_PIN(NAND1_CLE, "nand1_cle"), 350 PINCTRL_PIN(NAND1_CEB0, "nand1_ceb0"), 351 PINCTRL_PIN(NAND1_CEB1, "nand1_ceb1"), 352 PINCTRL_PIN(NAND1_CEB2, "nand1_ceb2"), 353 PINCTRL_PIN(NAND1_CEB3, "nand1_ceb3"), 354 PINCTRL_PIN(SGPIO0, "sgpio0"), 355 PINCTRL_PIN(SGPIO1, "sgpio1"), 356 PINCTRL_PIN(SGPIO2, "sgpio2"), 357 PINCTRL_PIN(SGPIO3, "sgpio3") 358 }; 359 360 enum s900_pinmux_functions { 361 S900_MUX_ERAM, 362 S900_MUX_ETH_RMII, 363 S900_MUX_ETH_SMII, 364 S900_MUX_SPI0, 365 S900_MUX_SPI1, 366 S900_MUX_SPI2, 367 S900_MUX_SPI3, 368 S900_MUX_SENS0, 369 S900_MUX_UART0, 370 S900_MUX_UART1, 371 S900_MUX_UART2, 372 S900_MUX_UART3, 373 S900_MUX_UART4, 374 S900_MUX_UART5, 375 S900_MUX_UART6, 376 S900_MUX_I2S0, 377 S900_MUX_I2S1, 378 S900_MUX_PCM0, 379 S900_MUX_PCM1, 380 S900_MUX_JTAG, 381 S900_MUX_PWM0, 382 S900_MUX_PWM1, 383 S900_MUX_PWM2, 384 S900_MUX_PWM3, 385 S900_MUX_PWM4, 386 S900_MUX_PWM5, 387 S900_MUX_SD0, 388 S900_MUX_SD1, 389 S900_MUX_SD2, 390 S900_MUX_SD3, 391 S900_MUX_I2C0, 392 S900_MUX_I2C1, 393 S900_MUX_I2C2, 394 S900_MUX_I2C3, 395 S900_MUX_I2C4, 396 S900_MUX_I2C5, 397 S900_MUX_LVDS, 398 S900_MUX_USB20, 399 S900_MUX_USB30, 400 S900_MUX_GPU, 401 S900_MUX_MIPI_CSI0, 402 S900_MUX_MIPI_CSI1, 403 S900_MUX_MIPI_DSI, 404 S900_MUX_NAND0, 405 S900_MUX_NAND1, 406 S900_MUX_SPDIF, 407 S900_MUX_SIRQ0, 408 S900_MUX_SIRQ1, 409 S900_MUX_SIRQ2, 410 S900_MUX_AUX_START, 411 S900_MUX_MAX, 412 S900_MUX_RESERVED 413 }; 414 415 /* mfp0_22 */ 416 static unsigned int lvds_oxx_uart4_mfp_pads[] = { LVDS_OAP, LVDS_OAN }; 417 static unsigned int lvds_oxx_uart4_mfp_funcs[] = { S900_MUX_ERAM, 418 S900_MUX_UART4 }; 419 /* mfp0_21_20 */ 420 static unsigned int rmii_mdc_mfp_pads[] = { ETH_MDC }; 421 static unsigned int rmii_mdc_mfp_funcs[] = { S900_MUX_ETH_RMII, 422 S900_MUX_PWM2, 423 S900_MUX_UART2, 424 S900_MUX_RESERVED }; 425 static unsigned int rmii_mdio_mfp_pads[] = { ETH_MDIO }; 426 static unsigned int rmii_mdio_mfp_funcs[] = { S900_MUX_ETH_RMII, 427 S900_MUX_PWM3, 428 S900_MUX_UART2, 429 S900_MUX_RESERVED }; 430 /* mfp0_19 */ 431 static unsigned int sirq0_mfp_pads[] = { SIRQ0 }; 432 static unsigned int sirq0_mfp_funcs[] = { S900_MUX_SIRQ0, 433 S900_MUX_PWM0 }; 434 static unsigned int sirq1_mfp_pads[] = { SIRQ1 }; 435 static unsigned int sirq1_mfp_funcs[] = { S900_MUX_SIRQ1, 436 S900_MUX_PWM1 }; 437 /* mfp0_18_16 */ 438 static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 }; 439 static unsigned int rmii_txd0_mfp_funcs[] = { S900_MUX_ETH_RMII, 440 S900_MUX_ETH_SMII, 441 S900_MUX_SPI2, 442 S900_MUX_UART6, 443 S900_MUX_SENS0, 444 S900_MUX_PWM0 }; 445 static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 }; 446 static unsigned int rmii_txd1_mfp_funcs[] = { S900_MUX_ETH_RMII, 447 S900_MUX_ETH_SMII, 448 S900_MUX_SPI2, 449 S900_MUX_UART6, 450 S900_MUX_SENS0, 451 S900_MUX_PWM1 }; 452 /* mfp0_15_13 */ 453 static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN }; 454 static unsigned int rmii_txen_mfp_funcs[] = { S900_MUX_ETH_RMII, 455 S900_MUX_UART2, 456 S900_MUX_SPI3, 457 S900_MUX_RESERVED, 458 S900_MUX_RESERVED, 459 S900_MUX_PWM2, 460 S900_MUX_SENS0 }; 461 462 static unsigned int rmii_rxer_mfp_pads[] = { ETH_RXER }; 463 static unsigned int rmii_rxer_mfp_funcs[] = { S900_MUX_ETH_RMII, 464 S900_MUX_UART2, 465 S900_MUX_SPI3, 466 S900_MUX_RESERVED, 467 S900_MUX_RESERVED, 468 S900_MUX_PWM3, 469 S900_MUX_SENS0 }; 470 /* mfp0_12_11 */ 471 static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV }; 472 static unsigned int rmii_crs_dv_mfp_funcs[] = { S900_MUX_ETH_RMII, 473 S900_MUX_ETH_SMII, 474 S900_MUX_SPI2, 475 S900_MUX_UART4 }; 476 /* mfp0_10_8 */ 477 static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 }; 478 static unsigned int rmii_rxd1_mfp_funcs[] = { S900_MUX_ETH_RMII, 479 S900_MUX_UART2, 480 S900_MUX_SPI3, 481 S900_MUX_RESERVED, 482 S900_MUX_UART5, 483 S900_MUX_PWM0, 484 S900_MUX_SENS0 }; 485 static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 }; 486 static unsigned int rmii_rxd0_mfp_funcs[] = { S900_MUX_ETH_RMII, 487 S900_MUX_UART2, 488 S900_MUX_SPI3, 489 S900_MUX_RESERVED, 490 S900_MUX_UART5, 491 S900_MUX_PWM1, 492 S900_MUX_SENS0 }; 493 /* mfp0_7_6 */ 494 static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK }; 495 static unsigned int rmii_ref_clk_mfp_funcs[] = { S900_MUX_ETH_RMII, 496 S900_MUX_UART4, 497 S900_MUX_SPI2, 498 S900_MUX_RESERVED }; 499 /* mfp0_5 */ 500 static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 }; 501 static unsigned int i2s_d0_mfp_funcs[] = { S900_MUX_I2S0, 502 S900_MUX_PCM0 }; 503 static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 }; 504 static unsigned int i2s_d1_mfp_funcs[] = { S900_MUX_I2S1, 505 S900_MUX_PCM0 }; 506 507 /* mfp0_4_3 */ 508 static unsigned int i2s_lr_m_clk0_mfp_pads[] = { I2S_LRCLK0, 509 I2S_MCLK0 }; 510 static unsigned int i2s_lr_m_clk0_mfp_funcs[] = { S900_MUX_I2S0, 511 S900_MUX_PCM0, 512 S900_MUX_PCM1, 513 S900_MUX_RESERVED }; 514 /* mfp0_2 */ 515 static unsigned int i2s_bclk0_mfp_pads[] = { I2S_BCLK0 }; 516 static unsigned int i2s_bclk0_mfp_funcs[] = { S900_MUX_I2S0, 517 S900_MUX_PCM0 }; 518 static unsigned int i2s_bclk1_mclk1_mfp_pads[] = { I2S_BCLK1, 519 I2S_LRCLK1, 520 I2S_MCLK1 }; 521 static unsigned int i2s_bclk1_mclk1_mfp_funcs[] = { S900_MUX_I2S1, 522 S900_MUX_PCM0 }; 523 /* mfp0_1_0 */ 524 static unsigned int pcm1_in_out_mfp_pads[] = { PCM1_IN, 525 PCM1_OUT }; 526 static unsigned int pcm1_in_out_mfp_funcs[] = { S900_MUX_PCM1, 527 S900_MUX_SPI1, 528 S900_MUX_I2C3, 529 S900_MUX_UART4 }; 530 static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK }; 531 static unsigned int pcm1_clk_mfp_funcs[] = { S900_MUX_PCM1, 532 S900_MUX_SPI1, 533 S900_MUX_PWM4, 534 S900_MUX_UART4 }; 535 static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC }; 536 static unsigned int pcm1_sync_mfp_funcs[] = { S900_MUX_PCM1, 537 S900_MUX_SPI1, 538 S900_MUX_PWM5, 539 S900_MUX_UART4 }; 540 /* mfp1_31_29 */ 541 static unsigned int eram_a5_mfp_pads[] = { ERAM_A5 }; 542 static unsigned int eram_a5_mfp_funcs[] = { S900_MUX_UART4, 543 S900_MUX_JTAG, 544 S900_MUX_ERAM, 545 S900_MUX_PWM0, 546 S900_MUX_RESERVED, 547 S900_MUX_SENS0 }; 548 static unsigned int eram_a6_mfp_pads[] = { ERAM_A6 }; 549 static unsigned int eram_a6_mfp_funcs[] = { S900_MUX_UART4, 550 S900_MUX_JTAG, 551 S900_MUX_ERAM, 552 S900_MUX_PWM1, 553 S900_MUX_RESERVED, 554 S900_MUX_SENS0, 555 }; 556 static unsigned int eram_a7_mfp_pads[] = { ERAM_A7 }; 557 static unsigned int eram_a7_mfp_funcs[] = { S900_MUX_RESERVED, 558 S900_MUX_JTAG, 559 S900_MUX_ERAM, 560 S900_MUX_RESERVED, 561 S900_MUX_RESERVED, 562 S900_MUX_SENS0 }; 563 /* mfp1_28_26 */ 564 static unsigned int eram_a8_mfp_pads[] = { ERAM_A8 }; 565 static unsigned int eram_a8_mfp_funcs[] = { S900_MUX_RESERVED, 566 S900_MUX_JTAG, 567 S900_MUX_ERAM, 568 S900_MUX_PWM1, 569 S900_MUX_RESERVED, 570 S900_MUX_SENS0 }; 571 static unsigned int eram_a9_mfp_pads[] = { ERAM_A9 }; 572 static unsigned int eram_a9_mfp_funcs[] = { S900_MUX_USB20, 573 S900_MUX_UART5, 574 S900_MUX_ERAM, 575 S900_MUX_PWM2, 576 S900_MUX_RESERVED, 577 S900_MUX_SENS0 }; 578 static unsigned int eram_a10_mfp_pads[] = { ERAM_A10 }; 579 static unsigned int eram_a10_mfp_funcs[] = { S900_MUX_USB30, 580 S900_MUX_JTAG, 581 S900_MUX_ERAM, 582 S900_MUX_PWM3, 583 S900_MUX_RESERVED, 584 S900_MUX_SENS0, 585 S900_MUX_RESERVED, 586 S900_MUX_RESERVED }; 587 /* mfp1_25_23 */ 588 static unsigned int eram_a11_mfp_pads[] = { ERAM_A11 }; 589 static unsigned int eram_a11_mfp_funcs[] = { S900_MUX_RESERVED, 590 S900_MUX_RESERVED, 591 S900_MUX_ERAM, 592 S900_MUX_PWM2, 593 S900_MUX_UART5, 594 S900_MUX_RESERVED, 595 S900_MUX_SENS0, 596 S900_MUX_RESERVED }; 597 /* mfp1_22 */ 598 static unsigned int lvds_oep_odn_mfp_pads[] = { LVDS_OEP, 599 LVDS_OEN, 600 LVDS_ODP, 601 LVDS_ODN }; 602 static unsigned int lvds_oep_odn_mfp_funcs[] = { S900_MUX_LVDS, 603 S900_MUX_UART2 }; 604 static unsigned int lvds_ocp_obn_mfp_pads[] = { LVDS_OCP, 605 LVDS_OCN, 606 LVDS_OBP, 607 LVDS_OBN }; 608 static unsigned int lvds_ocp_obn_mfp_funcs[] = { S900_MUX_LVDS, 609 S900_MUX_PCM1 }; 610 static unsigned int lvds_oap_oan_mfp_pads[] = { LVDS_OAP, 611 LVDS_OAN }; 612 static unsigned int lvds_oap_oan_mfp_funcs[] = { S900_MUX_LVDS, 613 S900_MUX_ERAM }; 614 /* mfp1_21 */ 615 static unsigned int lvds_e_mfp_pads[] = { LVDS_EEP, 616 LVDS_EEN, 617 LVDS_EDP, 618 LVDS_EDN, 619 LVDS_ECP, 620 LVDS_ECN, 621 LVDS_EBP, 622 LVDS_EBN, 623 LVDS_EAP, 624 LVDS_EAN }; 625 static unsigned int lvds_e_mfp_funcs[] = { S900_MUX_LVDS, 626 S900_MUX_ERAM }; 627 /* mfp1_5_4 */ 628 static unsigned int spi0_sclk_mosi_mfp_pads[] = { SPI0_SCLK, 629 SPI0_MOSI }; 630 static unsigned int spi0_sclk_mosi_mfp_funcs[] = { S900_MUX_SPI0, 631 S900_MUX_ERAM, 632 S900_MUX_I2C3, 633 S900_MUX_PCM0 }; 634 /* mfp1_3_1 */ 635 static unsigned int spi0_ss_mfp_pads[] = { SPI0_SS }; 636 static unsigned int spi0_ss_mfp_funcs[] = { S900_MUX_SPI0, 637 S900_MUX_ERAM, 638 S900_MUX_I2S1, 639 S900_MUX_PCM1, 640 S900_MUX_PCM0, 641 S900_MUX_PWM4 }; 642 static unsigned int spi0_miso_mfp_pads[] = { SPI0_MISO }; 643 static unsigned int spi0_miso_mfp_funcs[] = { S900_MUX_SPI0, 644 S900_MUX_ERAM, 645 S900_MUX_I2S1, 646 S900_MUX_PCM1, 647 S900_MUX_PCM0, 648 S900_MUX_PWM5 }; 649 /* mfp2_23 */ 650 static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB }; 651 static unsigned int uart2_rtsb_mfp_funcs[] = { S900_MUX_UART2, 652 S900_MUX_UART0 }; 653 /* mfp2_22 */ 654 static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB }; 655 static unsigned int uart2_ctsb_mfp_funcs[] = { S900_MUX_UART2, 656 S900_MUX_UART0 }; 657 /* mfp2_21 */ 658 static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB }; 659 static unsigned int uart3_rtsb_mfp_funcs[] = { S900_MUX_UART3, 660 S900_MUX_UART5 }; 661 /* mfp2_20 */ 662 static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB }; 663 static unsigned int uart3_ctsb_mfp_funcs[] = { S900_MUX_UART3, 664 S900_MUX_UART5 }; 665 /* mfp2_19_17 */ 666 static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 }; 667 static unsigned int sd0_d0_mfp_funcs[] = { S900_MUX_SD0, 668 S900_MUX_ERAM, 669 S900_MUX_RESERVED, 670 S900_MUX_JTAG, 671 S900_MUX_UART2, 672 S900_MUX_UART5, 673 S900_MUX_GPU }; 674 /* mfp2_16_14 */ 675 static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 }; 676 static unsigned int sd0_d1_mfp_funcs[] = { S900_MUX_SD0, 677 S900_MUX_ERAM, 678 S900_MUX_GPU, 679 S900_MUX_RESERVED, 680 S900_MUX_UART2, 681 S900_MUX_UART5 }; 682 /* mfp_13_11 */ 683 static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2, 684 SD0_D3 }; 685 static unsigned int sd0_d2_d3_mfp_funcs[] = { S900_MUX_SD0, 686 S900_MUX_ERAM, 687 S900_MUX_RESERVED, 688 S900_MUX_JTAG, 689 S900_MUX_UART2, 690 S900_MUX_UART1, 691 S900_MUX_GPU }; 692 /* mfp2_10_9 */ 693 static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1, 694 SD1_D2, SD1_D3 }; 695 static unsigned int sd1_d0_d3_mfp_funcs[] = { S900_MUX_SD1, 696 S900_MUX_ERAM }; 697 /* mfp2_8_7 */ 698 static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD }; 699 static unsigned int sd0_cmd_mfp_funcs[] = { S900_MUX_SD0, 700 S900_MUX_ERAM, 701 S900_MUX_GPU, 702 S900_MUX_JTAG }; 703 /* mfp2_6_5 */ 704 static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK }; 705 static unsigned int sd0_clk_mfp_funcs[] = { S900_MUX_SD0, 706 S900_MUX_ERAM, 707 S900_MUX_JTAG, 708 S900_MUX_GPU }; 709 /* mfp2_4_3 */ 710 static unsigned int sd1_cmd_clk_mfp_pads[] = { SD1_CMD, SD1_CLK }; 711 static unsigned int sd1_cmd_clk_mfp_funcs[] = { S900_MUX_SD1, 712 S900_MUX_ERAM }; 713 /* mfp2_2_0 */ 714 static unsigned int uart0_rx_mfp_pads[] = { UART0_RX }; 715 static unsigned int uart0_rx_mfp_funcs[] = { S900_MUX_UART0, 716 S900_MUX_UART2, 717 S900_MUX_SPI1, 718 S900_MUX_I2C5, 719 S900_MUX_PCM1, 720 S900_MUX_I2S1 }; 721 /* mfp3_27 */ 722 static unsigned int nand0_d0_ceb3_mfp_pads[] = { NAND0_D0, NAND0_D1, 723 NAND0_D2, NAND0_D3, 724 NAND0_D4, NAND0_D5, 725 NAND0_D6, NAND0_D7, 726 NAND0_DQSN, NAND0_CEB3 }; 727 static unsigned int nand0_d0_ceb3_mfp_funcs[] = { S900_MUX_NAND0, 728 S900_MUX_SD2 }; 729 /* mfp3_21_19 */ 730 static unsigned int uart0_tx_mfp_pads[] = { UART0_TX }; 731 static unsigned int uart0_tx_mfp_funcs[] = { S900_MUX_UART0, 732 S900_MUX_UART2, 733 S900_MUX_SPI1, 734 S900_MUX_I2C5, 735 S900_MUX_SPDIF, 736 S900_MUX_PCM1, 737 S900_MUX_I2S1 }; 738 /* mfp3_18_16 */ 739 static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK, I2C0_SDATA }; 740 static unsigned int i2c0_mfp_funcs[] = { S900_MUX_I2C0, 741 S900_MUX_UART2, 742 S900_MUX_I2C1, 743 S900_MUX_UART1, 744 S900_MUX_SPI1 }; 745 /* mfp3_15 */ 746 static unsigned int csi0_cn_cp_mfp_pads[] = { CSI0_CN, CSI0_CP }; 747 static unsigned int csi0_cn_cp_mfp_funcs[] = { S900_MUX_SENS0, 748 S900_MUX_SENS0 }; 749 /* mfp3_14 */ 750 static unsigned int csi0_dn0_dp3_mfp_pads[] = { CSI0_DN0, CSI0_DP0, 751 CSI0_DN1, CSI0_DP1, 752 CSI0_CN, CSI0_CP, 753 CSI0_DP2, CSI0_DN2, 754 CSI0_DN3, CSI0_DP3 }; 755 static unsigned int csi0_dn0_dp3_mfp_funcs[] = { S900_MUX_MIPI_CSI0, 756 S900_MUX_SENS0 }; 757 /* mfp3_13 */ 758 static unsigned int csi1_dn0_cp_mfp_pads[] = { CSI1_DN0, CSI1_DP0, 759 CSI1_DN1, CSI1_DP1, 760 CSI1_CN, CSI1_CP }; 761 static unsigned int csi1_dn0_cp_mfp_funcs[] = { S900_MUX_MIPI_CSI1, 762 S900_MUX_SENS0 }; 763 /* mfp3_12_dsi */ 764 static unsigned int dsi_dp3_dn1_mfp_pads[] = { DSI_DP3, DSI_DN2, 765 DSI_DP1, DSI_DN1 }; 766 static unsigned int dsi_dp3_dn1_mfp_funcs[] = { S900_MUX_MIPI_DSI, 767 S900_MUX_UART2 }; 768 static unsigned int dsi_cp_dn0_mfp_pads[] = { DSI_CP, DSI_CN, 769 DSI_DP0, DSI_DN0 }; 770 static unsigned int dsi_cp_dn0_mfp_funcs[] = { S900_MUX_MIPI_DSI, 771 S900_MUX_PCM1 }; 772 static unsigned int dsi_dp2_dn2_mfp_pads[] = { DSI_DP2, DSI_DN2 }; 773 static unsigned int dsi_dp2_dn2_mfp_funcs[] = { S900_MUX_MIPI_DSI, 774 S900_MUX_UART4 }; 775 /* mfp3_11 */ 776 static unsigned int nand1_d0_ceb1_mfp_pads[] = { NAND1_D0, NAND1_D1, 777 NAND1_D2, NAND1_D3, 778 NAND1_D4, NAND1_D5, 779 NAND1_D6, NAND1_D7, 780 NAND1_DQSN, NAND1_CEB1 }; 781 static unsigned int nand1_d0_ceb1_mfp_funcs[] = { S900_MUX_NAND1, 782 S900_MUX_SD3 }; 783 /* mfp3_10 */ 784 static unsigned int nand1_ceb3_mfp_pads[] = { NAND1_CEB3 }; 785 static unsigned int nand1_ceb3_mfp_funcs[] = { S900_MUX_NAND1, 786 S900_MUX_PWM0 }; 787 static unsigned int nand1_ceb0_mfp_pads[] = { NAND1_CEB0 }; 788 static unsigned int nand1_ceb0_mfp_funcs[] = { S900_MUX_NAND1, 789 S900_MUX_PWM1 }; 790 /* mfp3_9 */ 791 static unsigned int csi1_dn0_dp0_mfp_pads[] = { CSI1_DN0, CSI1_DP0 }; 792 static unsigned int csi1_dn0_dp0_mfp_funcs[] = { S900_MUX_SENS0, 793 S900_MUX_SENS0 }; 794 /* mfp3_8 */ 795 static unsigned int uart4_rx_tx_mfp_pads[] = { UART4_RX, UART4_TX }; 796 static unsigned int uart4_rx_tx_mfp_funcs[] = { S900_MUX_UART4, 797 S900_MUX_I2C4 }; 798 /* PADDRV group data */ 799 /* drv0 */ 800 static unsigned int sgpio3_drv_pads[] = { SGPIO3 }; 801 static unsigned int sgpio2_drv_pads[] = { SGPIO2 }; 802 static unsigned int sgpio1_drv_pads[] = { SGPIO1 }; 803 static unsigned int sgpio0_drv_pads[] = { SGPIO0 }; 804 static unsigned int rmii_tx_d0_d1_drv_pads[] = { ETH_TXD0, ETH_TXD1 }; 805 static unsigned int rmii_txen_rxer_drv_pads[] = { ETH_TXEN, ETH_RXER }; 806 static unsigned int rmii_crs_dv_drv_pads[] = { ETH_CRS_DV }; 807 static unsigned int rmii_rx_d1_d0_drv_pads[] = { ETH_RXD1, ETH_RXD0 }; 808 static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK }; 809 static unsigned int rmii_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO }; 810 static unsigned int sirq_0_1_drv_pads[] = { SIRQ0, SIRQ1 }; 811 static unsigned int sirq2_drv_pads[] = { SIRQ2 }; 812 static unsigned int i2s_d0_d1_drv_pads[] = { I2S_D0, I2S_D1 }; 813 static unsigned int i2s_lr_m_clk0_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0 }; 814 static unsigned int i2s_blk1_mclk1_drv_pads[] = { I2S_BCLK0, I2S_BCLK1, 815 I2S_LRCLK1, I2S_MCLK1 }; 816 static unsigned int pcm1_in_out_drv_pads[] = { PCM1_IN, PCM1_CLK, 817 PCM1_SYNC, PCM1_OUT }; 818 /* drv1 */ 819 static unsigned int lvds_oap_oan_drv_pads[] = { LVDS_OAP, LVDS_OAN }; 820 static unsigned int lvds_oep_odn_drv_pads[] = { LVDS_OEP, LVDS_OEN, 821 LVDS_ODP, LVDS_ODN }; 822 static unsigned int lvds_ocp_obn_drv_pads[] = { LVDS_OCP, LVDS_OCN, 823 LVDS_OBP, LVDS_OBN }; 824 static unsigned int lvds_e_drv_pads[] = { LVDS_EEP, LVDS_EEN, 825 LVDS_EDP, LVDS_EDN, 826 LVDS_ECP, LVDS_ECN, 827 LVDS_EBP, LVDS_EBN }; 828 static unsigned int sd0_d3_d0_drv_pads[] = { SD0_D3, SD0_D2, 829 SD0_D1, SD0_D0 }; 830 static unsigned int sd1_d3_d0_drv_pads[] = { SD1_D3, SD1_D2, 831 SD1_D1, SD1_D0 }; 832 static unsigned int sd0_sd1_cmd_clk_drv_pads[] = { SD0_CLK, SD0_CMD, 833 SD1_CLK, SD1_CMD }; 834 static unsigned int spi0_sclk_mosi_drv_pads[] = { SPI0_SCLK, SPI0_MOSI }; 835 static unsigned int spi0_ss_miso_drv_pads[] = { SPI0_SS, SPI0_MISO }; 836 static unsigned int uart0_rx_tx_drv_pads[] = { UART0_RX, UART0_TX }; 837 static unsigned int uart4_rx_tx_drv_pads[] = { UART4_RX, UART4_TX }; 838 static unsigned int uart2_drv_pads[] = { UART2_RX, UART2_TX, 839 UART2_RTSB, UART2_CTSB }; 840 static unsigned int uart3_drv_pads[] = { UART3_RX, UART3_TX, 841 UART3_RTSB, UART3_CTSB }; 842 /* drv2 */ 843 static unsigned int i2c0_drv_pads[] = { I2C0_SCLK, I2C0_SDATA }; 844 static unsigned int i2c1_drv_pads[] = { I2C1_SCLK, I2C1_SDATA }; 845 static unsigned int i2c2_drv_pads[] = { I2C2_SCLK, I2C2_SDATA }; 846 static unsigned int sensor0_drv_pads[] = { SENSOR0_PCLK, 847 SENSOR0_CKOUT }; 848 /* SR group data */ 849 /* sr0 */ 850 static unsigned int sgpio3_sr_pads[] = { SGPIO3 }; 851 static unsigned int sgpio2_sr_pads[] = { SGPIO2 }; 852 static unsigned int sgpio1_sr_pads[] = { SGPIO1 }; 853 static unsigned int sgpio0_sr_pads[] = { SGPIO0 }; 854 static unsigned int rmii_tx_d0_d1_sr_pads[] = { ETH_TXD0, ETH_TXD1 }; 855 static unsigned int rmii_txen_rxer_sr_pads[] = { ETH_TXEN, ETH_RXER }; 856 static unsigned int rmii_crs_dv_sr_pads[] = { ETH_CRS_DV }; 857 static unsigned int rmii_rx_d1_d0_sr_pads[] = { ETH_RXD1, ETH_RXD0 }; 858 static unsigned int rmii_ref_clk_sr_pads[] = { ETH_REF_CLK }; 859 static unsigned int rmii_mdc_mdio_sr_pads[] = { ETH_MDC, ETH_MDIO }; 860 static unsigned int sirq_0_1_sr_pads[] = { SIRQ0, SIRQ1 }; 861 static unsigned int sirq2_sr_pads[] = { SIRQ2 }; 862 static unsigned int i2s_do_d1_sr_pads[] = { I2S_D0, I2S_D1 }; 863 static unsigned int i2s_lr_m_clk0_sr_pads[] = { I2S_LRCLK0, I2S_MCLK0 }; 864 static unsigned int i2s_bclk0_mclk1_sr_pads[] = { I2S_BCLK0, I2S_BCLK1, 865 I2S_LRCLK1, I2S_MCLK1 }; 866 static unsigned int pcm1_in_out_sr_pads[] = { PCM1_IN, PCM1_CLK, 867 PCM1_SYNC, PCM1_OUT }; 868 /* sr1 */ 869 static unsigned int sd1_d3_d0_sr_pads[] = { SD1_D3, SD1_D2, 870 SD1_D1, SD1_D0 }; 871 static unsigned int sd0_sd1_clk_cmd_sr_pads[] = { SD0_CLK, SD0_CMD, 872 SD1_CLK, SD1_CMD }; 873 static unsigned int spi0_sclk_mosi_sr_pads[] = { SPI0_SCLK, SPI0_MOSI }; 874 static unsigned int spi0_ss_miso_sr_pads[] = { SPI0_SS, SPI0_MISO }; 875 static unsigned int uart0_rx_tx_sr_pads[] = { UART0_RX, UART0_TX }; 876 static unsigned int uart4_rx_tx_sr_pads[] = { UART4_RX, UART4_TX }; 877 static unsigned int uart2_sr_pads[] = { UART2_RX, UART2_TX, 878 UART2_RTSB, UART2_CTSB }; 879 static unsigned int uart3_sr_pads[] = { UART3_RX, UART3_TX, 880 UART3_RTSB, UART3_CTSB }; 881 /* sr2 */ 882 static unsigned int i2c0_sr_pads[] = { I2C0_SCLK, I2C0_SDATA }; 883 static unsigned int i2c1_sr_pads[] = { I2C1_SCLK, I2C1_SDATA }; 884 static unsigned int i2c2_sr_pads[] = { I2C2_SCLK, I2C2_SDATA }; 885 static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK, 886 SENSOR0_CKOUT }; 887 888 889 /* Pinctrl groups */ 890 static const struct owl_pingroup s900_groups[] = { 891 MUX_PG(lvds_oxx_uart4_mfp, 0, 22, 1), 892 MUX_PG(rmii_mdc_mfp, 0, 20, 2), 893 MUX_PG(rmii_mdio_mfp, 0, 20, 2), 894 MUX_PG(sirq0_mfp, 0, 19, 1), 895 MUX_PG(sirq1_mfp, 0, 19, 1), 896 MUX_PG(rmii_txd0_mfp, 0, 16, 3), 897 MUX_PG(rmii_txd1_mfp, 0, 16, 3), 898 MUX_PG(rmii_txen_mfp, 0, 13, 3), 899 MUX_PG(rmii_rxer_mfp, 0, 13, 3), 900 MUX_PG(rmii_crs_dv_mfp, 0, 11, 2), 901 MUX_PG(rmii_rxd1_mfp, 0, 8, 3), 902 MUX_PG(rmii_rxd0_mfp, 0, 8, 3), 903 MUX_PG(rmii_ref_clk_mfp, 0, 6, 2), 904 MUX_PG(i2s_d0_mfp, 0, 5, 1), 905 MUX_PG(i2s_d1_mfp, 0, 5, 1), 906 MUX_PG(i2s_lr_m_clk0_mfp, 0, 3, 2), 907 MUX_PG(i2s_bclk0_mfp, 0, 2, 1), 908 MUX_PG(i2s_bclk1_mclk1_mfp, 0, 2, 1), 909 MUX_PG(pcm1_in_out_mfp, 0, 0, 2), 910 MUX_PG(pcm1_clk_mfp, 0, 0, 2), 911 MUX_PG(pcm1_sync_mfp, 0, 0, 2), 912 MUX_PG(eram_a5_mfp, 1, 29, 3), 913 MUX_PG(eram_a6_mfp, 1, 29, 3), 914 MUX_PG(eram_a7_mfp, 1, 29, 3), 915 MUX_PG(eram_a8_mfp, 1, 26, 3), 916 MUX_PG(eram_a9_mfp, 1, 26, 3), 917 MUX_PG(eram_a10_mfp, 1, 26, 3), 918 MUX_PG(eram_a11_mfp, 1, 23, 3), 919 MUX_PG(lvds_oep_odn_mfp, 1, 22, 1), 920 MUX_PG(lvds_ocp_obn_mfp, 1, 22, 1), 921 MUX_PG(lvds_oap_oan_mfp, 1, 22, 1), 922 MUX_PG(lvds_e_mfp, 1, 21, 1), 923 MUX_PG(spi0_sclk_mosi_mfp, 1, 4, 2), 924 MUX_PG(spi0_ss_mfp, 1, 1, 3), 925 MUX_PG(spi0_miso_mfp, 1, 1, 3), 926 MUX_PG(uart2_rtsb_mfp, 2, 23, 1), 927 MUX_PG(uart2_ctsb_mfp, 2, 22, 1), 928 MUX_PG(uart3_rtsb_mfp, 2, 21, 1), 929 MUX_PG(uart3_ctsb_mfp, 2, 20, 1), 930 MUX_PG(sd0_d0_mfp, 2, 17, 3), 931 MUX_PG(sd0_d1_mfp, 2, 14, 3), 932 MUX_PG(sd0_d2_d3_mfp, 2, 11, 3), 933 MUX_PG(sd1_d0_d3_mfp, 2, 9, 2), 934 MUX_PG(sd0_cmd_mfp, 2, 7, 2), 935 MUX_PG(sd0_clk_mfp, 2, 5, 2), 936 MUX_PG(sd1_cmd_clk_mfp, 2, 3, 2), 937 MUX_PG(uart0_rx_mfp, 2, 0, 3), 938 MUX_PG(nand0_d0_ceb3_mfp, 3, 27, 1), 939 MUX_PG(uart0_tx_mfp, 3, 19, 3), 940 MUX_PG(i2c0_mfp, 3, 16, 3), 941 MUX_PG(csi0_cn_cp_mfp, 3, 15, 1), 942 MUX_PG(csi0_dn0_dp3_mfp, 3, 14, 1), 943 MUX_PG(csi1_dn0_cp_mfp, 3, 13, 1), 944 MUX_PG(dsi_dp3_dn1_mfp, 3, 12, 1), 945 MUX_PG(dsi_cp_dn0_mfp, 3, 12, 1), 946 MUX_PG(dsi_dp2_dn2_mfp, 3, 12, 1), 947 MUX_PG(nand1_d0_ceb1_mfp, 3, 11, 1), 948 MUX_PG(nand1_ceb3_mfp, 3, 10, 1), 949 MUX_PG(nand1_ceb0_mfp, 3, 10, 1), 950 MUX_PG(csi1_dn0_dp0_mfp, 3, 9, 1), 951 MUX_PG(uart4_rx_tx_mfp, 3, 8, 1), 952 953 DRV_PG(sgpio3_drv, 0, 30, 2), 954 DRV_PG(sgpio2_drv, 0, 28, 2), 955 DRV_PG(sgpio1_drv, 0, 26, 2), 956 DRV_PG(sgpio0_drv, 0, 24, 2), 957 DRV_PG(rmii_tx_d0_d1_drv, 0, 22, 2), 958 DRV_PG(rmii_txen_rxer_drv, 0, 20, 2), 959 DRV_PG(rmii_crs_dv_drv, 0, 18, 2), 960 DRV_PG(rmii_rx_d1_d0_drv, 0, 16, 2), 961 DRV_PG(rmii_ref_clk_drv, 0, 14, 2), 962 DRV_PG(rmii_mdc_mdio_drv, 0, 12, 2), 963 DRV_PG(sirq_0_1_drv, 0, 10, 2), 964 DRV_PG(sirq2_drv, 0, 8, 2), 965 DRV_PG(i2s_d0_d1_drv, 0, 6, 2), 966 DRV_PG(i2s_lr_m_clk0_drv, 0, 4, 2), 967 DRV_PG(i2s_blk1_mclk1_drv, 0, 2, 2), 968 DRV_PG(pcm1_in_out_drv, 0, 0, 2), 969 DRV_PG(lvds_oap_oan_drv, 1, 28, 2), 970 DRV_PG(lvds_oep_odn_drv, 1, 26, 2), 971 DRV_PG(lvds_ocp_obn_drv, 1, 24, 2), 972 DRV_PG(lvds_e_drv, 1, 22, 2), 973 DRV_PG(sd0_d3_d0_drv, 1, 20, 2), 974 DRV_PG(sd1_d3_d0_drv, 1, 18, 2), 975 DRV_PG(sd0_sd1_cmd_clk_drv, 1, 16, 2), 976 DRV_PG(spi0_sclk_mosi_drv, 1, 14, 2), 977 DRV_PG(spi0_ss_miso_drv, 1, 12, 2), 978 DRV_PG(uart0_rx_tx_drv, 1, 10, 2), 979 DRV_PG(uart4_rx_tx_drv, 1, 8, 2), 980 DRV_PG(uart2_drv, 1, 6, 2), 981 DRV_PG(uart3_drv, 1, 4, 2), 982 DRV_PG(i2c0_drv, 2, 30, 2), 983 DRV_PG(i2c1_drv, 2, 28, 2), 984 DRV_PG(i2c2_drv, 2, 26, 2), 985 DRV_PG(sensor0_drv, 2, 20, 2), 986 987 SR_PG(sgpio3_sr, 0, 15, 1), 988 SR_PG(sgpio2_sr, 0, 14, 1), 989 SR_PG(sgpio1_sr, 0, 13, 1), 990 SR_PG(sgpio0_sr, 0, 12, 1), 991 SR_PG(rmii_tx_d0_d1_sr, 0, 11, 1), 992 SR_PG(rmii_txen_rxer_sr, 0, 10, 1), 993 SR_PG(rmii_crs_dv_sr, 0, 9, 1), 994 SR_PG(rmii_rx_d1_d0_sr, 0, 8, 1), 995 SR_PG(rmii_ref_clk_sr, 0, 7, 1), 996 SR_PG(rmii_mdc_mdio_sr, 0, 6, 1), 997 SR_PG(sirq_0_1_sr, 0, 5, 1), 998 SR_PG(sirq2_sr, 0, 4, 1), 999 SR_PG(i2s_do_d1_sr, 0, 3, 1), 1000 SR_PG(i2s_lr_m_clk0_sr, 0, 2, 1), 1001 SR_PG(i2s_bclk0_mclk1_sr, 0, 1, 1), 1002 SR_PG(pcm1_in_out_sr, 0, 0, 1), 1003 SR_PG(sd1_d3_d0_sr, 1, 25, 1), 1004 SR_PG(sd0_sd1_clk_cmd_sr, 1, 24, 1), 1005 SR_PG(spi0_sclk_mosi_sr, 1, 23, 1), 1006 SR_PG(spi0_ss_miso_sr, 1, 22, 1), 1007 SR_PG(uart0_rx_tx_sr, 1, 21, 1), 1008 SR_PG(uart4_rx_tx_sr, 1, 20, 1), 1009 SR_PG(uart2_sr, 1, 19, 1), 1010 SR_PG(uart3_sr, 1, 18, 1), 1011 SR_PG(i2c0_sr, 2, 31, 1), 1012 SR_PG(i2c1_sr, 2, 30, 1), 1013 SR_PG(i2c2_sr, 2, 29, 1), 1014 SR_PG(sensor0_sr, 2, 25, 1) 1015 }; 1016 1017 static const char * const eram_groups[] = { 1018 "lvds_oxx_uart4_mfp", 1019 "eram_a5_mfp", 1020 "eram_a6_mfp", 1021 "eram_a7_mfp", 1022 "eram_a8_mfp", 1023 "eram_a9_mfp", 1024 "eram_a10_mfp", 1025 "eram_a11_mfp", 1026 "lvds_oap_oan_mfp", 1027 "lvds_e_mfp", 1028 "spi0_sclk_mosi_mfp", 1029 "spi0_ss_mfp", 1030 "spi0_miso_mfp", 1031 "sd0_d0_mfp", 1032 "sd0_d1_mfp", 1033 "sd0_d2_d3_mfp", 1034 "sd1_d0_d3_mfp", 1035 "sd0_cmd_mfp", 1036 "sd0_clk_mfp", 1037 "sd1_cmd_clk_mfp", 1038 }; 1039 1040 static const char * const eth_rmii_groups[] = { 1041 "rmii_mdc_mfp", 1042 "rmii_mdio_mfp", 1043 "rmii_txd0_mfp", 1044 "rmii_txd1_mfp", 1045 "rmii_txen_mfp", 1046 "rmii_rxer_mfp", 1047 "rmii_crs_dv_mfp", 1048 "rmii_rxd1_mfp", 1049 "rmii_rxd0_mfp", 1050 "rmii_ref_clk_mfp", 1051 "eth_smi_dummy", 1052 }; 1053 1054 static const char * const eth_smii_groups[] = { 1055 "rmii_txd0_mfp", 1056 "rmii_txd1_mfp", 1057 "rmii_crs_dv_mfp", 1058 "eth_smi_dummy", 1059 }; 1060 1061 static const char * const spi0_groups[] = { 1062 "spi0_sclk_mosi_mfp", 1063 "spi0_ss_mfp", 1064 "spi0_miso_mfp", 1065 "spi0_sclk_mosi_mfp", 1066 "spi0_ss_mfp", 1067 "spi0_miso_mfp", 1068 }; 1069 1070 static const char * const spi1_groups[] = { 1071 "pcm1_in_out_mfp", 1072 "pcm1_clk_mfp", 1073 "pcm1_sync_mfp", 1074 "uart0_rx_mfp", 1075 "uart0_tx_mfp", 1076 "i2c0_mfp", 1077 }; 1078 1079 static const char * const spi2_groups[] = { 1080 "rmii_txd0_mfp", 1081 "rmii_txd1_mfp", 1082 "rmii_crs_dv_mfp", 1083 "rmii_ref_clk_mfp", 1084 }; 1085 1086 static const char * const spi3_groups[] = { 1087 "rmii_txen_mfp", 1088 "rmii_rxer_mfp", 1089 }; 1090 1091 static const char * const sens0_groups[] = { 1092 "rmii_txd0_mfp", 1093 "rmii_txd1_mfp", 1094 "rmii_txen_mfp", 1095 "rmii_rxer_mfp", 1096 "rmii_rxd1_mfp", 1097 "rmii_rxd0_mfp", 1098 "eram_a5_mfp", 1099 "eram_a6_mfp", 1100 "eram_a7_mfp", 1101 "eram_a8_mfp", 1102 "eram_a9_mfp", 1103 "csi0_cn_cp_mfp", 1104 "csi0_dn0_dp3_mfp", 1105 "csi1_dn0_cp_mfp", 1106 "csi1_dn0_dp0_mfp", 1107 }; 1108 1109 static const char * const uart0_groups[] = { 1110 "uart2_rtsb_mfp", 1111 "uart2_ctsb_mfp", 1112 "uart0_rx_mfp", 1113 "uart0_tx_mfp", 1114 }; 1115 1116 static const char * const uart1_groups[] = { 1117 "sd0_d2_d3_mfp", 1118 "i2c0_mfp", 1119 }; 1120 1121 static const char * const uart2_groups[] = { 1122 "rmii_mdc_mfp", 1123 "rmii_mdio_mfp", 1124 "rmii_txen_mfp", 1125 "rmii_rxer_mfp", 1126 "rmii_rxd1_mfp", 1127 "rmii_rxd0_mfp", 1128 "lvds_oep_odn_mfp", 1129 "uart2_rtsb_mfp", 1130 "uart2_ctsb_mfp", 1131 "sd0_d0_mfp", 1132 "sd0_d1_mfp", 1133 "sd0_d2_d3_mfp", 1134 "uart0_rx_mfp", 1135 "uart0_tx_mfp_pads", 1136 "i2c0_mfp_pads", 1137 "dsi_dp3_dn1_mfp", 1138 "uart2_dummy" 1139 }; 1140 1141 static const char * const uart3_groups[] = { 1142 "uart3_rtsb_mfp", 1143 "uart3_ctsb_mfp", 1144 "uart3_dummy" 1145 }; 1146 1147 static const char * const uart4_groups[] = { 1148 "lvds_oxx_uart4_mfp", 1149 "rmii_crs_dv_mfp", 1150 "rmii_ref_clk_mfp", 1151 "pcm1_in_out_mfp", 1152 "pcm1_clk_mfp", 1153 "pcm1_sync_mfp", 1154 "eram_a5_mfp", 1155 "eram_a6_mfp", 1156 "dsi_dp2_dn2_mfp", 1157 "uart4_rx_tx_mfp_pads", 1158 "uart4_dummy" 1159 }; 1160 1161 static const char * const uart5_groups[] = { 1162 "rmii_rxd1_mfp", 1163 "rmii_rxd0_mfp", 1164 "eram_a9_mfp", 1165 "eram_a11_mfp", 1166 "uart3_rtsb_mfp", 1167 "uart3_ctsb_mfp", 1168 "sd0_d0_mfp", 1169 "sd0_d1_mfp", 1170 }; 1171 1172 static const char * const uart6_groups[] = { 1173 "rmii_txd0_mfp", 1174 "rmii_txd1_mfp", 1175 }; 1176 1177 static const char * const i2s0_groups[] = { 1178 "i2s_d0_mfp", 1179 "i2s_lr_m_clk0_mfp", 1180 "i2s_bclk0_mfp", 1181 "i2s0_dummy", 1182 }; 1183 1184 static const char * const i2s1_groups[] = { 1185 "i2s_d1_mfp", 1186 "i2s_bclk1_mclk1_mfp", 1187 "spi0_ss_mfp", 1188 "spi0_miso_mfp", 1189 "uart0_rx_mfp", 1190 "uart0_tx_mfp", 1191 "i2s1_dummy", 1192 }; 1193 1194 static const char * const pcm0_groups[] = { 1195 "i2s_d0_mfp", 1196 "i2s_d1_mfp", 1197 "i2s_lr_m_clk0_mfp", 1198 "i2s_bclk0_mfp", 1199 "i2s_bclk1_mclk1_mfp", 1200 "spi0_sclk_mosi_mfp", 1201 "spi0_ss_mfp", 1202 "spi0_miso_mfp", 1203 }; 1204 1205 static const char * const pcm1_groups[] = { 1206 "i2s_lr_m_clk0_mfp", 1207 "pcm1_in_out_mfp", 1208 "pcm1_clk_mfp", 1209 "pcm1_sync_mfp", 1210 "lvds_oep_odn_mfp", 1211 "spi0_ss_mfp", 1212 "spi0_miso_mfp", 1213 "uart0_rx_mfp", 1214 "uart0_tx_mfp", 1215 "dsi_cp_dn0_mfp", 1216 "pcm1_dummy", 1217 }; 1218 1219 static const char * const jtag_groups[] = { 1220 "eram_a5_mfp", 1221 "eram_a6_mfp", 1222 "eram_a7_mfp", 1223 "eram_a8_mfp", 1224 "eram_a10_mfp", 1225 "eram_a10_mfp", 1226 "sd0_d2_d3_mfp", 1227 "sd0_cmd_mfp", 1228 "sd0_clk_mfp", 1229 }; 1230 1231 static const char * const pwm0_groups[] = { 1232 "sirq0_mfp", 1233 "rmii_txd0_mfp", 1234 "rmii_rxd1_mfp", 1235 "eram_a5_mfp", 1236 "nand1_ceb3_mfp", 1237 }; 1238 1239 static const char * const pwm1_groups[] = { 1240 "sirq1_mfp", 1241 "rmii_txd1_mfp", 1242 "rmii_rxd0_mfp", 1243 "eram_a6_mfp", 1244 "eram_a8_mfp", 1245 "nand1_ceb0_mfp", 1246 }; 1247 1248 static const char * const pwm2_groups[] = { 1249 "rmii_mdc_mfp", 1250 "rmii_txen_mfp", 1251 "eram_a9_mfp", 1252 "eram_a11_mfp", 1253 }; 1254 1255 static const char * const pwm3_groups[] = { 1256 "rmii_mdio_mfp", 1257 "rmii_rxer_mfp", 1258 "eram_a10_mfp", 1259 }; 1260 1261 static const char * const pwm4_groups[] = { 1262 "pcm1_clk_mfp", 1263 "spi0_ss_mfp", 1264 }; 1265 1266 static const char * const pwm5_groups[] = { 1267 "pcm1_sync_mfp", 1268 "spi0_miso_mfp", 1269 }; 1270 1271 static const char * const sd0_groups[] = { 1272 "sd0_d0_mfp", 1273 "sd0_d1_mfp", 1274 "sd0_d2_d3_mfp", 1275 "sd0_cmd_mfp", 1276 "sd0_clk_mfp", 1277 }; 1278 1279 static const char * const sd1_groups[] = { 1280 "sd1_d0_d3_mfp", 1281 "sd1_cmd_clk_mfp", 1282 "sd1_dummy", 1283 }; 1284 1285 static const char * const sd2_groups[] = { 1286 "nand0_d0_ceb3_mfp", 1287 }; 1288 1289 static const char * const sd3_groups[] = { 1290 "nand1_d0_ceb1_mfp", 1291 }; 1292 1293 static const char * const i2c0_groups[] = { 1294 "i2c0_mfp", 1295 }; 1296 1297 static const char * const i2c1_groups[] = { 1298 "i2c0_mfp", 1299 "i2c1_dummy" 1300 }; 1301 1302 static const char * const i2c2_groups[] = { 1303 "i2c2_dummy" 1304 }; 1305 1306 static const char * const i2c3_groups[] = { 1307 "pcm1_in_out_mfp", 1308 "spi0_sclk_mosi_mfp", 1309 }; 1310 1311 static const char * const i2c4_groups[] = { 1312 "uart4_rx_tx_mfp", 1313 }; 1314 1315 static const char * const i2c5_groups[] = { 1316 "uart0_rx_mfp", 1317 "uart0_tx_mfp", 1318 }; 1319 1320 1321 static const char * const lvds_groups[] = { 1322 "lvds_oep_odn_mfp", 1323 "lvds_ocp_obn_mfp", 1324 "lvds_oap_oan_mfp", 1325 "lvds_e_mfp", 1326 }; 1327 1328 static const char * const usb20_groups[] = { 1329 "eram_a9_mfp", 1330 }; 1331 1332 static const char * const usb30_groups[] = { 1333 "eram_a10_mfp", 1334 }; 1335 1336 static const char * const gpu_groups[] = { 1337 "sd0_d0_mfp", 1338 "sd0_d1_mfp", 1339 "sd0_d2_d3_mfp", 1340 "sd0_cmd_mfp", 1341 "sd0_clk_mfp", 1342 }; 1343 1344 static const char * const mipi_csi0_groups[] = { 1345 "csi0_dn0_dp3_mfp", 1346 }; 1347 1348 static const char * const mipi_csi1_groups[] = { 1349 "csi1_dn0_cp_mfp", 1350 }; 1351 1352 static const char * const mipi_dsi_groups[] = { 1353 "dsi_dp3_dn1_mfp", 1354 "dsi_cp_dn0_mfp", 1355 "dsi_dp2_dn2_mfp", 1356 "mipi_dsi_dummy", 1357 }; 1358 1359 static const char * const nand0_groups[] = { 1360 "nand0_d0_ceb3_mfp", 1361 "nand0_dummy", 1362 }; 1363 1364 static const char * const nand1_groups[] = { 1365 "nand1_d0_ceb1_mfp", 1366 "nand1_ceb3_mfp", 1367 "nand1_ceb0_mfp", 1368 "nand1_dummy", 1369 }; 1370 1371 static const char * const spdif_groups[] = { 1372 "uart0_tx_mfp", 1373 }; 1374 1375 static const char * const sirq0_groups[] = { 1376 "sirq0_mfp", 1377 "sirq0_dummy", 1378 }; 1379 1380 static const char * const sirq1_groups[] = { 1381 "sirq1_mfp", 1382 "sirq1_dummy", 1383 }; 1384 1385 static const char * const sirq2_groups[] = { 1386 "sirq2_dummy", 1387 }; 1388 1389 static const struct owl_pinmux_func s900_functions[] = { 1390 [S900_MUX_ERAM] = FUNCTION(eram), 1391 [S900_MUX_ETH_RMII] = FUNCTION(eth_rmii), 1392 [S900_MUX_ETH_SMII] = FUNCTION(eth_smii), 1393 [S900_MUX_SPI0] = FUNCTION(spi0), 1394 [S900_MUX_SPI1] = FUNCTION(spi1), 1395 [S900_MUX_SPI2] = FUNCTION(spi2), 1396 [S900_MUX_SPI3] = FUNCTION(spi3), 1397 [S900_MUX_SENS0] = FUNCTION(sens0), 1398 [S900_MUX_UART0] = FUNCTION(uart0), 1399 [S900_MUX_UART1] = FUNCTION(uart1), 1400 [S900_MUX_UART2] = FUNCTION(uart2), 1401 [S900_MUX_UART3] = FUNCTION(uart3), 1402 [S900_MUX_UART4] = FUNCTION(uart4), 1403 [S900_MUX_UART5] = FUNCTION(uart5), 1404 [S900_MUX_UART6] = FUNCTION(uart6), 1405 [S900_MUX_I2S0] = FUNCTION(i2s0), 1406 [S900_MUX_I2S1] = FUNCTION(i2s1), 1407 [S900_MUX_PCM0] = FUNCTION(pcm0), 1408 [S900_MUX_PCM1] = FUNCTION(pcm1), 1409 [S900_MUX_JTAG] = FUNCTION(jtag), 1410 [S900_MUX_PWM0] = FUNCTION(pwm0), 1411 [S900_MUX_PWM1] = FUNCTION(pwm1), 1412 [S900_MUX_PWM2] = FUNCTION(pwm2), 1413 [S900_MUX_PWM3] = FUNCTION(pwm3), 1414 [S900_MUX_PWM4] = FUNCTION(pwm4), 1415 [S900_MUX_PWM5] = FUNCTION(pwm5), 1416 [S900_MUX_SD0] = FUNCTION(sd0), 1417 [S900_MUX_SD1] = FUNCTION(sd1), 1418 [S900_MUX_SD2] = FUNCTION(sd2), 1419 [S900_MUX_SD3] = FUNCTION(sd3), 1420 [S900_MUX_I2C0] = FUNCTION(i2c0), 1421 [S900_MUX_I2C1] = FUNCTION(i2c1), 1422 [S900_MUX_I2C2] = FUNCTION(i2c2), 1423 [S900_MUX_I2C3] = FUNCTION(i2c3), 1424 [S900_MUX_I2C4] = FUNCTION(i2c4), 1425 [S900_MUX_I2C5] = FUNCTION(i2c5), 1426 [S900_MUX_LVDS] = FUNCTION(lvds), 1427 [S900_MUX_USB30] = FUNCTION(usb30), 1428 [S900_MUX_USB20] = FUNCTION(usb20), 1429 [S900_MUX_GPU] = FUNCTION(gpu), 1430 [S900_MUX_MIPI_CSI0] = FUNCTION(mipi_csi0), 1431 [S900_MUX_MIPI_CSI1] = FUNCTION(mipi_csi1), 1432 [S900_MUX_MIPI_DSI] = FUNCTION(mipi_dsi), 1433 [S900_MUX_NAND0] = FUNCTION(nand0), 1434 [S900_MUX_NAND1] = FUNCTION(nand1), 1435 [S900_MUX_SPDIF] = FUNCTION(spdif), 1436 [S900_MUX_SIRQ0] = FUNCTION(sirq0), 1437 [S900_MUX_SIRQ1] = FUNCTION(sirq1), 1438 [S900_MUX_SIRQ2] = FUNCTION(sirq2) 1439 }; 1440 1441 /* PAD_PULLCTL0 */ 1442 static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2); 1443 static PAD_PULLCTL_CONF(SIRQ0, 0, 16, 2); 1444 static PAD_PULLCTL_CONF(SIRQ1, 0, 14, 2); 1445 static PAD_PULLCTL_CONF(SIRQ2, 0, 12, 2); 1446 static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 10, 2); 1447 static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 2); 1448 static PAD_PULLCTL_CONF(ERAM_A5, 0, 6, 2); 1449 static PAD_PULLCTL_CONF(ERAM_A6, 0, 4, 2); 1450 static PAD_PULLCTL_CONF(ERAM_A7, 0, 2, 2); 1451 static PAD_PULLCTL_CONF(ERAM_A10, 0, 0, 2); 1452 1453 /* PAD_PULLCTL1 */ 1454 static PAD_PULLCTL_CONF(PCM1_IN, 1, 30, 2); 1455 static PAD_PULLCTL_CONF(PCM1_OUT, 1, 28, 2); 1456 static PAD_PULLCTL_CONF(SD0_D0, 1, 26, 2); 1457 static PAD_PULLCTL_CONF(SD0_D1, 1, 24, 2); 1458 static PAD_PULLCTL_CONF(SD0_D2, 1, 22, 2); 1459 static PAD_PULLCTL_CONF(SD0_D3, 1, 20, 2); 1460 static PAD_PULLCTL_CONF(SD0_CMD, 1, 18, 2); 1461 static PAD_PULLCTL_CONF(SD0_CLK, 1, 16, 2); 1462 static PAD_PULLCTL_CONF(SD1_CMD, 1, 14, 2); 1463 static PAD_PULLCTL_CONF(SD1_D0, 1, 12, 2); 1464 static PAD_PULLCTL_CONF(SD1_D1, 1, 10, 2); 1465 static PAD_PULLCTL_CONF(SD1_D2, 1, 8, 2); 1466 static PAD_PULLCTL_CONF(SD1_D3, 1, 6, 2); 1467 static PAD_PULLCTL_CONF(UART0_RX, 1, 4, 2); 1468 static PAD_PULLCTL_CONF(UART0_TX, 1, 2, 2); 1469 1470 /* PAD_PULLCTL2 */ 1471 static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 26, 2); 1472 static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 24, 2); 1473 static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 22, 2); 1474 static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 20, 2); 1475 static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 18, 2); 1476 static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 16, 2); 1477 static PAD_PULLCTL_CONF(NAND0_D0, 2, 15, 1); 1478 static PAD_PULLCTL_CONF(NAND0_D1, 2, 15, 1); 1479 static PAD_PULLCTL_CONF(NAND0_D2, 2, 15, 1); 1480 static PAD_PULLCTL_CONF(NAND0_D3, 2, 15, 1); 1481 static PAD_PULLCTL_CONF(NAND0_D4, 2, 15, 1); 1482 static PAD_PULLCTL_CONF(NAND0_D5, 2, 15, 1); 1483 static PAD_PULLCTL_CONF(NAND0_D6, 2, 15, 1); 1484 static PAD_PULLCTL_CONF(NAND0_D7, 2, 15, 1); 1485 static PAD_PULLCTL_CONF(NAND0_DQSN, 2, 14, 1); 1486 static PAD_PULLCTL_CONF(NAND0_DQS, 2, 13, 1); 1487 static PAD_PULLCTL_CONF(NAND1_D0, 2, 12, 1); 1488 static PAD_PULLCTL_CONF(NAND1_D1, 2, 12, 1); 1489 static PAD_PULLCTL_CONF(NAND1_D2, 2, 12, 1); 1490 static PAD_PULLCTL_CONF(NAND1_D3, 2, 12, 1); 1491 static PAD_PULLCTL_CONF(NAND1_D4, 2, 12, 1); 1492 static PAD_PULLCTL_CONF(NAND1_D5, 2, 12, 1); 1493 static PAD_PULLCTL_CONF(NAND1_D6, 2, 12, 1); 1494 static PAD_PULLCTL_CONF(NAND1_D7, 2, 12, 1); 1495 static PAD_PULLCTL_CONF(NAND1_DQSN, 2, 11, 1); 1496 static PAD_PULLCTL_CONF(NAND1_DQS, 2, 10, 1); 1497 static PAD_PULLCTL_CONF(SGPIO2, 2, 8, 2); 1498 static PAD_PULLCTL_CONF(SGPIO3, 2, 6, 2); 1499 static PAD_PULLCTL_CONF(UART4_RX, 2, 4, 2); 1500 static PAD_PULLCTL_CONF(UART4_TX, 2, 2, 2); 1501 1502 /* PAD_ST0 */ 1503 static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1); 1504 static PAD_ST_CONF(UART0_RX, 0, 29, 1); 1505 static PAD_ST_CONF(ETH_MDC, 0, 28, 1); 1506 static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1); 1507 static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1); 1508 static PAD_ST_CONF(ETH_TXEN, 0, 21, 1); 1509 static PAD_ST_CONF(ETH_TXD0, 0, 20, 1); 1510 static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1); 1511 static PAD_ST_CONF(SGPIO2, 0, 18, 1); 1512 static PAD_ST_CONF(SGPIO3, 0, 17, 1); 1513 static PAD_ST_CONF(UART4_TX, 0, 16, 1); 1514 static PAD_ST_CONF(I2S_D1, 0, 15, 1); 1515 static PAD_ST_CONF(UART0_TX, 0, 14, 1); 1516 static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1); 1517 static PAD_ST_CONF(SD0_CLK, 0, 12, 1); 1518 static PAD_ST_CONF(ERAM_A5, 0, 11, 1); 1519 static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1); 1520 static PAD_ST_CONF(ERAM_A9, 0, 6, 1); 1521 static PAD_ST_CONF(LVDS_OEP, 0, 5, 1); 1522 static PAD_ST_CONF(LVDS_ODN, 0, 4, 1); 1523 static PAD_ST_CONF(LVDS_OAP, 0, 3, 1); 1524 static PAD_ST_CONF(I2S_BCLK1, 0, 2, 1); 1525 1526 /* PAD_ST1 */ 1527 static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1); 1528 static PAD_ST_CONF(UART4_RX, 1, 28, 1); 1529 static PAD_ST_CONF(UART3_CTSB, 1, 27, 1); 1530 static PAD_ST_CONF(UART3_RTSB, 1, 26, 1); 1531 static PAD_ST_CONF(UART3_RX, 1, 25, 1); 1532 static PAD_ST_CONF(UART2_RTSB, 1, 24, 1); 1533 static PAD_ST_CONF(UART2_CTSB, 1, 23, 1); 1534 static PAD_ST_CONF(UART2_RX, 1, 22, 1); 1535 static PAD_ST_CONF(ETH_RXD0, 1, 21, 1); 1536 static PAD_ST_CONF(ETH_RXD1, 1, 20, 1); 1537 static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1); 1538 static PAD_ST_CONF(ETH_RXER, 1, 18, 1); 1539 static PAD_ST_CONF(ETH_TXD1, 1, 17, 1); 1540 static PAD_ST_CONF(LVDS_OCP, 1, 16, 1); 1541 static PAD_ST_CONF(LVDS_OBP, 1, 15, 1); 1542 static PAD_ST_CONF(LVDS_OBN, 1, 14, 1); 1543 static PAD_ST_CONF(PCM1_OUT, 1, 12, 1); 1544 static PAD_ST_CONF(PCM1_CLK, 1, 11, 1); 1545 static PAD_ST_CONF(PCM1_IN, 1, 10, 1); 1546 static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1); 1547 static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1); 1548 static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1); 1549 static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1); 1550 static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1); 1551 static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1); 1552 static PAD_ST_CONF(SPI0_MISO, 1, 3, 1); 1553 static PAD_ST_CONF(SPI0_SS, 1, 2, 1); 1554 static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1); 1555 static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1); 1556 1557 /* Pad info table */ 1558 static struct owl_padinfo s900_padinfo[NUM_PADS] = { 1559 [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), 1560 [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1), 1561 [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN), 1562 [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER), 1563 [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV), 1564 [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1), 1565 [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0), 1566 [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK), 1567 [ETH_MDC] = PAD_INFO_ST(ETH_MDC), 1568 [ETH_MDIO] = PAD_INFO(ETH_MDIO), 1569 [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0), 1570 [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1), 1571 [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2), 1572 [I2S_D0] = PAD_INFO(I2S_D0), 1573 [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0), 1574 [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0), 1575 [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0), 1576 [I2S_D1] = PAD_INFO_ST(I2S_D1), 1577 [I2S_BCLK1] = PAD_INFO_ST(I2S_BCLK1), 1578 [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1), 1579 [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1), 1580 [PCM1_IN] = PAD_INFO_PULLCTL_ST(PCM1_IN), 1581 [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK), 1582 [PCM1_SYNC] = PAD_INFO_ST(PCM1_SYNC), 1583 [PCM1_OUT] = PAD_INFO_PULLCTL_ST(PCM1_OUT), 1584 [ERAM_A5] = PAD_INFO_PULLCTL_ST(ERAM_A5), 1585 [ERAM_A6] = PAD_INFO_PULLCTL(ERAM_A6), 1586 [ERAM_A7] = PAD_INFO_PULLCTL(ERAM_A7), 1587 [ERAM_A8] = PAD_INFO(ERAM_A8), 1588 [ERAM_A9] = PAD_INFO_ST(ERAM_A9), 1589 [ERAM_A10] = PAD_INFO_PULLCTL(ERAM_A10), 1590 [ERAM_A11] = PAD_INFO(ERAM_A11), 1591 [LVDS_OEP] = PAD_INFO_ST(LVDS_OEP), 1592 [LVDS_OEN] = PAD_INFO(LVDS_OEN), 1593 [LVDS_ODP] = PAD_INFO(LVDS_ODP), 1594 [LVDS_ODN] = PAD_INFO_ST(LVDS_ODN), 1595 [LVDS_OCP] = PAD_INFO_ST(LVDS_OCP), 1596 [LVDS_OCN] = PAD_INFO(LVDS_OCN), 1597 [LVDS_OBP] = PAD_INFO_ST(LVDS_OBP), 1598 [LVDS_OBN] = PAD_INFO_ST(LVDS_OBN), 1599 [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP), 1600 [LVDS_OAN] = PAD_INFO(LVDS_OAN), 1601 [LVDS_EEP] = PAD_INFO(LVDS_EEP), 1602 [LVDS_EEN] = PAD_INFO(LVDS_EEN), 1603 [LVDS_EDP] = PAD_INFO(LVDS_EDP), 1604 [LVDS_EDN] = PAD_INFO(LVDS_EDN), 1605 [LVDS_ECP] = PAD_INFO(LVDS_ECP), 1606 [LVDS_ECN] = PAD_INFO(LVDS_ECN), 1607 [LVDS_EBP] = PAD_INFO(LVDS_EBP), 1608 [LVDS_EBN] = PAD_INFO(LVDS_EBN), 1609 [LVDS_EAP] = PAD_INFO(LVDS_EAP), 1610 [LVDS_EAN] = PAD_INFO(LVDS_EAN), 1611 [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0), 1612 [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1), 1613 [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2), 1614 [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3), 1615 [SD1_D0] = PAD_INFO_PULLCTL(SD1_D0), 1616 [SD1_D1] = PAD_INFO_PULLCTL(SD1_D1), 1617 [SD1_D2] = PAD_INFO_PULLCTL(SD1_D2), 1618 [SD1_D3] = PAD_INFO_PULLCTL(SD1_D3), 1619 [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD), 1620 [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK), 1621 [SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD), 1622 [SD1_CLK] = PAD_INFO(SD1_CLK), 1623 [SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK), 1624 [SPI0_SS] = PAD_INFO_ST(SPI0_SS), 1625 [SPI0_MISO] = PAD_INFO_ST(SPI0_MISO), 1626 [SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI), 1627 [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX), 1628 [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX), 1629 [UART2_RX] = PAD_INFO_ST(UART2_RX), 1630 [UART2_TX] = PAD_INFO(UART2_TX), 1631 [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB), 1632 [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB), 1633 [UART3_RX] = PAD_INFO_ST(UART3_RX), 1634 [UART3_TX] = PAD_INFO(UART3_TX), 1635 [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB), 1636 [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB), 1637 [UART4_RX] = PAD_INFO_PULLCTL_ST(UART4_RX), 1638 [UART4_TX] = PAD_INFO_PULLCTL_ST(UART4_TX), 1639 [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK), 1640 [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA), 1641 [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK), 1642 [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA), 1643 [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK), 1644 [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA), 1645 [CSI0_DN0] = PAD_INFO(CSI0_DN0), 1646 [CSI0_DP0] = PAD_INFO(CSI0_DP0), 1647 [CSI0_DN1] = PAD_INFO(CSI0_DN1), 1648 [CSI0_DP1] = PAD_INFO(CSI0_DP1), 1649 [CSI0_CN] = PAD_INFO(CSI0_CN), 1650 [CSI0_CP] = PAD_INFO(CSI0_CP), 1651 [CSI0_DN2] = PAD_INFO(CSI0_DN2), 1652 [CSI0_DP2] = PAD_INFO(CSI0_DP2), 1653 [CSI0_DN3] = PAD_INFO(CSI0_DN3), 1654 [CSI0_DP3] = PAD_INFO(CSI0_DP3), 1655 [DSI_DP3] = PAD_INFO(DSI_DP3), 1656 [DSI_DN3] = PAD_INFO(DSI_DN3), 1657 [DSI_DP1] = PAD_INFO(DSI_DP1), 1658 [DSI_DN1] = PAD_INFO(DSI_DN1), 1659 [DSI_CP] = PAD_INFO(DSI_CP), 1660 [DSI_CN] = PAD_INFO(DSI_CN), 1661 [DSI_DP0] = PAD_INFO(DSI_DP0), 1662 [DSI_DN0] = PAD_INFO(DSI_DN0), 1663 [DSI_DP2] = PAD_INFO(DSI_DP2), 1664 [DSI_DN2] = PAD_INFO(DSI_DN2), 1665 [SENSOR0_PCLK] = PAD_INFO(SENSOR0_PCLK), 1666 [CSI1_DN0] = PAD_INFO(CSI1_DN0), 1667 [CSI1_DP0] = PAD_INFO(CSI1_DP0), 1668 [CSI1_DN1] = PAD_INFO(CSI1_DN1), 1669 [CSI1_DP1] = PAD_INFO(CSI1_DP1), 1670 [CSI1_CN] = PAD_INFO(CSI1_CN), 1671 [CSI1_CP] = PAD_INFO(CSI1_CP), 1672 [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT), 1673 [NAND0_D0] = PAD_INFO_PULLCTL(NAND0_D0), 1674 [NAND0_D1] = PAD_INFO_PULLCTL(NAND0_D1), 1675 [NAND0_D2] = PAD_INFO_PULLCTL(NAND0_D2), 1676 [NAND0_D3] = PAD_INFO_PULLCTL(NAND0_D3), 1677 [NAND0_D4] = PAD_INFO_PULLCTL(NAND0_D4), 1678 [NAND0_D5] = PAD_INFO_PULLCTL(NAND0_D5), 1679 [NAND0_D6] = PAD_INFO_PULLCTL(NAND0_D6), 1680 [NAND0_D7] = PAD_INFO_PULLCTL(NAND0_D7), 1681 [NAND0_DQS] = PAD_INFO_PULLCTL(NAND0_DQS), 1682 [NAND0_DQSN] = PAD_INFO_PULLCTL(NAND0_DQSN), 1683 [NAND0_ALE] = PAD_INFO(NAND0_ALE), 1684 [NAND0_CLE] = PAD_INFO(NAND0_CLE), 1685 [NAND0_CEB0] = PAD_INFO(NAND0_CEB0), 1686 [NAND0_CEB1] = PAD_INFO(NAND0_CEB1), 1687 [NAND0_CEB2] = PAD_INFO(NAND0_CEB2), 1688 [NAND0_CEB3] = PAD_INFO(NAND0_CEB3), 1689 [NAND1_D0] = PAD_INFO_PULLCTL(NAND1_D0), 1690 [NAND1_D1] = PAD_INFO_PULLCTL(NAND1_D1), 1691 [NAND1_D2] = PAD_INFO_PULLCTL(NAND1_D2), 1692 [NAND1_D3] = PAD_INFO_PULLCTL(NAND1_D3), 1693 [NAND1_D4] = PAD_INFO_PULLCTL(NAND1_D4), 1694 [NAND1_D5] = PAD_INFO_PULLCTL(NAND1_D5), 1695 [NAND1_D6] = PAD_INFO_PULLCTL(NAND1_D6), 1696 [NAND1_D7] = PAD_INFO_PULLCTL(NAND1_D7), 1697 [NAND1_DQS] = PAD_INFO_PULLCTL(NAND1_DQS), 1698 [NAND1_DQSN] = PAD_INFO_PULLCTL(NAND1_DQSN), 1699 [NAND1_ALE] = PAD_INFO(NAND1_ALE), 1700 [NAND1_CLE] = PAD_INFO(NAND1_CLE), 1701 [NAND1_CEB0] = PAD_INFO(NAND1_CEB0), 1702 [NAND1_CEB1] = PAD_INFO(NAND1_CEB1), 1703 [NAND1_CEB2] = PAD_INFO(NAND1_CEB2), 1704 [NAND1_CEB3] = PAD_INFO(NAND1_CEB3), 1705 [SGPIO0] = PAD_INFO(SGPIO0), 1706 [SGPIO1] = PAD_INFO(SGPIO1), 1707 [SGPIO2] = PAD_INFO_PULLCTL_ST(SGPIO2), 1708 [SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3) 1709 }; 1710 1711 static const struct owl_gpio_port s900_gpio_ports[] = { 1712 OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240, 0), 1713 OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C, 0), 1714 OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0), 1715 OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234, 0), 1716 OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230, 0), 1717 OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178, 0) 1718 }; 1719 1720 static struct owl_pinctrl_soc_data s900_pinctrl_data = { 1721 .padinfo = s900_padinfo, 1722 .pins = (const struct pinctrl_pin_desc *)s900_pads, 1723 .npins = ARRAY_SIZE(s900_pads), 1724 .functions = s900_functions, 1725 .nfunctions = ARRAY_SIZE(s900_functions), 1726 .groups = s900_groups, 1727 .ngroups = ARRAY_SIZE(s900_groups), 1728 .ngpios = NUM_GPIOS, 1729 .ports = s900_gpio_ports, 1730 .nports = ARRAY_SIZE(s900_gpio_ports) 1731 }; 1732 1733 static int s900_pinctrl_probe(struct platform_device *pdev) 1734 { 1735 return owl_pinctrl_probe(pdev, &s900_pinctrl_data); 1736 } 1737 1738 static const struct of_device_id s900_pinctrl_of_match[] = { 1739 { .compatible = "actions,s900-pinctrl", }, 1740 { } 1741 }; 1742 1743 static struct platform_driver s900_pinctrl_driver = { 1744 .driver = { 1745 .name = "pinctrl-s900", 1746 .of_match_table = of_match_ptr(s900_pinctrl_of_match), 1747 }, 1748 .probe = s900_pinctrl_probe, 1749 }; 1750 1751 static int __init s900_pinctrl_init(void) 1752 { 1753 return platform_driver_register(&s900_pinctrl_driver); 1754 } 1755 arch_initcall(s900_pinctrl_init); 1756 1757 static void __exit s900_pinctrl_exit(void) 1758 { 1759 platform_driver_unregister(&s900_pinctrl_driver); 1760 } 1761 module_exit(s900_pinctrl_exit); 1762 1763 MODULE_AUTHOR("Actions Semi Inc."); 1764 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 1765 MODULE_DESCRIPTION("Actions Semi S900 SoC Pinctrl Driver"); 1766 MODULE_LICENSE("GPL"); 1767