1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OWL SoC's Pinctrl driver 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Copyright (c) 2018 Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/pinctrl/machine.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 28 #include "../core.h" 29 #include "../pinctrl-utils.h" 30 #include "pinctrl-owl.h" 31 32 /** 33 * struct owl_pinctrl - pinctrl state of the device 34 * @dev: device handle 35 * @pctrldev: pinctrl handle 36 * @chip: gpio chip 37 * @lock: spinlock to protect registers 38 * @clk: clock control 39 * @soc: reference to soc_data 40 * @base: pinctrl register base address 41 * @num_irq: number of possible interrupts 42 * @irq: interrupt numbers 43 */ 44 struct owl_pinctrl { 45 struct device *dev; 46 struct pinctrl_dev *pctrldev; 47 struct gpio_chip chip; 48 raw_spinlock_t lock; 49 struct clk *clk; 50 const struct owl_pinctrl_soc_data *soc; 51 void __iomem *base; 52 unsigned int num_irq; 53 unsigned int *irq; 54 }; 55 56 static void owl_update_bits(void __iomem *base, u32 mask, u32 val) 57 { 58 u32 reg_val; 59 60 reg_val = readl_relaxed(base); 61 62 reg_val = (reg_val & ~mask) | (val & mask); 63 64 writel_relaxed(reg_val, base); 65 } 66 67 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg, 68 u32 bit, u32 width) 69 { 70 u32 tmp, mask; 71 72 tmp = readl_relaxed(pctrl->base + reg); 73 mask = (1 << width) - 1; 74 75 return (tmp >> bit) & mask; 76 } 77 78 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg, 79 u32 bit, u32 width) 80 { 81 u32 mask; 82 83 mask = (1 << width) - 1; 84 mask = mask << bit; 85 86 owl_update_bits(pctrl->base + reg, mask, (arg << bit)); 87 } 88 89 static int owl_get_groups_count(struct pinctrl_dev *pctrldev) 90 { 91 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 92 93 return pctrl->soc->ngroups; 94 } 95 96 static const char *owl_get_group_name(struct pinctrl_dev *pctrldev, 97 unsigned int group) 98 { 99 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 100 101 return pctrl->soc->groups[group].name; 102 } 103 104 static int owl_get_group_pins(struct pinctrl_dev *pctrldev, 105 unsigned int group, 106 const unsigned int **pins, 107 unsigned int *num_pins) 108 { 109 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 110 111 *pins = pctrl->soc->groups[group].pads; 112 *num_pins = pctrl->soc->groups[group].npads; 113 114 return 0; 115 } 116 117 static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev, 118 struct seq_file *s, 119 unsigned int offset) 120 { 121 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 122 123 seq_printf(s, "%s", dev_name(pctrl->dev)); 124 } 125 126 static const struct pinctrl_ops owl_pinctrl_ops = { 127 .get_groups_count = owl_get_groups_count, 128 .get_group_name = owl_get_group_name, 129 .get_group_pins = owl_get_group_pins, 130 .pin_dbg_show = owl_pin_dbg_show, 131 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 132 .dt_free_map = pinctrl_utils_free_map, 133 }; 134 135 static int owl_get_funcs_count(struct pinctrl_dev *pctrldev) 136 { 137 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 138 139 return pctrl->soc->nfunctions; 140 } 141 142 static const char *owl_get_func_name(struct pinctrl_dev *pctrldev, 143 unsigned int function) 144 { 145 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 146 147 return pctrl->soc->functions[function].name; 148 } 149 150 static int owl_get_func_groups(struct pinctrl_dev *pctrldev, 151 unsigned int function, 152 const char * const **groups, 153 unsigned int * const num_groups) 154 { 155 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 156 157 *groups = pctrl->soc->functions[function].groups; 158 *num_groups = pctrl->soc->functions[function].ngroups; 159 160 return 0; 161 } 162 163 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g, 164 int function, 165 u32 *mask, 166 u32 *val) 167 { 168 int id; 169 u32 option_num; 170 u32 option_mask; 171 172 for (id = 0; id < g->nfuncs; id++) { 173 if (g->funcs[id] == function) 174 break; 175 } 176 if (WARN_ON(id == g->nfuncs)) 177 return -EINVAL; 178 179 option_num = (1 << g->mfpctl_width); 180 if (id > option_num) 181 id -= option_num; 182 183 option_mask = option_num - 1; 184 *mask = (option_mask << g->mfpctl_shift); 185 *val = (id << g->mfpctl_shift); 186 187 return 0; 188 } 189 190 static int owl_set_mux(struct pinctrl_dev *pctrldev, 191 unsigned int function, 192 unsigned int group) 193 { 194 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 195 const struct owl_pingroup *g; 196 unsigned long flags; 197 u32 val, mask; 198 199 g = &pctrl->soc->groups[group]; 200 201 if (get_group_mfp_mask_val(g, function, &mask, &val)) 202 return -EINVAL; 203 204 raw_spin_lock_irqsave(&pctrl->lock, flags); 205 206 owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val); 207 208 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 209 210 return 0; 211 } 212 213 static const struct pinmux_ops owl_pinmux_ops = { 214 .get_functions_count = owl_get_funcs_count, 215 .get_function_name = owl_get_func_name, 216 .get_function_groups = owl_get_func_groups, 217 .set_mux = owl_set_mux, 218 }; 219 220 static int owl_pad_pinconf_reg(const struct owl_padinfo *info, 221 unsigned int param, 222 u32 *reg, 223 u32 *bit, 224 u32 *width) 225 { 226 switch (param) { 227 case PIN_CONFIG_BIAS_BUS_HOLD: 228 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 229 case PIN_CONFIG_BIAS_PULL_DOWN: 230 case PIN_CONFIG_BIAS_PULL_UP: 231 if (!info->pullctl) 232 return -EINVAL; 233 *reg = info->pullctl->reg; 234 *bit = info->pullctl->shift; 235 *width = info->pullctl->width; 236 break; 237 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 238 if (!info->st) 239 return -EINVAL; 240 *reg = info->st->reg; 241 *bit = info->st->shift; 242 *width = info->st->width; 243 break; 244 default: 245 return -ENOTSUPP; 246 } 247 248 return 0; 249 } 250 251 static int owl_pin_config_get(struct pinctrl_dev *pctrldev, 252 unsigned int pin, 253 unsigned long *config) 254 { 255 int ret = 0; 256 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 257 const struct owl_padinfo *info; 258 unsigned int param = pinconf_to_config_param(*config); 259 u32 reg, bit, width, arg; 260 261 info = &pctrl->soc->padinfo[pin]; 262 263 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width); 264 if (ret) 265 return ret; 266 267 arg = owl_read_field(pctrl, reg, bit, width); 268 269 if (!pctrl->soc->padctl_val2arg) 270 return -ENOTSUPP; 271 272 ret = pctrl->soc->padctl_val2arg(info, param, &arg); 273 if (ret) 274 return ret; 275 276 *config = pinconf_to_config_packed(param, arg); 277 278 return ret; 279 } 280 281 static int owl_pin_config_set(struct pinctrl_dev *pctrldev, 282 unsigned int pin, 283 unsigned long *configs, 284 unsigned int num_configs) 285 { 286 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 287 const struct owl_padinfo *info; 288 unsigned long flags; 289 unsigned int param; 290 u32 reg, bit, width, arg; 291 int ret = 0, i; 292 293 info = &pctrl->soc->padinfo[pin]; 294 295 for (i = 0; i < num_configs; i++) { 296 param = pinconf_to_config_param(configs[i]); 297 arg = pinconf_to_config_argument(configs[i]); 298 299 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width); 300 if (ret) 301 return ret; 302 303 if (!pctrl->soc->padctl_arg2val) 304 return -ENOTSUPP; 305 306 ret = pctrl->soc->padctl_arg2val(info, param, &arg); 307 if (ret) 308 return ret; 309 310 raw_spin_lock_irqsave(&pctrl->lock, flags); 311 312 owl_write_field(pctrl, reg, arg, bit, width); 313 314 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 315 } 316 317 return ret; 318 } 319 320 static int owl_group_pinconf_reg(const struct owl_pingroup *g, 321 unsigned int param, 322 u32 *reg, 323 u32 *bit, 324 u32 *width) 325 { 326 switch (param) { 327 case PIN_CONFIG_DRIVE_STRENGTH: 328 if (g->drv_reg < 0) 329 return -EINVAL; 330 *reg = g->drv_reg; 331 *bit = g->drv_shift; 332 *width = g->drv_width; 333 break; 334 case PIN_CONFIG_SLEW_RATE: 335 if (g->sr_reg < 0) 336 return -EINVAL; 337 *reg = g->sr_reg; 338 *bit = g->sr_shift; 339 *width = g->sr_width; 340 break; 341 default: 342 return -ENOTSUPP; 343 } 344 345 return 0; 346 } 347 348 static int owl_group_pinconf_arg2val(const struct owl_pingroup *g, 349 unsigned int param, 350 u32 *arg) 351 { 352 switch (param) { 353 case PIN_CONFIG_DRIVE_STRENGTH: 354 switch (*arg) { 355 case 2: 356 *arg = OWL_PINCONF_DRV_2MA; 357 break; 358 case 4: 359 *arg = OWL_PINCONF_DRV_4MA; 360 break; 361 case 8: 362 *arg = OWL_PINCONF_DRV_8MA; 363 break; 364 case 12: 365 *arg = OWL_PINCONF_DRV_12MA; 366 break; 367 default: 368 return -EINVAL; 369 } 370 break; 371 case PIN_CONFIG_SLEW_RATE: 372 if (*arg) 373 *arg = OWL_PINCONF_SLEW_FAST; 374 else 375 *arg = OWL_PINCONF_SLEW_SLOW; 376 break; 377 default: 378 return -ENOTSUPP; 379 } 380 381 return 0; 382 } 383 384 static int owl_group_pinconf_val2arg(const struct owl_pingroup *g, 385 unsigned int param, 386 u32 *arg) 387 { 388 switch (param) { 389 case PIN_CONFIG_DRIVE_STRENGTH: 390 switch (*arg) { 391 case OWL_PINCONF_DRV_2MA: 392 *arg = 2; 393 break; 394 case OWL_PINCONF_DRV_4MA: 395 *arg = 4; 396 break; 397 case OWL_PINCONF_DRV_8MA: 398 *arg = 8; 399 break; 400 case OWL_PINCONF_DRV_12MA: 401 *arg = 12; 402 break; 403 default: 404 return -EINVAL; 405 } 406 break; 407 case PIN_CONFIG_SLEW_RATE: 408 if (*arg) 409 *arg = 1; 410 else 411 *arg = 0; 412 break; 413 default: 414 return -ENOTSUPP; 415 } 416 417 return 0; 418 } 419 420 static int owl_group_config_get(struct pinctrl_dev *pctrldev, 421 unsigned int group, 422 unsigned long *config) 423 { 424 const struct owl_pingroup *g; 425 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 426 unsigned int param = pinconf_to_config_param(*config); 427 u32 reg, bit, width, arg; 428 int ret; 429 430 g = &pctrl->soc->groups[group]; 431 432 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width); 433 if (ret) 434 return ret; 435 436 arg = owl_read_field(pctrl, reg, bit, width); 437 438 ret = owl_group_pinconf_val2arg(g, param, &arg); 439 if (ret) 440 return ret; 441 442 *config = pinconf_to_config_packed(param, arg); 443 444 return ret; 445 } 446 447 static int owl_group_config_set(struct pinctrl_dev *pctrldev, 448 unsigned int group, 449 unsigned long *configs, 450 unsigned int num_configs) 451 { 452 const struct owl_pingroup *g; 453 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 454 unsigned long flags; 455 unsigned int param; 456 u32 reg, bit, width, arg; 457 int ret, i; 458 459 g = &pctrl->soc->groups[group]; 460 461 for (i = 0; i < num_configs; i++) { 462 param = pinconf_to_config_param(configs[i]); 463 arg = pinconf_to_config_argument(configs[i]); 464 465 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width); 466 if (ret) 467 return ret; 468 469 ret = owl_group_pinconf_arg2val(g, param, &arg); 470 if (ret) 471 return ret; 472 473 /* Update register */ 474 raw_spin_lock_irqsave(&pctrl->lock, flags); 475 476 owl_write_field(pctrl, reg, arg, bit, width); 477 478 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 479 } 480 481 return 0; 482 } 483 484 static const struct pinconf_ops owl_pinconf_ops = { 485 .is_generic = true, 486 .pin_config_get = owl_pin_config_get, 487 .pin_config_set = owl_pin_config_set, 488 .pin_config_group_get = owl_group_config_get, 489 .pin_config_group_set = owl_group_config_set, 490 }; 491 492 static struct pinctrl_desc owl_pinctrl_desc = { 493 .pctlops = &owl_pinctrl_ops, 494 .pmxops = &owl_pinmux_ops, 495 .confops = &owl_pinconf_ops, 496 .owner = THIS_MODULE, 497 }; 498 499 static const struct owl_gpio_port * 500 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin) 501 { 502 unsigned int start = 0, i; 503 504 for (i = 0; i < pctrl->soc->nports; i++) { 505 const struct owl_gpio_port *port = &pctrl->soc->ports[i]; 506 507 if (*pin >= start && *pin < start + port->pins) { 508 *pin -= start; 509 return port; 510 } 511 512 start += port->pins; 513 } 514 515 return NULL; 516 } 517 518 static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag) 519 { 520 u32 val; 521 522 val = readl_relaxed(base); 523 524 if (flag) 525 val |= BIT(pin); 526 else 527 val &= ~BIT(pin); 528 529 writel_relaxed(val, base); 530 } 531 532 static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset) 533 { 534 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 535 const struct owl_gpio_port *port; 536 void __iomem *gpio_base; 537 unsigned long flags; 538 539 port = owl_gpio_get_port(pctrl, &offset); 540 if (WARN_ON(port == NULL)) 541 return -ENODEV; 542 543 gpio_base = pctrl->base + port->offset; 544 545 /* 546 * GPIOs have higher priority over other modules, so either setting 547 * them as OUT or IN is sufficient 548 */ 549 raw_spin_lock_irqsave(&pctrl->lock, flags); 550 owl_gpio_update_reg(gpio_base + port->outen, offset, true); 551 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 552 553 return 0; 554 } 555 556 static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset) 557 { 558 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 559 const struct owl_gpio_port *port; 560 void __iomem *gpio_base; 561 unsigned long flags; 562 563 port = owl_gpio_get_port(pctrl, &offset); 564 if (WARN_ON(port == NULL)) 565 return; 566 567 gpio_base = pctrl->base + port->offset; 568 569 raw_spin_lock_irqsave(&pctrl->lock, flags); 570 /* disable gpio output */ 571 owl_gpio_update_reg(gpio_base + port->outen, offset, false); 572 573 /* disable gpio input */ 574 owl_gpio_update_reg(gpio_base + port->inen, offset, false); 575 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 576 } 577 578 static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset) 579 { 580 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 581 const struct owl_gpio_port *port; 582 void __iomem *gpio_base; 583 unsigned long flags; 584 u32 val; 585 586 port = owl_gpio_get_port(pctrl, &offset); 587 if (WARN_ON(port == NULL)) 588 return -ENODEV; 589 590 gpio_base = pctrl->base + port->offset; 591 592 raw_spin_lock_irqsave(&pctrl->lock, flags); 593 val = readl_relaxed(gpio_base + port->dat); 594 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 595 596 return !!(val & BIT(offset)); 597 } 598 599 static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 600 { 601 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 602 const struct owl_gpio_port *port; 603 void __iomem *gpio_base; 604 unsigned long flags; 605 606 port = owl_gpio_get_port(pctrl, &offset); 607 if (WARN_ON(port == NULL)) 608 return; 609 610 gpio_base = pctrl->base + port->offset; 611 612 raw_spin_lock_irqsave(&pctrl->lock, flags); 613 owl_gpio_update_reg(gpio_base + port->dat, offset, value); 614 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 615 } 616 617 static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 618 { 619 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 620 const struct owl_gpio_port *port; 621 void __iomem *gpio_base; 622 unsigned long flags; 623 624 port = owl_gpio_get_port(pctrl, &offset); 625 if (WARN_ON(port == NULL)) 626 return -ENODEV; 627 628 gpio_base = pctrl->base + port->offset; 629 630 raw_spin_lock_irqsave(&pctrl->lock, flags); 631 owl_gpio_update_reg(gpio_base + port->outen, offset, false); 632 owl_gpio_update_reg(gpio_base + port->inen, offset, true); 633 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 634 635 return 0; 636 } 637 638 static int owl_gpio_direction_output(struct gpio_chip *chip, 639 unsigned int offset, int value) 640 { 641 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 642 const struct owl_gpio_port *port; 643 void __iomem *gpio_base; 644 unsigned long flags; 645 646 port = owl_gpio_get_port(pctrl, &offset); 647 if (WARN_ON(port == NULL)) 648 return -ENODEV; 649 650 gpio_base = pctrl->base + port->offset; 651 652 raw_spin_lock_irqsave(&pctrl->lock, flags); 653 owl_gpio_update_reg(gpio_base + port->inen, offset, false); 654 owl_gpio_update_reg(gpio_base + port->outen, offset, true); 655 owl_gpio_update_reg(gpio_base + port->dat, offset, value); 656 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 657 658 return 0; 659 } 660 661 static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type) 662 { 663 const struct owl_gpio_port *port; 664 void __iomem *gpio_base; 665 unsigned long flags; 666 unsigned int offset, value, irq_type = 0; 667 668 switch (type) { 669 case IRQ_TYPE_EDGE_BOTH: 670 /* 671 * Since the hardware doesn't support interrupts on both edges, 672 * emulate it in the software by setting the single edge 673 * interrupt and switching to the opposite edge while ACKing 674 * the interrupt 675 */ 676 if (owl_gpio_get(&pctrl->chip, gpio)) 677 irq_type = OWL_GPIO_INT_EDGE_FALLING; 678 else 679 irq_type = OWL_GPIO_INT_EDGE_RISING; 680 break; 681 682 case IRQ_TYPE_EDGE_RISING: 683 irq_type = OWL_GPIO_INT_EDGE_RISING; 684 break; 685 686 case IRQ_TYPE_EDGE_FALLING: 687 irq_type = OWL_GPIO_INT_EDGE_FALLING; 688 break; 689 690 case IRQ_TYPE_LEVEL_HIGH: 691 irq_type = OWL_GPIO_INT_LEVEL_HIGH; 692 break; 693 694 case IRQ_TYPE_LEVEL_LOW: 695 irq_type = OWL_GPIO_INT_LEVEL_LOW; 696 break; 697 698 default: 699 break; 700 } 701 702 port = owl_gpio_get_port(pctrl, &gpio); 703 if (WARN_ON(port == NULL)) 704 return; 705 706 gpio_base = pctrl->base + port->offset; 707 708 raw_spin_lock_irqsave(&pctrl->lock, flags); 709 710 offset = (gpio < 16) ? 4 : 0; 711 value = readl_relaxed(gpio_base + port->intc_type + offset); 712 value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2)); 713 value |= irq_type << ((gpio % 16) * 2); 714 writel_relaxed(value, gpio_base + port->intc_type + offset); 715 716 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 717 } 718 719 static void owl_gpio_irq_mask(struct irq_data *data) 720 { 721 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 722 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 723 irq_hw_number_t hwirq = irqd_to_hwirq(data); 724 const struct owl_gpio_port *port; 725 unsigned int gpio = hwirq; 726 void __iomem *gpio_base; 727 unsigned long flags; 728 u32 val; 729 730 port = owl_gpio_get_port(pctrl, &gpio); 731 if (WARN_ON(port == NULL)) 732 return; 733 734 gpio_base = pctrl->base + port->offset; 735 736 raw_spin_lock_irqsave(&pctrl->lock, flags); 737 738 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false); 739 740 /* disable port interrupt if no interrupt pending bit is active */ 741 val = readl_relaxed(gpio_base + port->intc_msk); 742 if (val == 0) 743 owl_gpio_update_reg(gpio_base + port->intc_ctl, 744 OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false); 745 746 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 747 748 gpiochip_disable_irq(gc, hwirq); 749 } 750 751 static void owl_gpio_irq_unmask(struct irq_data *data) 752 { 753 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 754 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 755 irq_hw_number_t hwirq = irqd_to_hwirq(data); 756 const struct owl_gpio_port *port; 757 unsigned int gpio = hwirq; 758 void __iomem *gpio_base; 759 unsigned long flags; 760 u32 value; 761 762 port = owl_gpio_get_port(pctrl, &gpio); 763 if (WARN_ON(port == NULL)) 764 return; 765 766 gpiochip_enable_irq(gc, hwirq); 767 768 gpio_base = pctrl->base + port->offset; 769 raw_spin_lock_irqsave(&pctrl->lock, flags); 770 771 /* enable port interrupt */ 772 value = readl_relaxed(gpio_base + port->intc_ctl); 773 value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M)) 774 << port->shared_ctl_offset * 5); 775 writel_relaxed(value, gpio_base + port->intc_ctl); 776 777 /* enable GPIO interrupt */ 778 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true); 779 780 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 781 } 782 783 static void owl_gpio_irq_ack(struct irq_data *data) 784 { 785 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 786 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 787 irq_hw_number_t hwirq = irqd_to_hwirq(data); 788 const struct owl_gpio_port *port; 789 unsigned int gpio = hwirq; 790 void __iomem *gpio_base; 791 unsigned long flags; 792 793 /* 794 * Switch the interrupt edge to the opposite edge of the interrupt 795 * which got triggered for the case of emulating both edges 796 */ 797 if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) { 798 if (owl_gpio_get(gc, hwirq)) 799 irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_FALLING); 800 else 801 irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_RISING); 802 } 803 804 port = owl_gpio_get_port(pctrl, &gpio); 805 if (WARN_ON(port == NULL)) 806 return; 807 808 gpio_base = pctrl->base + port->offset; 809 810 raw_spin_lock_irqsave(&pctrl->lock, flags); 811 812 owl_gpio_update_reg(gpio_base + port->intc_ctl, 813 OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true); 814 815 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 816 } 817 818 static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type) 819 { 820 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 821 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 822 823 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 824 irq_set_handler_locked(data, handle_level_irq); 825 else 826 irq_set_handler_locked(data, handle_edge_irq); 827 828 irq_set_type(pctrl, data->hwirq, type); 829 830 return 0; 831 } 832 833 static const struct irq_chip owl_gpio_irqchip = { 834 .name = "owl-irq", 835 .irq_ack = owl_gpio_irq_ack, 836 .irq_mask = owl_gpio_irq_mask, 837 .irq_unmask = owl_gpio_irq_unmask, 838 .irq_set_type = owl_gpio_irq_set_type, 839 .flags = IRQCHIP_IMMUTABLE, 840 GPIOCHIP_IRQ_RESOURCE_HELPERS, 841 }; 842 843 static void owl_gpio_irq_handler(struct irq_desc *desc) 844 { 845 struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc); 846 struct irq_chip *chip = irq_desc_get_chip(desc); 847 struct irq_domain *domain = pctrl->chip.irq.domain; 848 unsigned int parent = irq_desc_get_irq(desc); 849 const struct owl_gpio_port *port; 850 void __iomem *base; 851 unsigned int pin, offset = 0, i; 852 unsigned long pending_irq; 853 854 chained_irq_enter(chip, desc); 855 856 for (i = 0; i < pctrl->soc->nports; i++) { 857 port = &pctrl->soc->ports[i]; 858 base = pctrl->base + port->offset; 859 860 /* skip ports that are not associated with this irq */ 861 if (parent != pctrl->irq[i]) 862 goto skip; 863 864 pending_irq = readl_relaxed(base + port->intc_pd); 865 866 for_each_set_bit(pin, &pending_irq, port->pins) { 867 generic_handle_domain_irq(domain, offset + pin); 868 869 /* clear pending interrupt */ 870 owl_gpio_update_reg(base + port->intc_pd, pin, true); 871 } 872 873 skip: 874 offset += port->pins; 875 } 876 877 chained_irq_exit(chip, desc); 878 } 879 880 static int owl_gpio_init(struct owl_pinctrl *pctrl) 881 { 882 struct gpio_chip *chip; 883 struct gpio_irq_chip *gpio_irq; 884 int ret, i, j, offset; 885 886 chip = &pctrl->chip; 887 chip->base = -1; 888 chip->ngpio = pctrl->soc->ngpios; 889 chip->label = dev_name(pctrl->dev); 890 chip->parent = pctrl->dev; 891 chip->owner = THIS_MODULE; 892 893 gpio_irq = &chip->irq; 894 gpio_irq_chip_set_chip(gpio_irq, &owl_gpio_irqchip); 895 gpio_irq->handler = handle_simple_irq; 896 gpio_irq->default_type = IRQ_TYPE_NONE; 897 gpio_irq->parent_handler = owl_gpio_irq_handler; 898 gpio_irq->parent_handler_data = pctrl; 899 gpio_irq->num_parents = pctrl->num_irq; 900 gpio_irq->parents = pctrl->irq; 901 902 gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio, 903 sizeof(*gpio_irq->map), GFP_KERNEL); 904 if (!gpio_irq->map) 905 return -ENOMEM; 906 907 for (i = 0, offset = 0; i < pctrl->soc->nports; i++) { 908 const struct owl_gpio_port *port = &pctrl->soc->ports[i]; 909 910 for (j = 0; j < port->pins; j++) 911 gpio_irq->map[offset + j] = gpio_irq->parents[i]; 912 913 offset += port->pins; 914 } 915 916 ret = gpiochip_add_data(&pctrl->chip, pctrl); 917 if (ret) { 918 dev_err(pctrl->dev, "failed to register gpiochip\n"); 919 return ret; 920 } 921 922 return 0; 923 } 924 925 int owl_pinctrl_probe(struct platform_device *pdev, 926 struct owl_pinctrl_soc_data *soc_data) 927 { 928 struct owl_pinctrl *pctrl; 929 int ret, i; 930 931 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 932 if (!pctrl) 933 return -ENOMEM; 934 935 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 936 if (IS_ERR(pctrl->base)) 937 return PTR_ERR(pctrl->base); 938 939 /* enable GPIO/MFP clock */ 940 pctrl->clk = devm_clk_get(&pdev->dev, NULL); 941 if (IS_ERR(pctrl->clk)) { 942 dev_err(&pdev->dev, "no clock defined\n"); 943 return PTR_ERR(pctrl->clk); 944 } 945 946 ret = clk_prepare_enable(pctrl->clk); 947 if (ret) { 948 dev_err(&pdev->dev, "clk enable failed\n"); 949 return ret; 950 } 951 952 raw_spin_lock_init(&pctrl->lock); 953 954 owl_pinctrl_desc.name = dev_name(&pdev->dev); 955 owl_pinctrl_desc.pins = soc_data->pins; 956 owl_pinctrl_desc.npins = soc_data->npins; 957 958 pctrl->chip.direction_input = owl_gpio_direction_input; 959 pctrl->chip.direction_output = owl_gpio_direction_output; 960 pctrl->chip.get = owl_gpio_get; 961 pctrl->chip.set = owl_gpio_set; 962 pctrl->chip.request = owl_gpio_request; 963 pctrl->chip.free = owl_gpio_free; 964 965 pctrl->soc = soc_data; 966 pctrl->dev = &pdev->dev; 967 968 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, 969 &owl_pinctrl_desc, pctrl); 970 if (IS_ERR(pctrl->pctrldev)) { 971 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n"); 972 ret = PTR_ERR(pctrl->pctrldev); 973 goto err_exit; 974 } 975 976 ret = platform_irq_count(pdev); 977 if (ret < 0) 978 goto err_exit; 979 980 pctrl->num_irq = ret; 981 982 pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq, 983 sizeof(*pctrl->irq), GFP_KERNEL); 984 if (!pctrl->irq) { 985 ret = -ENOMEM; 986 goto err_exit; 987 } 988 989 for (i = 0; i < pctrl->num_irq ; i++) { 990 ret = platform_get_irq(pdev, i); 991 if (ret < 0) 992 goto err_exit; 993 pctrl->irq[i] = ret; 994 } 995 996 ret = owl_gpio_init(pctrl); 997 if (ret) 998 goto err_exit; 999 1000 platform_set_drvdata(pdev, pctrl); 1001 1002 return 0; 1003 1004 err_exit: 1005 clk_disable_unprepare(pctrl->clk); 1006 1007 return ret; 1008 } 1009