1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OWL SoC's Pinctrl driver 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Copyright (c) 2018 Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/seq_file.h> 21 #include <linux/slab.h> 22 #include <linux/spinlock.h> 23 24 #include <linux/pinctrl/machine.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 #include <linux/pinctrl/pinconf.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinmux.h> 29 30 #include "../core.h" 31 #include "../pinctrl-utils.h" 32 #include "pinctrl-owl.h" 33 34 /** 35 * struct owl_pinctrl - pinctrl state of the device 36 * @dev: device handle 37 * @pctrldev: pinctrl handle 38 * @chip: gpio chip 39 * @lock: spinlock to protect registers 40 * @clk: clock control 41 * @soc: reference to soc_data 42 * @base: pinctrl register base address 43 * @irq_chip: IRQ chip information 44 * @num_irq: number of possible interrupts 45 * @irq: interrupt numbers 46 */ 47 struct owl_pinctrl { 48 struct device *dev; 49 struct pinctrl_dev *pctrldev; 50 struct gpio_chip chip; 51 raw_spinlock_t lock; 52 struct clk *clk; 53 const struct owl_pinctrl_soc_data *soc; 54 void __iomem *base; 55 struct irq_chip irq_chip; 56 unsigned int num_irq; 57 unsigned int *irq; 58 }; 59 60 static void owl_update_bits(void __iomem *base, u32 mask, u32 val) 61 { 62 u32 reg_val; 63 64 reg_val = readl_relaxed(base); 65 66 reg_val = (reg_val & ~mask) | (val & mask); 67 68 writel_relaxed(reg_val, base); 69 } 70 71 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg, 72 u32 bit, u32 width) 73 { 74 u32 tmp, mask; 75 76 tmp = readl_relaxed(pctrl->base + reg); 77 mask = (1 << width) - 1; 78 79 return (tmp >> bit) & mask; 80 } 81 82 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg, 83 u32 bit, u32 width) 84 { 85 u32 mask; 86 87 mask = (1 << width) - 1; 88 mask = mask << bit; 89 90 owl_update_bits(pctrl->base + reg, mask, (arg << bit)); 91 } 92 93 static int owl_get_groups_count(struct pinctrl_dev *pctrldev) 94 { 95 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 96 97 return pctrl->soc->ngroups; 98 } 99 100 static const char *owl_get_group_name(struct pinctrl_dev *pctrldev, 101 unsigned int group) 102 { 103 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 104 105 return pctrl->soc->groups[group].name; 106 } 107 108 static int owl_get_group_pins(struct pinctrl_dev *pctrldev, 109 unsigned int group, 110 const unsigned int **pins, 111 unsigned int *num_pins) 112 { 113 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 114 115 *pins = pctrl->soc->groups[group].pads; 116 *num_pins = pctrl->soc->groups[group].npads; 117 118 return 0; 119 } 120 121 static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev, 122 struct seq_file *s, 123 unsigned int offset) 124 { 125 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 126 127 seq_printf(s, "%s", dev_name(pctrl->dev)); 128 } 129 130 static const struct pinctrl_ops owl_pinctrl_ops = { 131 .get_groups_count = owl_get_groups_count, 132 .get_group_name = owl_get_group_name, 133 .get_group_pins = owl_get_group_pins, 134 .pin_dbg_show = owl_pin_dbg_show, 135 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 136 .dt_free_map = pinctrl_utils_free_map, 137 }; 138 139 static int owl_get_funcs_count(struct pinctrl_dev *pctrldev) 140 { 141 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 142 143 return pctrl->soc->nfunctions; 144 } 145 146 static const char *owl_get_func_name(struct pinctrl_dev *pctrldev, 147 unsigned int function) 148 { 149 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 150 151 return pctrl->soc->functions[function].name; 152 } 153 154 static int owl_get_func_groups(struct pinctrl_dev *pctrldev, 155 unsigned int function, 156 const char * const **groups, 157 unsigned int * const num_groups) 158 { 159 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 160 161 *groups = pctrl->soc->functions[function].groups; 162 *num_groups = pctrl->soc->functions[function].ngroups; 163 164 return 0; 165 } 166 167 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g, 168 int function, 169 u32 *mask, 170 u32 *val) 171 { 172 int id; 173 u32 option_num; 174 u32 option_mask; 175 176 for (id = 0; id < g->nfuncs; id++) { 177 if (g->funcs[id] == function) 178 break; 179 } 180 if (WARN_ON(id == g->nfuncs)) 181 return -EINVAL; 182 183 option_num = (1 << g->mfpctl_width); 184 if (id > option_num) 185 id -= option_num; 186 187 option_mask = option_num - 1; 188 *mask = (option_mask << g->mfpctl_shift); 189 *val = (id << g->mfpctl_shift); 190 191 return 0; 192 } 193 194 static int owl_set_mux(struct pinctrl_dev *pctrldev, 195 unsigned int function, 196 unsigned int group) 197 { 198 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 199 const struct owl_pingroup *g; 200 unsigned long flags; 201 u32 val, mask; 202 203 g = &pctrl->soc->groups[group]; 204 205 if (get_group_mfp_mask_val(g, function, &mask, &val)) 206 return -EINVAL; 207 208 raw_spin_lock_irqsave(&pctrl->lock, flags); 209 210 owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val); 211 212 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 213 214 return 0; 215 } 216 217 static const struct pinmux_ops owl_pinmux_ops = { 218 .get_functions_count = owl_get_funcs_count, 219 .get_function_name = owl_get_func_name, 220 .get_function_groups = owl_get_func_groups, 221 .set_mux = owl_set_mux, 222 }; 223 224 static int owl_pad_pinconf_reg(const struct owl_padinfo *info, 225 unsigned int param, 226 u32 *reg, 227 u32 *bit, 228 u32 *width) 229 { 230 switch (param) { 231 case PIN_CONFIG_BIAS_BUS_HOLD: 232 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 233 case PIN_CONFIG_BIAS_PULL_DOWN: 234 case PIN_CONFIG_BIAS_PULL_UP: 235 if (!info->pullctl) 236 return -EINVAL; 237 *reg = info->pullctl->reg; 238 *bit = info->pullctl->shift; 239 *width = info->pullctl->width; 240 break; 241 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 242 if (!info->st) 243 return -EINVAL; 244 *reg = info->st->reg; 245 *bit = info->st->shift; 246 *width = info->st->width; 247 break; 248 default: 249 return -ENOTSUPP; 250 } 251 252 return 0; 253 } 254 255 static int owl_pin_config_get(struct pinctrl_dev *pctrldev, 256 unsigned int pin, 257 unsigned long *config) 258 { 259 int ret = 0; 260 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 261 const struct owl_padinfo *info; 262 unsigned int param = pinconf_to_config_param(*config); 263 u32 reg, bit, width, arg; 264 265 info = &pctrl->soc->padinfo[pin]; 266 267 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width); 268 if (ret) 269 return ret; 270 271 arg = owl_read_field(pctrl, reg, bit, width); 272 273 if (!pctrl->soc->padctl_val2arg) 274 return -ENOTSUPP; 275 276 ret = pctrl->soc->padctl_val2arg(info, param, &arg); 277 if (ret) 278 return ret; 279 280 *config = pinconf_to_config_packed(param, arg); 281 282 return ret; 283 } 284 285 static int owl_pin_config_set(struct pinctrl_dev *pctrldev, 286 unsigned int pin, 287 unsigned long *configs, 288 unsigned int num_configs) 289 { 290 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 291 const struct owl_padinfo *info; 292 unsigned long flags; 293 unsigned int param; 294 u32 reg, bit, width, arg; 295 int ret = 0, i; 296 297 info = &pctrl->soc->padinfo[pin]; 298 299 for (i = 0; i < num_configs; i++) { 300 param = pinconf_to_config_param(configs[i]); 301 arg = pinconf_to_config_argument(configs[i]); 302 303 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width); 304 if (ret) 305 return ret; 306 307 if (!pctrl->soc->padctl_arg2val) 308 return -ENOTSUPP; 309 310 ret = pctrl->soc->padctl_arg2val(info, param, &arg); 311 if (ret) 312 return ret; 313 314 raw_spin_lock_irqsave(&pctrl->lock, flags); 315 316 owl_write_field(pctrl, reg, arg, bit, width); 317 318 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 319 } 320 321 return ret; 322 } 323 324 static int owl_group_pinconf_reg(const struct owl_pingroup *g, 325 unsigned int param, 326 u32 *reg, 327 u32 *bit, 328 u32 *width) 329 { 330 switch (param) { 331 case PIN_CONFIG_DRIVE_STRENGTH: 332 if (g->drv_reg < 0) 333 return -EINVAL; 334 *reg = g->drv_reg; 335 *bit = g->drv_shift; 336 *width = g->drv_width; 337 break; 338 case PIN_CONFIG_SLEW_RATE: 339 if (g->sr_reg < 0) 340 return -EINVAL; 341 *reg = g->sr_reg; 342 *bit = g->sr_shift; 343 *width = g->sr_width; 344 break; 345 default: 346 return -ENOTSUPP; 347 } 348 349 return 0; 350 } 351 352 static int owl_group_pinconf_arg2val(const struct owl_pingroup *g, 353 unsigned int param, 354 u32 *arg) 355 { 356 switch (param) { 357 case PIN_CONFIG_DRIVE_STRENGTH: 358 switch (*arg) { 359 case 2: 360 *arg = OWL_PINCONF_DRV_2MA; 361 break; 362 case 4: 363 *arg = OWL_PINCONF_DRV_4MA; 364 break; 365 case 8: 366 *arg = OWL_PINCONF_DRV_8MA; 367 break; 368 case 12: 369 *arg = OWL_PINCONF_DRV_12MA; 370 break; 371 default: 372 return -EINVAL; 373 } 374 break; 375 case PIN_CONFIG_SLEW_RATE: 376 if (*arg) 377 *arg = OWL_PINCONF_SLEW_FAST; 378 else 379 *arg = OWL_PINCONF_SLEW_SLOW; 380 break; 381 default: 382 return -ENOTSUPP; 383 } 384 385 return 0; 386 } 387 388 static int owl_group_pinconf_val2arg(const struct owl_pingroup *g, 389 unsigned int param, 390 u32 *arg) 391 { 392 switch (param) { 393 case PIN_CONFIG_DRIVE_STRENGTH: 394 switch (*arg) { 395 case OWL_PINCONF_DRV_2MA: 396 *arg = 2; 397 break; 398 case OWL_PINCONF_DRV_4MA: 399 *arg = 4; 400 break; 401 case OWL_PINCONF_DRV_8MA: 402 *arg = 8; 403 break; 404 case OWL_PINCONF_DRV_12MA: 405 *arg = 12; 406 break; 407 default: 408 return -EINVAL; 409 } 410 break; 411 case PIN_CONFIG_SLEW_RATE: 412 if (*arg) 413 *arg = 1; 414 else 415 *arg = 0; 416 break; 417 default: 418 return -ENOTSUPP; 419 } 420 421 return 0; 422 } 423 424 static int owl_group_config_get(struct pinctrl_dev *pctrldev, 425 unsigned int group, 426 unsigned long *config) 427 { 428 const struct owl_pingroup *g; 429 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 430 unsigned int param = pinconf_to_config_param(*config); 431 u32 reg, bit, width, arg; 432 int ret; 433 434 g = &pctrl->soc->groups[group]; 435 436 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width); 437 if (ret) 438 return ret; 439 440 arg = owl_read_field(pctrl, reg, bit, width); 441 442 ret = owl_group_pinconf_val2arg(g, param, &arg); 443 if (ret) 444 return ret; 445 446 *config = pinconf_to_config_packed(param, arg); 447 448 return ret; 449 } 450 451 static int owl_group_config_set(struct pinctrl_dev *pctrldev, 452 unsigned int group, 453 unsigned long *configs, 454 unsigned int num_configs) 455 { 456 const struct owl_pingroup *g; 457 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 458 unsigned long flags; 459 unsigned int param; 460 u32 reg, bit, width, arg; 461 int ret, i; 462 463 g = &pctrl->soc->groups[group]; 464 465 for (i = 0; i < num_configs; i++) { 466 param = pinconf_to_config_param(configs[i]); 467 arg = pinconf_to_config_argument(configs[i]); 468 469 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width); 470 if (ret) 471 return ret; 472 473 ret = owl_group_pinconf_arg2val(g, param, &arg); 474 if (ret) 475 return ret; 476 477 /* Update register */ 478 raw_spin_lock_irqsave(&pctrl->lock, flags); 479 480 owl_write_field(pctrl, reg, arg, bit, width); 481 482 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 483 } 484 485 return 0; 486 } 487 488 static const struct pinconf_ops owl_pinconf_ops = { 489 .is_generic = true, 490 .pin_config_get = owl_pin_config_get, 491 .pin_config_set = owl_pin_config_set, 492 .pin_config_group_get = owl_group_config_get, 493 .pin_config_group_set = owl_group_config_set, 494 }; 495 496 static struct pinctrl_desc owl_pinctrl_desc = { 497 .pctlops = &owl_pinctrl_ops, 498 .pmxops = &owl_pinmux_ops, 499 .confops = &owl_pinconf_ops, 500 .owner = THIS_MODULE, 501 }; 502 503 static const struct owl_gpio_port * 504 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin) 505 { 506 unsigned int start = 0, i; 507 508 for (i = 0; i < pctrl->soc->nports; i++) { 509 const struct owl_gpio_port *port = &pctrl->soc->ports[i]; 510 511 if (*pin >= start && *pin < start + port->pins) { 512 *pin -= start; 513 return port; 514 } 515 516 start += port->pins; 517 } 518 519 return NULL; 520 } 521 522 static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag) 523 { 524 u32 val; 525 526 val = readl_relaxed(base); 527 528 if (flag) 529 val |= BIT(pin); 530 else 531 val &= ~BIT(pin); 532 533 writel_relaxed(val, base); 534 } 535 536 static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset) 537 { 538 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 539 const struct owl_gpio_port *port; 540 void __iomem *gpio_base; 541 unsigned long flags; 542 543 port = owl_gpio_get_port(pctrl, &offset); 544 if (WARN_ON(port == NULL)) 545 return -ENODEV; 546 547 gpio_base = pctrl->base + port->offset; 548 549 /* 550 * GPIOs have higher priority over other modules, so either setting 551 * them as OUT or IN is sufficient 552 */ 553 raw_spin_lock_irqsave(&pctrl->lock, flags); 554 owl_gpio_update_reg(gpio_base + port->outen, offset, true); 555 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 556 557 return 0; 558 } 559 560 static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset) 561 { 562 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 563 const struct owl_gpio_port *port; 564 void __iomem *gpio_base; 565 unsigned long flags; 566 567 port = owl_gpio_get_port(pctrl, &offset); 568 if (WARN_ON(port == NULL)) 569 return; 570 571 gpio_base = pctrl->base + port->offset; 572 573 raw_spin_lock_irqsave(&pctrl->lock, flags); 574 /* disable gpio output */ 575 owl_gpio_update_reg(gpio_base + port->outen, offset, false); 576 577 /* disable gpio input */ 578 owl_gpio_update_reg(gpio_base + port->inen, offset, false); 579 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 580 } 581 582 static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset) 583 { 584 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 585 const struct owl_gpio_port *port; 586 void __iomem *gpio_base; 587 unsigned long flags; 588 u32 val; 589 590 port = owl_gpio_get_port(pctrl, &offset); 591 if (WARN_ON(port == NULL)) 592 return -ENODEV; 593 594 gpio_base = pctrl->base + port->offset; 595 596 raw_spin_lock_irqsave(&pctrl->lock, flags); 597 val = readl_relaxed(gpio_base + port->dat); 598 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 599 600 return !!(val & BIT(offset)); 601 } 602 603 static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 604 { 605 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 606 const struct owl_gpio_port *port; 607 void __iomem *gpio_base; 608 unsigned long flags; 609 610 port = owl_gpio_get_port(pctrl, &offset); 611 if (WARN_ON(port == NULL)) 612 return; 613 614 gpio_base = pctrl->base + port->offset; 615 616 raw_spin_lock_irqsave(&pctrl->lock, flags); 617 owl_gpio_update_reg(gpio_base + port->dat, offset, value); 618 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 619 } 620 621 static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 622 { 623 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 624 const struct owl_gpio_port *port; 625 void __iomem *gpio_base; 626 unsigned long flags; 627 628 port = owl_gpio_get_port(pctrl, &offset); 629 if (WARN_ON(port == NULL)) 630 return -ENODEV; 631 632 gpio_base = pctrl->base + port->offset; 633 634 raw_spin_lock_irqsave(&pctrl->lock, flags); 635 owl_gpio_update_reg(gpio_base + port->outen, offset, false); 636 owl_gpio_update_reg(gpio_base + port->inen, offset, true); 637 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 638 639 return 0; 640 } 641 642 static int owl_gpio_direction_output(struct gpio_chip *chip, 643 unsigned int offset, int value) 644 { 645 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 646 const struct owl_gpio_port *port; 647 void __iomem *gpio_base; 648 unsigned long flags; 649 650 port = owl_gpio_get_port(pctrl, &offset); 651 if (WARN_ON(port == NULL)) 652 return -ENODEV; 653 654 gpio_base = pctrl->base + port->offset; 655 656 raw_spin_lock_irqsave(&pctrl->lock, flags); 657 owl_gpio_update_reg(gpio_base + port->inen, offset, false); 658 owl_gpio_update_reg(gpio_base + port->outen, offset, true); 659 owl_gpio_update_reg(gpio_base + port->dat, offset, value); 660 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 661 662 return 0; 663 } 664 665 static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type) 666 { 667 const struct owl_gpio_port *port; 668 void __iomem *gpio_base; 669 unsigned long flags; 670 unsigned int offset, value, irq_type = 0; 671 672 switch (type) { 673 case IRQ_TYPE_EDGE_BOTH: 674 /* 675 * Since the hardware doesn't support interrupts on both edges, 676 * emulate it in the software by setting the single edge 677 * interrupt and switching to the opposite edge while ACKing 678 * the interrupt 679 */ 680 if (owl_gpio_get(&pctrl->chip, gpio)) 681 irq_type = OWL_GPIO_INT_EDGE_FALLING; 682 else 683 irq_type = OWL_GPIO_INT_EDGE_RISING; 684 break; 685 686 case IRQ_TYPE_EDGE_RISING: 687 irq_type = OWL_GPIO_INT_EDGE_RISING; 688 break; 689 690 case IRQ_TYPE_EDGE_FALLING: 691 irq_type = OWL_GPIO_INT_EDGE_FALLING; 692 break; 693 694 case IRQ_TYPE_LEVEL_HIGH: 695 irq_type = OWL_GPIO_INT_LEVEL_HIGH; 696 break; 697 698 case IRQ_TYPE_LEVEL_LOW: 699 irq_type = OWL_GPIO_INT_LEVEL_LOW; 700 break; 701 702 default: 703 break; 704 } 705 706 port = owl_gpio_get_port(pctrl, &gpio); 707 if (WARN_ON(port == NULL)) 708 return; 709 710 gpio_base = pctrl->base + port->offset; 711 712 raw_spin_lock_irqsave(&pctrl->lock, flags); 713 714 offset = (gpio < 16) ? 4 : 0; 715 value = readl_relaxed(gpio_base + port->intc_type + offset); 716 value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2)); 717 value |= irq_type << ((gpio % 16) * 2); 718 writel_relaxed(value, gpio_base + port->intc_type + offset); 719 720 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 721 } 722 723 static void owl_gpio_irq_mask(struct irq_data *data) 724 { 725 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 726 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 727 const struct owl_gpio_port *port; 728 void __iomem *gpio_base; 729 unsigned long flags; 730 unsigned int gpio = data->hwirq; 731 u32 val; 732 733 port = owl_gpio_get_port(pctrl, &gpio); 734 if (WARN_ON(port == NULL)) 735 return; 736 737 gpio_base = pctrl->base + port->offset; 738 739 raw_spin_lock_irqsave(&pctrl->lock, flags); 740 741 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false); 742 743 /* disable port interrupt if no interrupt pending bit is active */ 744 val = readl_relaxed(gpio_base + port->intc_msk); 745 if (val == 0) 746 owl_gpio_update_reg(gpio_base + port->intc_ctl, 747 OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false); 748 749 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 750 } 751 752 static void owl_gpio_irq_unmask(struct irq_data *data) 753 { 754 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 755 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 756 const struct owl_gpio_port *port; 757 void __iomem *gpio_base; 758 unsigned long flags; 759 unsigned int gpio = data->hwirq; 760 u32 value; 761 762 port = owl_gpio_get_port(pctrl, &gpio); 763 if (WARN_ON(port == NULL)) 764 return; 765 766 gpio_base = pctrl->base + port->offset; 767 raw_spin_lock_irqsave(&pctrl->lock, flags); 768 769 /* enable port interrupt */ 770 value = readl_relaxed(gpio_base + port->intc_ctl); 771 value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M)) 772 << port->shared_ctl_offset * 5); 773 writel_relaxed(value, gpio_base + port->intc_ctl); 774 775 /* enable GPIO interrupt */ 776 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true); 777 778 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 779 } 780 781 static void owl_gpio_irq_ack(struct irq_data *data) 782 { 783 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 784 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 785 const struct owl_gpio_port *port; 786 void __iomem *gpio_base; 787 unsigned long flags; 788 unsigned int gpio = data->hwirq; 789 790 /* 791 * Switch the interrupt edge to the opposite edge of the interrupt 792 * which got triggered for the case of emulating both edges 793 */ 794 if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) { 795 if (owl_gpio_get(gc, gpio)) 796 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING); 797 else 798 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING); 799 } 800 801 port = owl_gpio_get_port(pctrl, &gpio); 802 if (WARN_ON(port == NULL)) 803 return; 804 805 gpio_base = pctrl->base + port->offset; 806 807 raw_spin_lock_irqsave(&pctrl->lock, flags); 808 809 owl_gpio_update_reg(gpio_base + port->intc_ctl, 810 OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true); 811 812 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 813 } 814 815 static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type) 816 { 817 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 818 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 819 820 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 821 irq_set_handler_locked(data, handle_level_irq); 822 else 823 irq_set_handler_locked(data, handle_edge_irq); 824 825 irq_set_type(pctrl, data->hwirq, type); 826 827 return 0; 828 } 829 830 static void owl_gpio_irq_handler(struct irq_desc *desc) 831 { 832 struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc); 833 struct irq_chip *chip = irq_desc_get_chip(desc); 834 struct irq_domain *domain = pctrl->chip.irq.domain; 835 unsigned int parent = irq_desc_get_irq(desc); 836 const struct owl_gpio_port *port; 837 void __iomem *base; 838 unsigned int pin, offset = 0, i; 839 unsigned long pending_irq; 840 841 chained_irq_enter(chip, desc); 842 843 for (i = 0; i < pctrl->soc->nports; i++) { 844 port = &pctrl->soc->ports[i]; 845 base = pctrl->base + port->offset; 846 847 /* skip ports that are not associated with this irq */ 848 if (parent != pctrl->irq[i]) 849 goto skip; 850 851 pending_irq = readl_relaxed(base + port->intc_pd); 852 853 for_each_set_bit(pin, &pending_irq, port->pins) { 854 generic_handle_domain_irq(domain, offset + pin); 855 856 /* clear pending interrupt */ 857 owl_gpio_update_reg(base + port->intc_pd, pin, true); 858 } 859 860 skip: 861 offset += port->pins; 862 } 863 864 chained_irq_exit(chip, desc); 865 } 866 867 static int owl_gpio_init(struct owl_pinctrl *pctrl) 868 { 869 struct gpio_chip *chip; 870 struct gpio_irq_chip *gpio_irq; 871 int ret, i, j, offset; 872 873 chip = &pctrl->chip; 874 chip->base = -1; 875 chip->ngpio = pctrl->soc->ngpios; 876 chip->label = dev_name(pctrl->dev); 877 chip->parent = pctrl->dev; 878 chip->owner = THIS_MODULE; 879 880 pctrl->irq_chip.name = chip->of_node->name; 881 pctrl->irq_chip.irq_ack = owl_gpio_irq_ack; 882 pctrl->irq_chip.irq_mask = owl_gpio_irq_mask; 883 pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask; 884 pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type; 885 886 gpio_irq = &chip->irq; 887 gpio_irq->chip = &pctrl->irq_chip; 888 gpio_irq->handler = handle_simple_irq; 889 gpio_irq->default_type = IRQ_TYPE_NONE; 890 gpio_irq->parent_handler = owl_gpio_irq_handler; 891 gpio_irq->parent_handler_data = pctrl; 892 gpio_irq->num_parents = pctrl->num_irq; 893 gpio_irq->parents = pctrl->irq; 894 895 gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio, 896 sizeof(*gpio_irq->map), GFP_KERNEL); 897 if (!gpio_irq->map) 898 return -ENOMEM; 899 900 for (i = 0, offset = 0; i < pctrl->soc->nports; i++) { 901 const struct owl_gpio_port *port = &pctrl->soc->ports[i]; 902 903 for (j = 0; j < port->pins; j++) 904 gpio_irq->map[offset + j] = gpio_irq->parents[i]; 905 906 offset += port->pins; 907 } 908 909 ret = gpiochip_add_data(&pctrl->chip, pctrl); 910 if (ret) { 911 dev_err(pctrl->dev, "failed to register gpiochip\n"); 912 return ret; 913 } 914 915 return 0; 916 } 917 918 int owl_pinctrl_probe(struct platform_device *pdev, 919 struct owl_pinctrl_soc_data *soc_data) 920 { 921 struct owl_pinctrl *pctrl; 922 int ret, i; 923 924 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 925 if (!pctrl) 926 return -ENOMEM; 927 928 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 929 if (IS_ERR(pctrl->base)) 930 return PTR_ERR(pctrl->base); 931 932 /* enable GPIO/MFP clock */ 933 pctrl->clk = devm_clk_get(&pdev->dev, NULL); 934 if (IS_ERR(pctrl->clk)) { 935 dev_err(&pdev->dev, "no clock defined\n"); 936 return PTR_ERR(pctrl->clk); 937 } 938 939 ret = clk_prepare_enable(pctrl->clk); 940 if (ret) { 941 dev_err(&pdev->dev, "clk enable failed\n"); 942 return ret; 943 } 944 945 raw_spin_lock_init(&pctrl->lock); 946 947 owl_pinctrl_desc.name = dev_name(&pdev->dev); 948 owl_pinctrl_desc.pins = soc_data->pins; 949 owl_pinctrl_desc.npins = soc_data->npins; 950 951 pctrl->chip.direction_input = owl_gpio_direction_input; 952 pctrl->chip.direction_output = owl_gpio_direction_output; 953 pctrl->chip.get = owl_gpio_get; 954 pctrl->chip.set = owl_gpio_set; 955 pctrl->chip.request = owl_gpio_request; 956 pctrl->chip.free = owl_gpio_free; 957 958 pctrl->soc = soc_data; 959 pctrl->dev = &pdev->dev; 960 961 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, 962 &owl_pinctrl_desc, pctrl); 963 if (IS_ERR(pctrl->pctrldev)) { 964 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n"); 965 ret = PTR_ERR(pctrl->pctrldev); 966 goto err_exit; 967 } 968 969 ret = platform_irq_count(pdev); 970 if (ret < 0) 971 goto err_exit; 972 973 pctrl->num_irq = ret; 974 975 pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq, 976 sizeof(*pctrl->irq), GFP_KERNEL); 977 if (!pctrl->irq) { 978 ret = -ENOMEM; 979 goto err_exit; 980 } 981 982 for (i = 0; i < pctrl->num_irq ; i++) { 983 ret = platform_get_irq(pdev, i); 984 if (ret < 0) 985 goto err_exit; 986 pctrl->irq[i] = ret; 987 } 988 989 ret = owl_gpio_init(pctrl); 990 if (ret) 991 goto err_exit; 992 993 platform_set_drvdata(pdev, pctrl); 994 995 return 0; 996 997 err_exit: 998 clk_disable_unprepare(pctrl->clk); 999 1000 return ret; 1001 } 1002