xref: /linux/drivers/pinctrl/Kconfig (revision d41af627638a0e1e964d546e385b20650e769ce5)
12744e8afSLinus Walleij#
22744e8afSLinus Walleij# PINCTRL infrastructure and drivers
32744e8afSLinus Walleij#
42744e8afSLinus Walleij
545f034efSLinus Walleijconfig PINCTRL
645f034efSLinus Walleij	bool
72744e8afSLinus Walleij
82744e8afSLinus Walleijif PINCTRL
92744e8afSLinus Walleij
1045f034efSLinus Walleijmenu "Pin controllers"
1145f034efSLinus Walleij	depends on PINCTRL
1245f034efSLinus Walleij
132744e8afSLinus Walleijconfig PINMUX
14ae6b4d85SLinus Walleij	bool "Support pin multiplexing controllers"
15ae6b4d85SLinus Walleij
16ae6b4d85SLinus Walleijconfig PINCONF
17ae6b4d85SLinus Walleij	bool "Support pin configuration controllers"
182744e8afSLinus Walleij
19394349f7SLinus Walleijconfig GENERIC_PINCONF
20394349f7SLinus Walleij	bool
21394349f7SLinus Walleij	select PINCONF
22394349f7SLinus Walleij
232744e8afSLinus Walleijconfig DEBUG_PINCTRL
242744e8afSLinus Walleij	bool "Debug PINCTRL calls"
252744e8afSLinus Walleij	depends on DEBUG_KERNEL
262744e8afSLinus Walleij	help
272744e8afSLinus Walleij	  Say Y here to add some extra checks and diagnostics to PINCTRL calls.
282744e8afSLinus Walleij
29f4e66983SHaojian Zhuangconfig PINCTRL_PXA3xx
30f4e66983SHaojian Zhuang	bool
31f4e66983SHaojian Zhuang	select PINMUX
32f4e66983SHaojian Zhuang
33f4e66983SHaojian Zhuangconfig PINCTRL_MMP2
34f4e66983SHaojian Zhuang	bool "MMP2 pin controller driver"
35f4e66983SHaojian Zhuang	depends on ARCH_MMP
36f4e66983SHaojian Zhuang	select PINCTRL_PXA3xx
37f4e66983SHaojian Zhuang	select PINCONF
38f4e66983SHaojian Zhuang
39e98ea774SLinus Walleijconfig PINCTRL_NOMADIK
40e98ea774SLinus Walleij	bool "Nomadik pin controller driver"
41e98ea774SLinus Walleij	depends on ARCH_U8500
42dbfe8ca2SLinus Walleij	select PINMUX
43*d41af627SLinus Walleij	select PINCONF
44e98ea774SLinus Walleij
45e98ea774SLinus Walleijconfig PINCTRL_DB8500
46e98ea774SLinus Walleij	bool "DB8500 pin controller driver"
47e98ea774SLinus Walleij	depends on PINCTRL_NOMADIK && ARCH_U8500
48e98ea774SLinus Walleij
49f4e66983SHaojian Zhuangconfig PINCTRL_PXA168
50f4e66983SHaojian Zhuang	bool "PXA168 pin controller driver"
51f4e66983SHaojian Zhuang	depends on ARCH_MMP
52f4e66983SHaojian Zhuang	select PINCTRL_PXA3xx
53f4e66983SHaojian Zhuang	select PINCONF
54f4e66983SHaojian Zhuang
55f4e66983SHaojian Zhuangconfig PINCTRL_PXA910
56f4e66983SHaojian Zhuang	bool "PXA910 pin controller driver"
57f4e66983SHaojian Zhuang	depends on ARCH_MMP
58f4e66983SHaojian Zhuang	select PINCTRL_PXA3xx
59f4e66983SHaojian Zhuang	select PINCONF
60f4e66983SHaojian Zhuang
613bece55aSLinus Walleijconfig PINCTRL_SIRF
623bece55aSLinus Walleij	bool "CSR SiRFprimaII pin controller driver"
63393daa81SRongjun Ying	depends on ARCH_PRIMA2
64393daa81SRongjun Ying	select PINMUX
65393daa81SRongjun Ying
66971dac71SStephen Warrenconfig PINCTRL_TEGRA
67971dac71SStephen Warren	bool
68971dac71SStephen Warren
69971dac71SStephen Warrenconfig PINCTRL_TEGRA20
70971dac71SStephen Warren	bool
71971dac71SStephen Warren	select PINMUX
72971dac71SStephen Warren	select PINCONF
73971dac71SStephen Warren	select PINCTRL_TEGRA
74971dac71SStephen Warren
75971dac71SStephen Warrenconfig PINCTRL_TEGRA30
76971dac71SStephen Warren	bool
77971dac71SStephen Warren	select PINMUX
78971dac71SStephen Warren	select PINCONF
79971dac71SStephen Warren	select PINCTRL_TEGRA
80971dac71SStephen Warren
813bece55aSLinus Walleijconfig PINCTRL_U300
823bece55aSLinus Walleij	bool "U300 pin controller driver"
8398da3529SLinus Walleij	depends on ARCH_U300
8498da3529SLinus Walleij	select PINMUX
85dc0b1aa3SLinus Walleij	select GENERIC_PINCONF
8645f034efSLinus Walleij
87ca402d37SLinus Walleijconfig PINCTRL_COH901
88ca402d37SLinus Walleij	bool "ST-Ericsson U300 COH 901 335/571 GPIO"
89b4e3ac74SLinus Walleij	depends on GPIOLIB && ARCH_U300 && PINMUX_U300
90ca402d37SLinus Walleij	help
91ca402d37SLinus Walleij	  Say yes here to support GPIO interface on ST-Ericsson U300.
92ca402d37SLinus Walleij	  The names of the two IP block variants supported are
93ca402d37SLinus Walleij	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
94ca402d37SLinus Walleij	  ports of 8 GPIO pins each.
95ca402d37SLinus Walleij
9645f034efSLinus Walleijendmenu
9798da3529SLinus Walleij
982744e8afSLinus Walleijendif
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