1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Wrapper driver for SERDES used in J721E 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-ti.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/gpio.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/mux/consumer.h> 20 #include <linux/of_address.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/reset-controller.h> 26 27 /* SCM offsets */ 28 #define SERDES_SUP_CTRL 0x4400 29 30 /* SERDES offsets */ 31 #define WIZ_SERDES_CTRL 0x404 32 #define WIZ_SERDES_TOP_CTRL 0x408 33 #define WIZ_SERDES_RST 0x40c 34 #define WIZ_SERDES_TYPEC 0x410 35 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) 36 #define WIZ_LANEDIV(n) (0x484 + (0x40 * (n))) 37 38 #define WIZ_MAX_INPUT_CLOCKS 4 39 /* To include mux clocks, divider clocks and gate clocks */ 40 #define WIZ_MAX_OUTPUT_CLOCKS 32 41 42 #define WIZ_MAX_LANES 4 43 #define WIZ_MUX_NUM_CLOCKS 3 44 #define WIZ_DIV_NUM_CLOCKS_16G 2 45 #define WIZ_DIV_NUM_CLOCKS_10G 1 46 47 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) 48 49 enum wiz_lane_standard_mode { 50 LANE_MODE_GEN1, 51 LANE_MODE_GEN2, 52 LANE_MODE_GEN3, 53 LANE_MODE_GEN4, 54 }; 55 56 enum wiz_refclk_mux_sel { 57 PLL0_REFCLK, 58 PLL1_REFCLK, 59 REFCLK_DIG, 60 }; 61 62 enum wiz_refclk_div_sel { 63 CMN_REFCLK_DIG_DIV, 64 CMN_REFCLK1_DIG_DIV, 65 }; 66 67 enum wiz_clock_input { 68 WIZ_CORE_REFCLK, 69 WIZ_EXT_REFCLK, 70 WIZ_CORE_REFCLK1, 71 WIZ_EXT_REFCLK1, 72 }; 73 74 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); 75 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); 76 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); 77 static const struct reg_field pll1_refclk_mux_sel = 78 REG_FIELD(WIZ_SERDES_RST, 29, 29); 79 static const struct reg_field pll0_refclk_mux_sel = 80 REG_FIELD(WIZ_SERDES_RST, 28, 28); 81 static const struct reg_field refclk_dig_sel_16g = 82 REG_FIELD(WIZ_SERDES_RST, 24, 25); 83 static const struct reg_field refclk_dig_sel_10g = 84 REG_FIELD(WIZ_SERDES_RST, 24, 24); 85 static const struct reg_field pma_cmn_refclk_int_mode = 86 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 87 static const struct reg_field pma_cmn_refclk_mode = 88 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 89 static const struct reg_field pma_cmn_refclk_dig_div = 90 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); 91 static const struct reg_field pma_cmn_refclk1_dig_div = 92 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); 93 94 static const struct reg_field sup_pll0_refclk_mux_sel = 95 REG_FIELD(SERDES_SUP_CTRL, 0, 1); 96 static const struct reg_field sup_pll1_refclk_mux_sel = 97 REG_FIELD(SERDES_SUP_CTRL, 2, 3); 98 static const struct reg_field sup_pma_cmn_refclk1_int_mode = 99 REG_FIELD(SERDES_SUP_CTRL, 4, 5); 100 static const struct reg_field sup_refclk_dig_sel_10g = 101 REG_FIELD(SERDES_SUP_CTRL, 6, 7); 102 static const struct reg_field sup_legacy_clk_override = 103 REG_FIELD(SERDES_SUP_CTRL, 8, 8); 104 105 static const char * const output_clk_names[] = { 106 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk", 107 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk", 108 [TI_WIZ_REFCLK_DIG] = "refclk-dig", 109 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk", 110 }; 111 112 static const struct reg_field p_enable[WIZ_MAX_LANES] = { 113 REG_FIELD(WIZ_LANECTL(0), 30, 31), 114 REG_FIELD(WIZ_LANECTL(1), 30, 31), 115 REG_FIELD(WIZ_LANECTL(2), 30, 31), 116 REG_FIELD(WIZ_LANECTL(3), 30, 31), 117 }; 118 119 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; 120 121 static const struct reg_field p_align[WIZ_MAX_LANES] = { 122 REG_FIELD(WIZ_LANECTL(0), 29, 29), 123 REG_FIELD(WIZ_LANECTL(1), 29, 29), 124 REG_FIELD(WIZ_LANECTL(2), 29, 29), 125 REG_FIELD(WIZ_LANECTL(3), 29, 29), 126 }; 127 128 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { 129 REG_FIELD(WIZ_LANECTL(0), 28, 28), 130 REG_FIELD(WIZ_LANECTL(1), 28, 28), 131 REG_FIELD(WIZ_LANECTL(2), 28, 28), 132 REG_FIELD(WIZ_LANECTL(3), 28, 28), 133 }; 134 135 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { 136 REG_FIELD(WIZ_LANECTL(0), 24, 25), 137 REG_FIELD(WIZ_LANECTL(1), 24, 25), 138 REG_FIELD(WIZ_LANECTL(2), 24, 25), 139 REG_FIELD(WIZ_LANECTL(3), 24, 25), 140 }; 141 142 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { 143 REG_FIELD(WIZ_LANECTL(0), 22, 23), 144 REG_FIELD(WIZ_LANECTL(1), 22, 23), 145 REG_FIELD(WIZ_LANECTL(2), 22, 23), 146 REG_FIELD(WIZ_LANECTL(3), 22, 23), 147 }; 148 149 static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = { 150 REG_FIELD(WIZ_LANECTL(0), 20, 21), 151 REG_FIELD(WIZ_LANECTL(1), 20, 21), 152 REG_FIELD(WIZ_LANECTL(2), 20, 21), 153 REG_FIELD(WIZ_LANECTL(3), 20, 21), 154 }; 155 156 static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = { 157 REG_FIELD(WIZ_LANECTL(0), 6, 7), 158 REG_FIELD(WIZ_LANECTL(1), 6, 7), 159 REG_FIELD(WIZ_LANECTL(2), 6, 7), 160 REG_FIELD(WIZ_LANECTL(3), 6, 7), 161 }; 162 163 static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = { 164 REG_FIELD(WIZ_LANECTL(0), 18, 19), 165 REG_FIELD(WIZ_LANECTL(1), 18, 19), 166 REG_FIELD(WIZ_LANECTL(2), 18, 19), 167 REG_FIELD(WIZ_LANECTL(3), 18, 19), 168 }; 169 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { 170 REG_FIELD(WIZ_LANEDIV(0), 16, 22), 171 REG_FIELD(WIZ_LANEDIV(1), 16, 22), 172 REG_FIELD(WIZ_LANEDIV(2), 16, 22), 173 REG_FIELD(WIZ_LANEDIV(3), 16, 22), 174 }; 175 176 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { 177 REG_FIELD(WIZ_LANEDIV(0), 0, 8), 178 REG_FIELD(WIZ_LANEDIV(1), 0, 8), 179 REG_FIELD(WIZ_LANEDIV(2), 0, 8), 180 REG_FIELD(WIZ_LANEDIV(3), 0, 8), 181 }; 182 183 static const struct reg_field typec_ln10_swap = 184 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 185 186 struct wiz_clk_mux { 187 struct clk_hw hw; 188 struct regmap_field *field; 189 const u32 *table; 190 struct clk_init_data clk_data; 191 }; 192 193 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) 194 195 struct wiz_clk_divider { 196 struct clk_hw hw; 197 struct regmap_field *field; 198 const struct clk_div_table *table; 199 struct clk_init_data clk_data; 200 }; 201 202 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) 203 204 struct wiz_clk_mux_sel { 205 u32 table[WIZ_MAX_INPUT_CLOCKS]; 206 const char *node_name; 207 u32 num_parents; 208 u32 parents[WIZ_MAX_INPUT_CLOCKS]; 209 }; 210 211 struct wiz_clk_div_sel { 212 const struct clk_div_table *table; 213 const char *node_name; 214 }; 215 216 struct wiz_phy_en_refclk { 217 struct clk_hw hw; 218 struct regmap_field *phy_en_refclk; 219 struct clk_init_data clk_data; 220 }; 221 222 #define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw) 223 224 static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = { 225 { 226 /* 227 * Mux value to be configured for each of the input clocks 228 * in the order populated in device tree 229 */ 230 .table = { 1, 0 }, 231 .node_name = "pll0-refclk", 232 }, 233 { 234 .table = { 1, 0 }, 235 .node_name = "pll1-refclk", 236 }, 237 { 238 .table = { 1, 3, 0, 2 }, 239 .node_name = "refclk-dig", 240 }, 241 }; 242 243 static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 244 { 245 /* 246 * Mux value to be configured for each of the input clocks 247 * in the order populated in device tree 248 */ 249 .num_parents = 2, 250 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 251 .table = { 1, 0 }, 252 .node_name = "pll0-refclk", 253 }, 254 { 255 .num_parents = 2, 256 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 257 .table = { 1, 0 }, 258 .node_name = "pll1-refclk", 259 }, 260 { 261 .num_parents = 2, 262 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 263 .table = { 1, 0 }, 264 .node_name = "refclk-dig", 265 }, 266 }; 267 268 static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = { 269 { 270 .num_parents = 3, 271 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 272 .table = { 2, 3, 0 }, 273 .node_name = "pll0-refclk", 274 }, 275 { 276 .num_parents = 3, 277 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 278 .table = { 2, 3, 0 }, 279 .node_name = "pll1-refclk", 280 }, 281 { 282 .num_parents = 3, 283 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 284 .table = { 2, 3, 0 }, 285 .node_name = "refclk-dig", 286 }, 287 }; 288 289 static const struct clk_div_table clk_div_table[] = { 290 { .val = 0, .div = 1, }, 291 { .val = 1, .div = 2, }, 292 { .val = 2, .div = 4, }, 293 { .val = 3, .div = 8, }, 294 { /* sentinel */ }, 295 }; 296 297 static const struct wiz_clk_div_sel clk_div_sel[] = { 298 { 299 .table = clk_div_table, 300 .node_name = "cmn-refclk-dig-div", 301 }, 302 { 303 .table = clk_div_table, 304 .node_name = "cmn-refclk1-dig-div", 305 }, 306 }; 307 308 enum wiz_type { 309 J721E_WIZ_16G, 310 J721E_WIZ_10G, /* Also for J7200 SR1.0 */ 311 AM64_WIZ_10G, 312 J7200_WIZ_10G, /* J7200 SR2.0 */ 313 }; 314 315 struct wiz_data { 316 enum wiz_type type; 317 const struct reg_field *pll0_refclk_mux_sel; 318 const struct reg_field *pll1_refclk_mux_sel; 319 const struct reg_field *refclk_dig_sel; 320 const struct reg_field *pma_cmn_refclk1_dig_div; 321 const struct reg_field *pma_cmn_refclk1_int_mode; 322 const struct wiz_clk_mux_sel *clk_mux_sel; 323 unsigned int clk_div_sel_num; 324 }; 325 326 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ 327 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 328 329 struct wiz { 330 struct regmap *regmap; 331 struct regmap *scm_regmap; 332 enum wiz_type type; 333 const struct wiz_clk_mux_sel *clk_mux_sel; 334 const struct wiz_clk_div_sel *clk_div_sel; 335 unsigned int clk_div_sel_num; 336 struct regmap_field *por_en; 337 struct regmap_field *phy_reset_n; 338 struct regmap_field *phy_en_refclk; 339 struct regmap_field *p_enable[WIZ_MAX_LANES]; 340 struct regmap_field *p_align[WIZ_MAX_LANES]; 341 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; 342 struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; 343 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; 344 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; 345 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; 346 struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES]; 347 struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; 348 struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; 349 struct regmap_field *pma_cmn_refclk_int_mode; 350 struct regmap_field *pma_cmn_refclk1_int_mode; 351 struct regmap_field *pma_cmn_refclk_mode; 352 struct regmap_field *pma_cmn_refclk_dig_div; 353 struct regmap_field *pma_cmn_refclk1_dig_div; 354 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; 355 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; 356 struct regmap_field *typec_ln10_swap; 357 struct regmap_field *sup_legacy_clk_override; 358 359 struct device *dev; 360 u32 num_lanes; 361 struct platform_device *serdes_pdev; 362 struct reset_controller_dev wiz_phy_reset_dev; 363 struct gpio_desc *gpio_typec_dir; 364 int typec_dir_delay; 365 u32 lane_phy_type[WIZ_MAX_LANES]; 366 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; 367 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS]; 368 struct clk_onecell_data clk_data; 369 const struct wiz_data *data; 370 }; 371 372 static int wiz_reset(struct wiz *wiz) 373 { 374 int ret; 375 376 ret = regmap_field_write(wiz->por_en, 0x1); 377 if (ret) 378 return ret; 379 380 mdelay(1); 381 382 ret = regmap_field_write(wiz->por_en, 0x0); 383 if (ret) 384 return ret; 385 386 return 0; 387 } 388 389 static int wiz_p_mac_div_sel(struct wiz *wiz) 390 { 391 u32 num_lanes = wiz->num_lanes; 392 int ret; 393 int i; 394 395 for (i = 0; i < num_lanes; i++) { 396 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || 397 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII || 398 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 399 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); 400 if (ret) 401 return ret; 402 403 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); 404 if (ret) 405 return ret; 406 } 407 } 408 409 return 0; 410 } 411 412 static int wiz_mode_select(struct wiz *wiz) 413 { 414 u32 num_lanes = wiz->num_lanes; 415 enum wiz_lane_standard_mode mode; 416 int ret; 417 int i; 418 419 for (i = 0; i < num_lanes; i++) { 420 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) 421 mode = LANE_MODE_GEN1; 422 else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) 423 mode = LANE_MODE_GEN2; 424 else 425 continue; 426 427 if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 428 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); 429 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); 430 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3); 431 mode = LANE_MODE_GEN1; 432 } 433 434 ret = regmap_field_write(wiz->p_standard_mode[i], mode); 435 if (ret) 436 return ret; 437 } 438 439 return 0; 440 } 441 442 static int wiz_init_raw_interface(struct wiz *wiz, bool enable) 443 { 444 u32 num_lanes = wiz->num_lanes; 445 int i; 446 int ret; 447 448 for (i = 0; i < num_lanes; i++) { 449 ret = regmap_field_write(wiz->p_align[i], enable); 450 if (ret) 451 return ret; 452 453 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); 454 if (ret) 455 return ret; 456 } 457 458 return 0; 459 } 460 461 static int wiz_init(struct wiz *wiz) 462 { 463 struct device *dev = wiz->dev; 464 int ret; 465 466 ret = wiz_reset(wiz); 467 if (ret) { 468 dev_err(dev, "WIZ reset failed\n"); 469 return ret; 470 } 471 472 ret = wiz_mode_select(wiz); 473 if (ret) { 474 dev_err(dev, "WIZ mode select failed\n"); 475 return ret; 476 } 477 478 ret = wiz_p_mac_div_sel(wiz); 479 if (ret) { 480 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); 481 return ret; 482 } 483 484 ret = wiz_init_raw_interface(wiz, true); 485 if (ret) { 486 dev_err(dev, "WIZ interface initialization failed\n"); 487 return ret; 488 } 489 490 return 0; 491 } 492 493 static int wiz_regfield_init(struct wiz *wiz) 494 { 495 struct regmap *regmap = wiz->regmap; 496 struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */ 497 int num_lanes = wiz->num_lanes; 498 struct device *dev = wiz->dev; 499 const struct wiz_data *data = wiz->data; 500 int i; 501 502 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); 503 if (IS_ERR(wiz->por_en)) { 504 dev_err(dev, "POR_EN reg field init failed\n"); 505 return PTR_ERR(wiz->por_en); 506 } 507 508 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, 509 phy_reset_n); 510 if (IS_ERR(wiz->phy_reset_n)) { 511 dev_err(dev, "PHY_RESET_N reg field init failed\n"); 512 return PTR_ERR(wiz->phy_reset_n); 513 } 514 515 wiz->pma_cmn_refclk_int_mode = 516 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); 517 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { 518 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); 519 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); 520 } 521 522 wiz->pma_cmn_refclk_mode = 523 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); 524 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { 525 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); 526 return PTR_ERR(wiz->pma_cmn_refclk_mode); 527 } 528 529 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] = 530 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div); 531 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) { 532 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); 533 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); 534 } 535 536 if (data->pma_cmn_refclk1_dig_div) { 537 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = 538 devm_regmap_field_alloc(dev, regmap, 539 *data->pma_cmn_refclk1_dig_div); 540 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { 541 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); 542 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); 543 } 544 } 545 546 if (wiz->scm_regmap) { 547 scm_regmap = wiz->scm_regmap; 548 wiz->sup_legacy_clk_override = 549 devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override); 550 if (IS_ERR(wiz->sup_legacy_clk_override)) { 551 dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n"); 552 return PTR_ERR(wiz->sup_legacy_clk_override); 553 } 554 } 555 556 wiz->mux_sel_field[PLL0_REFCLK] = 557 devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel); 558 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { 559 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); 560 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); 561 } 562 563 wiz->mux_sel_field[PLL1_REFCLK] = 564 devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel); 565 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { 566 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); 567 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); 568 } 569 570 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap, 571 *data->refclk_dig_sel); 572 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { 573 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); 574 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); 575 } 576 577 if (data->pma_cmn_refclk1_int_mode) { 578 wiz->pma_cmn_refclk1_int_mode = 579 devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode); 580 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) { 581 dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n"); 582 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode); 583 } 584 } 585 586 for (i = 0; i < num_lanes; i++) { 587 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, 588 p_enable[i]); 589 if (IS_ERR(wiz->p_enable[i])) { 590 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 591 return PTR_ERR(wiz->p_enable[i]); 592 } 593 594 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, 595 p_align[i]); 596 if (IS_ERR(wiz->p_align[i])) { 597 dev_err(dev, "P%d_ALIGN reg field init failed\n", i); 598 return PTR_ERR(wiz->p_align[i]); 599 } 600 601 wiz->p_raw_auto_start[i] = 602 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); 603 if (IS_ERR(wiz->p_raw_auto_start[i])) { 604 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", 605 i); 606 return PTR_ERR(wiz->p_raw_auto_start[i]); 607 } 608 609 wiz->p_standard_mode[i] = 610 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); 611 if (IS_ERR(wiz->p_standard_mode[i])) { 612 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", 613 i); 614 return PTR_ERR(wiz->p_standard_mode[i]); 615 } 616 617 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); 618 if (IS_ERR(wiz->p0_fullrt_div[i])) { 619 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i); 620 return PTR_ERR(wiz->p0_fullrt_div[i]); 621 } 622 623 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]); 624 if (IS_ERR(wiz->p0_mac_src_sel[i])) { 625 dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i); 626 return PTR_ERR(wiz->p0_mac_src_sel[i]); 627 } 628 629 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]); 630 if (IS_ERR(wiz->p0_rxfclk_sel[i])) { 631 dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i); 632 return PTR_ERR(wiz->p0_rxfclk_sel[i]); 633 } 634 635 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]); 636 if (IS_ERR(wiz->p0_refclk_sel[i])) { 637 dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i); 638 return PTR_ERR(wiz->p0_refclk_sel[i]); 639 } 640 641 wiz->p_mac_div_sel0[i] = 642 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); 643 if (IS_ERR(wiz->p_mac_div_sel0[i])) { 644 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n", 645 i); 646 return PTR_ERR(wiz->p_mac_div_sel0[i]); 647 } 648 649 wiz->p_mac_div_sel1[i] = 650 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]); 651 if (IS_ERR(wiz->p_mac_div_sel1[i])) { 652 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n", 653 i); 654 return PTR_ERR(wiz->p_mac_div_sel1[i]); 655 } 656 } 657 658 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, 659 typec_ln10_swap); 660 if (IS_ERR(wiz->typec_ln10_swap)) { 661 dev_err(dev, "LN10_SWAP reg field init failed\n"); 662 return PTR_ERR(wiz->typec_ln10_swap); 663 } 664 665 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); 666 if (IS_ERR(wiz->phy_en_refclk)) { 667 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n"); 668 return PTR_ERR(wiz->phy_en_refclk); 669 } 670 671 return 0; 672 } 673 674 static int wiz_phy_en_refclk_enable(struct clk_hw *hw) 675 { 676 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 677 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 678 679 regmap_field_write(phy_en_refclk, 1); 680 681 return 0; 682 } 683 684 static void wiz_phy_en_refclk_disable(struct clk_hw *hw) 685 { 686 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 687 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 688 689 regmap_field_write(phy_en_refclk, 0); 690 } 691 692 static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw) 693 { 694 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 695 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 696 int val; 697 698 regmap_field_read(phy_en_refclk, &val); 699 700 return !!val; 701 } 702 703 static const struct clk_ops wiz_phy_en_refclk_ops = { 704 .enable = wiz_phy_en_refclk_enable, 705 .disable = wiz_phy_en_refclk_disable, 706 .is_enabled = wiz_phy_en_refclk_is_enabled, 707 }; 708 709 static int wiz_phy_en_refclk_register(struct wiz *wiz) 710 { 711 struct wiz_phy_en_refclk *wiz_phy_en_refclk; 712 struct device *dev = wiz->dev; 713 struct clk_init_data *init; 714 struct clk *clk; 715 716 wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL); 717 if (!wiz_phy_en_refclk) 718 return -ENOMEM; 719 720 init = &wiz_phy_en_refclk->clk_data; 721 722 init->ops = &wiz_phy_en_refclk_ops; 723 init->flags = 0; 724 init->name = output_clk_names[TI_WIZ_PHY_EN_REFCLK]; 725 726 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; 727 wiz_phy_en_refclk->hw.init = init; 728 729 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); 730 if (IS_ERR(clk)) 731 return PTR_ERR(clk); 732 733 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk; 734 735 return 0; 736 } 737 738 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) 739 { 740 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 741 struct regmap_field *field = mux->field; 742 unsigned int val; 743 744 regmap_field_read(field, &val); 745 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val); 746 } 747 748 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) 749 { 750 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 751 struct regmap_field *field = mux->field; 752 int val; 753 754 val = mux->table[index]; 755 return regmap_field_write(field, val); 756 } 757 758 static const struct clk_ops wiz_clk_mux_ops = { 759 .set_parent = wiz_clk_mux_set_parent, 760 .get_parent = wiz_clk_mux_get_parent, 761 }; 762 763 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field, 764 const struct wiz_clk_mux_sel *mux_sel, int clk_index) 765 { 766 struct device *dev = wiz->dev; 767 struct clk_init_data *init; 768 const char **parent_names; 769 unsigned int num_parents; 770 struct wiz_clk_mux *mux; 771 char clk_name[100]; 772 struct clk *clk; 773 int ret = 0, i; 774 775 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 776 if (!mux) 777 return -ENOMEM; 778 779 num_parents = mux_sel->num_parents; 780 781 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); 782 if (!parent_names) 783 return -ENOMEM; 784 785 for (i = 0; i < num_parents; i++) { 786 clk = wiz->input_clks[mux_sel->parents[i]]; 787 if (IS_ERR_OR_NULL(clk)) { 788 dev_err(dev, "Failed to get parent clk for %s\n", 789 output_clk_names[clk_index]); 790 ret = -EINVAL; 791 goto err; 792 } 793 parent_names[i] = __clk_get_name(clk); 794 } 795 796 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]); 797 798 init = &mux->clk_data; 799 800 init->ops = &wiz_clk_mux_ops; 801 init->flags = CLK_SET_RATE_NO_REPARENT; 802 init->parent_names = parent_names; 803 init->num_parents = num_parents; 804 init->name = clk_name; 805 806 mux->field = field; 807 mux->table = mux_sel->table; 808 mux->hw.init = init; 809 810 clk = devm_clk_register(dev, &mux->hw); 811 if (IS_ERR(clk)) { 812 ret = PTR_ERR(clk); 813 goto err; 814 } 815 816 wiz->output_clks[clk_index] = clk; 817 818 err: 819 kfree(parent_names); 820 821 return ret; 822 } 823 824 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node, 825 struct regmap_field *field, const u32 *table) 826 { 827 struct device *dev = wiz->dev; 828 struct clk_init_data *init; 829 const char **parent_names; 830 unsigned int num_parents; 831 struct wiz_clk_mux *mux; 832 char clk_name[100]; 833 struct clk *clk; 834 int ret; 835 836 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 837 if (!mux) 838 return -ENOMEM; 839 840 num_parents = of_clk_get_parent_count(node); 841 if (num_parents < 2) { 842 dev_err(dev, "SERDES clock must have parents\n"); 843 return -EINVAL; 844 } 845 846 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 847 GFP_KERNEL); 848 if (!parent_names) 849 return -ENOMEM; 850 851 of_clk_parent_fill(node, parent_names, num_parents); 852 853 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 854 node->name); 855 856 init = &mux->clk_data; 857 858 init->ops = &wiz_clk_mux_ops; 859 init->flags = CLK_SET_RATE_NO_REPARENT; 860 init->parent_names = parent_names; 861 init->num_parents = num_parents; 862 init->name = clk_name; 863 864 mux->field = field; 865 mux->table = table; 866 mux->hw.init = init; 867 868 clk = devm_clk_register(dev, &mux->hw); 869 if (IS_ERR(clk)) 870 return PTR_ERR(clk); 871 872 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 873 if (ret) 874 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 875 876 return ret; 877 } 878 879 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, 880 unsigned long parent_rate) 881 { 882 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 883 struct regmap_field *field = div->field; 884 int val; 885 886 regmap_field_read(field, &val); 887 888 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); 889 } 890 891 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 892 unsigned long *prate) 893 { 894 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 895 896 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); 897 } 898 899 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 900 unsigned long parent_rate) 901 { 902 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 903 struct regmap_field *field = div->field; 904 int val; 905 906 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); 907 if (val < 0) 908 return val; 909 910 return regmap_field_write(field, val); 911 } 912 913 static const struct clk_ops wiz_clk_div_ops = { 914 .recalc_rate = wiz_clk_div_recalc_rate, 915 .round_rate = wiz_clk_div_round_rate, 916 .set_rate = wiz_clk_div_set_rate, 917 }; 918 919 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, 920 struct regmap_field *field, 921 const struct clk_div_table *table) 922 { 923 struct device *dev = wiz->dev; 924 struct wiz_clk_divider *div; 925 struct clk_init_data *init; 926 const char **parent_names; 927 char clk_name[100]; 928 struct clk *clk; 929 int ret; 930 931 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 932 if (!div) 933 return -ENOMEM; 934 935 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 936 node->name); 937 938 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 939 if (!parent_names) 940 return -ENOMEM; 941 942 of_clk_parent_fill(node, parent_names, 1); 943 944 init = &div->clk_data; 945 946 init->ops = &wiz_clk_div_ops; 947 init->flags = 0; 948 init->parent_names = parent_names; 949 init->num_parents = 1; 950 init->name = clk_name; 951 952 div->field = field; 953 div->table = table; 954 div->hw.init = init; 955 956 clk = devm_clk_register(dev, &div->hw); 957 if (IS_ERR(clk)) 958 return PTR_ERR(clk); 959 960 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 961 if (ret) 962 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 963 964 return ret; 965 } 966 967 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) 968 { 969 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 970 struct device *dev = wiz->dev; 971 struct device_node *clk_node; 972 int i; 973 974 switch (wiz->type) { 975 case AM64_WIZ_10G: 976 case J7200_WIZ_10G: 977 of_clk_del_provider(dev->of_node); 978 return; 979 default: 980 break; 981 } 982 983 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 984 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); 985 of_clk_del_provider(clk_node); 986 of_node_put(clk_node); 987 } 988 989 for (i = 0; i < wiz->clk_div_sel_num; i++) { 990 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name); 991 of_clk_del_provider(clk_node); 992 of_node_put(clk_node); 993 } 994 995 of_clk_del_provider(wiz->dev->of_node); 996 } 997 998 static int wiz_clock_register(struct wiz *wiz) 999 { 1000 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1001 struct device *dev = wiz->dev; 1002 struct device_node *node = dev->of_node; 1003 int clk_index; 1004 int ret; 1005 int i; 1006 1007 clk_index = TI_WIZ_PLL0_REFCLK; 1008 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { 1009 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); 1010 if (ret) { 1011 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]); 1012 return ret; 1013 } 1014 } 1015 1016 ret = wiz_phy_en_refclk_register(wiz); 1017 if (ret) { 1018 dev_err(dev, "Failed to add phy-en-refclk\n"); 1019 return ret; 1020 } 1021 1022 wiz->clk_data.clks = wiz->output_clks; 1023 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS; 1024 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data); 1025 if (ret) 1026 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 1027 1028 return ret; 1029 } 1030 1031 static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 1032 { 1033 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1034 struct device *dev = wiz->dev; 1035 struct device_node *clk_node; 1036 const char *node_name; 1037 unsigned long rate; 1038 struct clk *clk; 1039 int ret; 1040 int i; 1041 1042 clk = devm_clk_get(dev, "core_ref_clk"); 1043 if (IS_ERR(clk)) { 1044 dev_err(dev, "core_ref_clk clock not found\n"); 1045 ret = PTR_ERR(clk); 1046 return ret; 1047 } 1048 wiz->input_clks[WIZ_CORE_REFCLK] = clk; 1049 1050 rate = clk_get_rate(clk); 1051 if (rate >= 100000000) 1052 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 1053 else 1054 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 1055 1056 if (wiz->data->pma_cmn_refclk1_int_mode) { 1057 clk = devm_clk_get(dev, "core_ref1_clk"); 1058 if (IS_ERR(clk)) { 1059 dev_err(dev, "core_ref1_clk clock not found\n"); 1060 ret = PTR_ERR(clk); 1061 return ret; 1062 } 1063 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; 1064 1065 rate = clk_get_rate(clk); 1066 if (rate >= 100000000) 1067 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); 1068 else 1069 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); 1070 } 1071 1072 clk = devm_clk_get(dev, "ext_ref_clk"); 1073 if (IS_ERR(clk)) { 1074 dev_err(dev, "ext_ref_clk clock not found\n"); 1075 ret = PTR_ERR(clk); 1076 return ret; 1077 } 1078 wiz->input_clks[WIZ_EXT_REFCLK] = clk; 1079 1080 rate = clk_get_rate(clk); 1081 if (rate >= 100000000) 1082 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 1083 else 1084 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 1085 1086 switch (wiz->type) { 1087 case AM64_WIZ_10G: 1088 case J7200_WIZ_10G: 1089 ret = wiz_clock_register(wiz); 1090 if (ret) 1091 dev_err(dev, "Failed to register wiz clocks\n"); 1092 return ret; 1093 default: 1094 break; 1095 } 1096 1097 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 1098 node_name = clk_mux_sel[i].node_name; 1099 clk_node = of_get_child_by_name(node, node_name); 1100 if (!clk_node) { 1101 dev_err(dev, "Unable to get %s node\n", node_name); 1102 ret = -EINVAL; 1103 goto err; 1104 } 1105 1106 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i], 1107 clk_mux_sel[i].table); 1108 if (ret) { 1109 dev_err(dev, "Failed to register %s clock\n", 1110 node_name); 1111 of_node_put(clk_node); 1112 goto err; 1113 } 1114 1115 of_node_put(clk_node); 1116 } 1117 1118 for (i = 0; i < wiz->clk_div_sel_num; i++) { 1119 node_name = clk_div_sel[i].node_name; 1120 clk_node = of_get_child_by_name(node, node_name); 1121 if (!clk_node) { 1122 dev_err(dev, "Unable to get %s node\n", node_name); 1123 ret = -EINVAL; 1124 goto err; 1125 } 1126 1127 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i], 1128 clk_div_sel[i].table); 1129 if (ret) { 1130 dev_err(dev, "Failed to register %s clock\n", 1131 node_name); 1132 of_node_put(clk_node); 1133 goto err; 1134 } 1135 1136 of_node_put(clk_node); 1137 } 1138 1139 return 0; 1140 err: 1141 wiz_clock_cleanup(wiz, node); 1142 1143 return ret; 1144 } 1145 1146 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, 1147 unsigned long id) 1148 { 1149 struct device *dev = rcdev->dev; 1150 struct wiz *wiz = dev_get_drvdata(dev); 1151 int ret = 0; 1152 1153 if (id == 0) { 1154 ret = regmap_field_write(wiz->phy_reset_n, false); 1155 return ret; 1156 } 1157 1158 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); 1159 return ret; 1160 } 1161 1162 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) 1163 { 1164 switch (wiz->type) { 1165 case AM64_WIZ_10G: 1166 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) 1167 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); 1168 break; 1169 case J721E_WIZ_10G: 1170 case J7200_WIZ_10G: 1171 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) 1172 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); 1173 break; 1174 default: 1175 return 0; 1176 } 1177 return 0; 1178 } 1179 1180 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, 1181 unsigned long id) 1182 { 1183 struct device *dev = rcdev->dev; 1184 struct wiz *wiz = dev_get_drvdata(dev); 1185 int ret; 1186 1187 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ 1188 if (id == 0 && wiz->gpio_typec_dir) { 1189 if (wiz->typec_dir_delay) 1190 msleep_interruptible(wiz->typec_dir_delay); 1191 1192 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) 1193 regmap_field_write(wiz->typec_ln10_swap, 1); 1194 else 1195 regmap_field_write(wiz->typec_ln10_swap, 0); 1196 } 1197 1198 if (id == 0) { 1199 ret = regmap_field_write(wiz->phy_reset_n, true); 1200 return ret; 1201 } 1202 1203 ret = wiz_phy_fullrt_div(wiz, id - 1); 1204 if (ret) 1205 return ret; 1206 1207 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) 1208 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); 1209 else 1210 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); 1211 1212 return ret; 1213 } 1214 1215 static const struct reset_control_ops wiz_phy_reset_ops = { 1216 .assert = wiz_phy_reset_assert, 1217 .deassert = wiz_phy_reset_deassert, 1218 }; 1219 1220 static const struct regmap_config wiz_regmap_config = { 1221 .reg_bits = 32, 1222 .val_bits = 32, 1223 .reg_stride = 4, 1224 .fast_io = true, 1225 }; 1226 1227 static struct wiz_data j721e_16g_data = { 1228 .type = J721E_WIZ_16G, 1229 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1230 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1231 .refclk_dig_sel = &refclk_dig_sel_16g, 1232 .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div, 1233 .clk_mux_sel = clk_mux_sel_16g, 1234 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G, 1235 }; 1236 1237 static struct wiz_data j721e_10g_data = { 1238 .type = J721E_WIZ_10G, 1239 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1240 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1241 .refclk_dig_sel = &refclk_dig_sel_10g, 1242 .clk_mux_sel = clk_mux_sel_10g, 1243 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1244 }; 1245 1246 static struct wiz_data am64_10g_data = { 1247 .type = AM64_WIZ_10G, 1248 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1249 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1250 .refclk_dig_sel = &refclk_dig_sel_10g, 1251 .clk_mux_sel = clk_mux_sel_10g, 1252 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1253 }; 1254 1255 static struct wiz_data j7200_pg2_10g_data = { 1256 .type = J7200_WIZ_10G, 1257 .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel, 1258 .pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel, 1259 .refclk_dig_sel = &sup_refclk_dig_sel_10g, 1260 .pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode, 1261 .clk_mux_sel = clk_mux_sel_10g_2_refclk, 1262 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1263 }; 1264 1265 static const struct of_device_id wiz_id_table[] = { 1266 { 1267 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, 1268 }, 1269 { 1270 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data, 1271 }, 1272 { 1273 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data, 1274 }, 1275 { 1276 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data, 1277 }, 1278 {} 1279 }; 1280 MODULE_DEVICE_TABLE(of, wiz_id_table); 1281 1282 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) 1283 { 1284 struct device_node *serdes, *subnode; 1285 1286 serdes = of_get_child_by_name(dev->of_node, "serdes"); 1287 if (!serdes) { 1288 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); 1289 return -EINVAL; 1290 } 1291 1292 for_each_child_of_node(serdes, subnode) { 1293 u32 reg, num_lanes = 1, phy_type = PHY_NONE; 1294 int ret, i; 1295 1296 if (!(of_node_name_eq(subnode, "phy") || 1297 of_node_name_eq(subnode, "link"))) 1298 continue; 1299 1300 ret = of_property_read_u32(subnode, "reg", ®); 1301 if (ret) { 1302 of_node_put(subnode); 1303 dev_err(dev, 1304 "%s: Reading \"reg\" from \"%s\" failed: %d\n", 1305 __func__, subnode->name, ret); 1306 return ret; 1307 } 1308 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); 1309 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); 1310 1311 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, 1312 reg, reg + num_lanes - 1, phy_type); 1313 1314 for (i = reg; i < reg + num_lanes; i++) 1315 wiz->lane_phy_type[i] = phy_type; 1316 } 1317 1318 return 0; 1319 } 1320 1321 static int wiz_probe(struct platform_device *pdev) 1322 { 1323 struct reset_controller_dev *phy_reset_dev; 1324 struct device *dev = &pdev->dev; 1325 struct device_node *node = dev->of_node; 1326 struct platform_device *serdes_pdev; 1327 bool already_configured = false; 1328 struct device_node *child_node; 1329 struct regmap *regmap; 1330 struct resource res; 1331 void __iomem *base; 1332 struct wiz *wiz; 1333 int ret, val, i; 1334 u32 num_lanes; 1335 const struct wiz_data *data; 1336 1337 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); 1338 if (!wiz) 1339 return -ENOMEM; 1340 1341 data = of_device_get_match_data(dev); 1342 if (!data) { 1343 dev_err(dev, "NULL device data\n"); 1344 return -EINVAL; 1345 } 1346 1347 wiz->data = data; 1348 wiz->type = data->type; 1349 1350 child_node = of_get_child_by_name(node, "serdes"); 1351 if (!child_node) { 1352 dev_err(dev, "Failed to get SERDES child DT node\n"); 1353 return -ENODEV; 1354 } 1355 1356 ret = of_address_to_resource(child_node, 0, &res); 1357 if (ret) { 1358 dev_err(dev, "Failed to get memory resource\n"); 1359 goto err_addr_to_resource; 1360 } 1361 1362 base = devm_ioremap(dev, res.start, resource_size(&res)); 1363 if (!base) { 1364 ret = -ENOMEM; 1365 goto err_addr_to_resource; 1366 } 1367 1368 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); 1369 if (IS_ERR(regmap)) { 1370 dev_err(dev, "Failed to initialize regmap\n"); 1371 ret = PTR_ERR(regmap); 1372 goto err_addr_to_resource; 1373 } 1374 1375 wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm"); 1376 if (IS_ERR(wiz->scm_regmap)) { 1377 if (wiz->type == J7200_WIZ_10G) { 1378 dev_err(dev, "Couldn't get ti,scm regmap\n"); 1379 return -ENODEV; 1380 } 1381 1382 wiz->scm_regmap = NULL; 1383 } 1384 1385 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 1386 if (ret) { 1387 dev_err(dev, "Failed to read num-lanes property\n"); 1388 goto err_addr_to_resource; 1389 } 1390 1391 if (num_lanes > WIZ_MAX_LANES) { 1392 dev_err(dev, "Cannot support %d lanes\n", num_lanes); 1393 ret = -ENODEV; 1394 goto err_addr_to_resource; 1395 } 1396 1397 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", 1398 GPIOD_IN); 1399 if (IS_ERR(wiz->gpio_typec_dir)) { 1400 ret = PTR_ERR(wiz->gpio_typec_dir); 1401 if (ret != -EPROBE_DEFER) 1402 dev_err(dev, "Failed to request typec-dir gpio: %d\n", 1403 ret); 1404 goto err_addr_to_resource; 1405 } 1406 1407 if (wiz->gpio_typec_dir) { 1408 ret = of_property_read_u32(node, "typec-dir-debounce-ms", 1409 &wiz->typec_dir_delay); 1410 if (ret && ret != -EINVAL) { 1411 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1412 goto err_addr_to_resource; 1413 } 1414 1415 /* use min. debounce from Type-C spec if not provided in DT */ 1416 if (ret == -EINVAL) 1417 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; 1418 1419 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 1420 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 1421 ret = -EINVAL; 1422 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1423 goto err_addr_to_resource; 1424 } 1425 } 1426 1427 ret = wiz_get_lane_phy_types(dev, wiz); 1428 if (ret) 1429 return ret; 1430 1431 wiz->dev = dev; 1432 wiz->regmap = regmap; 1433 wiz->num_lanes = num_lanes; 1434 wiz->clk_mux_sel = data->clk_mux_sel; 1435 wiz->clk_div_sel = clk_div_sel; 1436 wiz->clk_div_sel_num = data->clk_div_sel_num; 1437 1438 platform_set_drvdata(pdev, wiz); 1439 1440 ret = wiz_regfield_init(wiz); 1441 if (ret) { 1442 dev_err(dev, "Failed to initialize regfields\n"); 1443 goto err_addr_to_resource; 1444 } 1445 1446 /* Enable supplemental Control override if available */ 1447 if (wiz->scm_regmap) 1448 regmap_field_write(wiz->sup_legacy_clk_override, 1); 1449 1450 phy_reset_dev = &wiz->wiz_phy_reset_dev; 1451 phy_reset_dev->dev = dev; 1452 phy_reset_dev->ops = &wiz_phy_reset_ops, 1453 phy_reset_dev->owner = THIS_MODULE, 1454 phy_reset_dev->of_node = node; 1455 /* Reset for each of the lane and one for the entire SERDES */ 1456 phy_reset_dev->nr_resets = num_lanes + 1; 1457 1458 ret = devm_reset_controller_register(dev, phy_reset_dev); 1459 if (ret < 0) { 1460 dev_warn(dev, "Failed to register reset controller\n"); 1461 goto err_addr_to_resource; 1462 } 1463 1464 pm_runtime_enable(dev); 1465 ret = pm_runtime_get_sync(dev); 1466 if (ret < 0) { 1467 dev_err(dev, "pm_runtime_get_sync failed\n"); 1468 goto err_get_sync; 1469 } 1470 1471 ret = wiz_clock_init(wiz, node); 1472 if (ret < 0) { 1473 dev_warn(dev, "Failed to initialize clocks\n"); 1474 goto err_get_sync; 1475 } 1476 1477 for (i = 0; i < wiz->num_lanes; i++) { 1478 regmap_field_read(wiz->p_enable[i], &val); 1479 if (val & (P_ENABLE | P_ENABLE_FORCE)) { 1480 already_configured = true; 1481 break; 1482 } 1483 } 1484 1485 if (!already_configured) { 1486 ret = wiz_init(wiz); 1487 if (ret) { 1488 dev_err(dev, "WIZ initialization failed\n"); 1489 goto err_wiz_init; 1490 } 1491 } 1492 1493 serdes_pdev = of_platform_device_create(child_node, NULL, dev); 1494 if (!serdes_pdev) { 1495 dev_WARN(dev, "Unable to create SERDES platform device\n"); 1496 ret = -ENOMEM; 1497 goto err_wiz_init; 1498 } 1499 wiz->serdes_pdev = serdes_pdev; 1500 1501 of_node_put(child_node); 1502 return 0; 1503 1504 err_wiz_init: 1505 wiz_clock_cleanup(wiz, node); 1506 1507 err_get_sync: 1508 pm_runtime_put(dev); 1509 pm_runtime_disable(dev); 1510 1511 err_addr_to_resource: 1512 of_node_put(child_node); 1513 1514 return ret; 1515 } 1516 1517 static int wiz_remove(struct platform_device *pdev) 1518 { 1519 struct device *dev = &pdev->dev; 1520 struct device_node *node = dev->of_node; 1521 struct platform_device *serdes_pdev; 1522 struct wiz *wiz; 1523 1524 wiz = dev_get_drvdata(dev); 1525 serdes_pdev = wiz->serdes_pdev; 1526 1527 of_platform_device_destroy(&serdes_pdev->dev, NULL); 1528 wiz_clock_cleanup(wiz, node); 1529 pm_runtime_put(dev); 1530 pm_runtime_disable(dev); 1531 1532 return 0; 1533 } 1534 1535 static struct platform_driver wiz_driver = { 1536 .probe = wiz_probe, 1537 .remove = wiz_remove, 1538 .driver = { 1539 .name = "wiz", 1540 .of_match_table = wiz_id_table, 1541 }, 1542 }; 1543 module_platform_driver(wiz_driver); 1544 1545 MODULE_AUTHOR("Texas Instruments Inc."); 1546 MODULE_DESCRIPTION("TI J721E WIZ driver"); 1547 MODULE_LICENSE("GPL v2"); 1548