1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Wrapper driver for SERDES used in J721E 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-ti.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/gpio.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/mux/consumer.h> 20 #include <linux/of_address.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/reset-controller.h> 26 27 #define REF_CLK_19_2MHZ 19200000 28 #define REF_CLK_25MHZ 25000000 29 #define REF_CLK_100MHZ 100000000 30 #define REF_CLK_156_25MHZ 156250000 31 32 /* SCM offsets */ 33 #define SERDES_SUP_CTRL 0x4400 34 35 /* SERDES offsets */ 36 #define WIZ_SERDES_CTRL 0x404 37 #define WIZ_SERDES_TOP_CTRL 0x408 38 #define WIZ_SERDES_RST 0x40c 39 #define WIZ_SERDES_TYPEC 0x410 40 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) 41 #define WIZ_LANEDIV(n) (0x484 + (0x40 * (n))) 42 43 #define WIZ_MAX_INPUT_CLOCKS 4 44 /* To include mux clocks, divider clocks and gate clocks */ 45 #define WIZ_MAX_OUTPUT_CLOCKS 32 46 47 #define WIZ_MAX_LANES 4 48 #define WIZ_MUX_NUM_CLOCKS 3 49 #define WIZ_DIV_NUM_CLOCKS_16G 2 50 #define WIZ_DIV_NUM_CLOCKS_10G 1 51 52 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) 53 54 enum wiz_lane_standard_mode { 55 LANE_MODE_GEN1, 56 LANE_MODE_GEN2, 57 LANE_MODE_GEN3, 58 LANE_MODE_GEN4, 59 }; 60 61 enum wiz_refclk_mux_sel { 62 PLL0_REFCLK, 63 PLL1_REFCLK, 64 REFCLK_DIG, 65 }; 66 67 enum wiz_refclk_div_sel { 68 CMN_REFCLK_DIG_DIV, 69 CMN_REFCLK1_DIG_DIV, 70 }; 71 72 enum wiz_clock_input { 73 WIZ_CORE_REFCLK, 74 WIZ_EXT_REFCLK, 75 WIZ_CORE_REFCLK1, 76 WIZ_EXT_REFCLK1, 77 }; 78 79 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); 80 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); 81 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); 82 static const struct reg_field pll1_refclk_mux_sel = 83 REG_FIELD(WIZ_SERDES_RST, 29, 29); 84 static const struct reg_field pll1_refclk_mux_sel_2 = 85 REG_FIELD(WIZ_SERDES_RST, 22, 23); 86 static const struct reg_field pll0_refclk_mux_sel = 87 REG_FIELD(WIZ_SERDES_RST, 28, 28); 88 static const struct reg_field pll0_refclk_mux_sel_2 = 89 REG_FIELD(WIZ_SERDES_RST, 28, 29); 90 static const struct reg_field refclk_dig_sel_16g = 91 REG_FIELD(WIZ_SERDES_RST, 24, 25); 92 static const struct reg_field refclk_dig_sel_10g = 93 REG_FIELD(WIZ_SERDES_RST, 24, 24); 94 static const struct reg_field pma_cmn_refclk_int_mode = 95 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 96 static const struct reg_field pma_cmn_refclk1_int_mode = 97 REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21); 98 static const struct reg_field pma_cmn_refclk_mode = 99 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 100 static const struct reg_field pma_cmn_refclk_dig_div = 101 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); 102 static const struct reg_field pma_cmn_refclk1_dig_div = 103 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); 104 105 static const struct reg_field sup_pll0_refclk_mux_sel = 106 REG_FIELD(SERDES_SUP_CTRL, 0, 1); 107 static const struct reg_field sup_pll1_refclk_mux_sel = 108 REG_FIELD(SERDES_SUP_CTRL, 2, 3); 109 static const struct reg_field sup_pma_cmn_refclk1_int_mode = 110 REG_FIELD(SERDES_SUP_CTRL, 4, 5); 111 static const struct reg_field sup_refclk_dig_sel_10g = 112 REG_FIELD(SERDES_SUP_CTRL, 6, 7); 113 static const struct reg_field sup_legacy_clk_override = 114 REG_FIELD(SERDES_SUP_CTRL, 8, 8); 115 116 static const char * const output_clk_names[] = { 117 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk", 118 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk", 119 [TI_WIZ_REFCLK_DIG] = "refclk-dig", 120 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk", 121 }; 122 123 static const struct reg_field p_enable[WIZ_MAX_LANES] = { 124 REG_FIELD(WIZ_LANECTL(0), 30, 31), 125 REG_FIELD(WIZ_LANECTL(1), 30, 31), 126 REG_FIELD(WIZ_LANECTL(2), 30, 31), 127 REG_FIELD(WIZ_LANECTL(3), 30, 31), 128 }; 129 130 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; 131 132 static const struct reg_field p_align[WIZ_MAX_LANES] = { 133 REG_FIELD(WIZ_LANECTL(0), 29, 29), 134 REG_FIELD(WIZ_LANECTL(1), 29, 29), 135 REG_FIELD(WIZ_LANECTL(2), 29, 29), 136 REG_FIELD(WIZ_LANECTL(3), 29, 29), 137 }; 138 139 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { 140 REG_FIELD(WIZ_LANECTL(0), 28, 28), 141 REG_FIELD(WIZ_LANECTL(1), 28, 28), 142 REG_FIELD(WIZ_LANECTL(2), 28, 28), 143 REG_FIELD(WIZ_LANECTL(3), 28, 28), 144 }; 145 146 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { 147 REG_FIELD(WIZ_LANECTL(0), 24, 25), 148 REG_FIELD(WIZ_LANECTL(1), 24, 25), 149 REG_FIELD(WIZ_LANECTL(2), 24, 25), 150 REG_FIELD(WIZ_LANECTL(3), 24, 25), 151 }; 152 153 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { 154 REG_FIELD(WIZ_LANECTL(0), 22, 23), 155 REG_FIELD(WIZ_LANECTL(1), 22, 23), 156 REG_FIELD(WIZ_LANECTL(2), 22, 23), 157 REG_FIELD(WIZ_LANECTL(3), 22, 23), 158 }; 159 160 static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = { 161 REG_FIELD(WIZ_LANECTL(0), 20, 21), 162 REG_FIELD(WIZ_LANECTL(1), 20, 21), 163 REG_FIELD(WIZ_LANECTL(2), 20, 21), 164 REG_FIELD(WIZ_LANECTL(3), 20, 21), 165 }; 166 167 static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = { 168 REG_FIELD(WIZ_LANECTL(0), 6, 7), 169 REG_FIELD(WIZ_LANECTL(1), 6, 7), 170 REG_FIELD(WIZ_LANECTL(2), 6, 7), 171 REG_FIELD(WIZ_LANECTL(3), 6, 7), 172 }; 173 174 static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = { 175 REG_FIELD(WIZ_LANECTL(0), 18, 19), 176 REG_FIELD(WIZ_LANECTL(1), 18, 19), 177 REG_FIELD(WIZ_LANECTL(2), 18, 19), 178 REG_FIELD(WIZ_LANECTL(3), 18, 19), 179 }; 180 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { 181 REG_FIELD(WIZ_LANEDIV(0), 16, 22), 182 REG_FIELD(WIZ_LANEDIV(1), 16, 22), 183 REG_FIELD(WIZ_LANEDIV(2), 16, 22), 184 REG_FIELD(WIZ_LANEDIV(3), 16, 22), 185 }; 186 187 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { 188 REG_FIELD(WIZ_LANEDIV(0), 0, 8), 189 REG_FIELD(WIZ_LANEDIV(1), 0, 8), 190 REG_FIELD(WIZ_LANEDIV(2), 0, 8), 191 REG_FIELD(WIZ_LANEDIV(3), 0, 8), 192 }; 193 194 static const struct reg_field typec_ln10_swap = 195 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 196 197 struct wiz_clk_mux { 198 struct clk_hw hw; 199 struct regmap_field *field; 200 const u32 *table; 201 struct clk_init_data clk_data; 202 }; 203 204 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) 205 206 struct wiz_clk_divider { 207 struct clk_hw hw; 208 struct regmap_field *field; 209 const struct clk_div_table *table; 210 struct clk_init_data clk_data; 211 }; 212 213 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) 214 215 struct wiz_clk_mux_sel { 216 u32 table[WIZ_MAX_INPUT_CLOCKS]; 217 const char *node_name; 218 u32 num_parents; 219 u32 parents[WIZ_MAX_INPUT_CLOCKS]; 220 }; 221 222 struct wiz_clk_div_sel { 223 const struct clk_div_table *table; 224 const char *node_name; 225 }; 226 227 struct wiz_phy_en_refclk { 228 struct clk_hw hw; 229 struct regmap_field *phy_en_refclk; 230 struct clk_init_data clk_data; 231 }; 232 233 #define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw) 234 235 static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = { 236 { 237 /* 238 * Mux value to be configured for each of the input clocks 239 * in the order populated in device tree 240 */ 241 .table = { 1, 0 }, 242 .node_name = "pll0-refclk", 243 }, 244 { 245 .table = { 1, 0 }, 246 .node_name = "pll1-refclk", 247 }, 248 { 249 .table = { 1, 3, 0, 2 }, 250 .node_name = "refclk-dig", 251 }, 252 }; 253 254 static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 255 { 256 /* 257 * Mux value to be configured for each of the input clocks 258 * in the order populated in device tree 259 */ 260 .num_parents = 2, 261 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 262 .table = { 1, 0 }, 263 .node_name = "pll0-refclk", 264 }, 265 { 266 .num_parents = 2, 267 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 268 .table = { 1, 0 }, 269 .node_name = "pll1-refclk", 270 }, 271 { 272 .num_parents = 2, 273 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 274 .table = { 1, 0 }, 275 .node_name = "refclk-dig", 276 }, 277 }; 278 279 static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = { 280 { 281 .num_parents = 3, 282 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 283 .table = { 2, 3, 0 }, 284 .node_name = "pll0-refclk", 285 }, 286 { 287 .num_parents = 3, 288 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 289 .table = { 2, 3, 0 }, 290 .node_name = "pll1-refclk", 291 }, 292 { 293 .num_parents = 3, 294 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 295 .table = { 2, 3, 0 }, 296 .node_name = "refclk-dig", 297 }, 298 }; 299 300 static const struct clk_div_table clk_div_table[] = { 301 { .val = 0, .div = 1, }, 302 { .val = 1, .div = 2, }, 303 { .val = 2, .div = 4, }, 304 { .val = 3, .div = 8, }, 305 { /* sentinel */ }, 306 }; 307 308 static const struct wiz_clk_div_sel clk_div_sel[] = { 309 { 310 .table = clk_div_table, 311 .node_name = "cmn-refclk-dig-div", 312 }, 313 { 314 .table = clk_div_table, 315 .node_name = "cmn-refclk1-dig-div", 316 }, 317 }; 318 319 enum wiz_type { 320 J721E_WIZ_16G, 321 J721E_WIZ_10G, /* Also for J7200 SR1.0 */ 322 AM64_WIZ_10G, 323 J7200_WIZ_10G, /* J7200 SR2.0 */ 324 J784S4_WIZ_10G, 325 }; 326 327 struct wiz_data { 328 enum wiz_type type; 329 const struct reg_field *pll0_refclk_mux_sel; 330 const struct reg_field *pll1_refclk_mux_sel; 331 const struct reg_field *refclk_dig_sel; 332 const struct reg_field *pma_cmn_refclk1_dig_div; 333 const struct reg_field *pma_cmn_refclk1_int_mode; 334 const struct wiz_clk_mux_sel *clk_mux_sel; 335 unsigned int clk_div_sel_num; 336 }; 337 338 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ 339 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 340 341 struct wiz { 342 struct regmap *regmap; 343 struct regmap *scm_regmap; 344 enum wiz_type type; 345 const struct wiz_clk_mux_sel *clk_mux_sel; 346 const struct wiz_clk_div_sel *clk_div_sel; 347 unsigned int clk_div_sel_num; 348 struct regmap_field *por_en; 349 struct regmap_field *phy_reset_n; 350 struct regmap_field *phy_en_refclk; 351 struct regmap_field *p_enable[WIZ_MAX_LANES]; 352 struct regmap_field *p_align[WIZ_MAX_LANES]; 353 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; 354 struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; 355 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; 356 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; 357 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; 358 struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES]; 359 struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; 360 struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; 361 struct regmap_field *pma_cmn_refclk_int_mode; 362 struct regmap_field *pma_cmn_refclk1_int_mode; 363 struct regmap_field *pma_cmn_refclk_mode; 364 struct regmap_field *pma_cmn_refclk_dig_div; 365 struct regmap_field *pma_cmn_refclk1_dig_div; 366 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; 367 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; 368 struct regmap_field *typec_ln10_swap; 369 struct regmap_field *sup_legacy_clk_override; 370 371 struct device *dev; 372 u32 num_lanes; 373 struct platform_device *serdes_pdev; 374 struct reset_controller_dev wiz_phy_reset_dev; 375 struct gpio_desc *gpio_typec_dir; 376 int typec_dir_delay; 377 u32 lane_phy_type[WIZ_MAX_LANES]; 378 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; 379 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS]; 380 struct clk_onecell_data clk_data; 381 const struct wiz_data *data; 382 }; 383 384 static int wiz_reset(struct wiz *wiz) 385 { 386 int ret; 387 388 ret = regmap_field_write(wiz->por_en, 0x1); 389 if (ret) 390 return ret; 391 392 mdelay(1); 393 394 ret = regmap_field_write(wiz->por_en, 0x0); 395 if (ret) 396 return ret; 397 398 return 0; 399 } 400 401 static int wiz_p_mac_div_sel(struct wiz *wiz) 402 { 403 u32 num_lanes = wiz->num_lanes; 404 int ret; 405 int i; 406 407 for (i = 0; i < num_lanes; i++) { 408 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || 409 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII || 410 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 411 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); 412 if (ret) 413 return ret; 414 415 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); 416 if (ret) 417 return ret; 418 } 419 } 420 421 return 0; 422 } 423 424 static int wiz_mode_select(struct wiz *wiz) 425 { 426 u32 num_lanes = wiz->num_lanes; 427 enum wiz_lane_standard_mode mode; 428 int ret; 429 int i; 430 431 for (i = 0; i < num_lanes; i++) { 432 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) 433 mode = LANE_MODE_GEN1; 434 else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) 435 mode = LANE_MODE_GEN2; 436 else 437 continue; 438 439 if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 440 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); 441 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); 442 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3); 443 mode = LANE_MODE_GEN1; 444 } 445 446 ret = regmap_field_write(wiz->p_standard_mode[i], mode); 447 if (ret) 448 return ret; 449 } 450 451 return 0; 452 } 453 454 static int wiz_init_raw_interface(struct wiz *wiz, bool enable) 455 { 456 u32 num_lanes = wiz->num_lanes; 457 int i; 458 int ret; 459 460 for (i = 0; i < num_lanes; i++) { 461 ret = regmap_field_write(wiz->p_align[i], enable); 462 if (ret) 463 return ret; 464 465 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); 466 if (ret) 467 return ret; 468 } 469 470 return 0; 471 } 472 473 static int wiz_init(struct wiz *wiz) 474 { 475 struct device *dev = wiz->dev; 476 int ret; 477 478 ret = wiz_reset(wiz); 479 if (ret) { 480 dev_err(dev, "WIZ reset failed\n"); 481 return ret; 482 } 483 484 ret = wiz_mode_select(wiz); 485 if (ret) { 486 dev_err(dev, "WIZ mode select failed\n"); 487 return ret; 488 } 489 490 ret = wiz_p_mac_div_sel(wiz); 491 if (ret) { 492 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); 493 return ret; 494 } 495 496 ret = wiz_init_raw_interface(wiz, true); 497 if (ret) { 498 dev_err(dev, "WIZ interface initialization failed\n"); 499 return ret; 500 } 501 502 return 0; 503 } 504 505 static int wiz_regfield_init(struct wiz *wiz) 506 { 507 struct regmap *regmap = wiz->regmap; 508 struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */ 509 int num_lanes = wiz->num_lanes; 510 struct device *dev = wiz->dev; 511 const struct wiz_data *data = wiz->data; 512 int i; 513 514 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); 515 if (IS_ERR(wiz->por_en)) { 516 dev_err(dev, "POR_EN reg field init failed\n"); 517 return PTR_ERR(wiz->por_en); 518 } 519 520 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, 521 phy_reset_n); 522 if (IS_ERR(wiz->phy_reset_n)) { 523 dev_err(dev, "PHY_RESET_N reg field init failed\n"); 524 return PTR_ERR(wiz->phy_reset_n); 525 } 526 527 wiz->pma_cmn_refclk_int_mode = 528 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); 529 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { 530 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); 531 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); 532 } 533 534 wiz->pma_cmn_refclk_mode = 535 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); 536 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { 537 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); 538 return PTR_ERR(wiz->pma_cmn_refclk_mode); 539 } 540 541 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] = 542 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div); 543 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) { 544 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); 545 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); 546 } 547 548 if (data->pma_cmn_refclk1_dig_div) { 549 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = 550 devm_regmap_field_alloc(dev, regmap, 551 *data->pma_cmn_refclk1_dig_div); 552 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { 553 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); 554 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); 555 } 556 } 557 558 if (wiz->scm_regmap) { 559 scm_regmap = wiz->scm_regmap; 560 wiz->sup_legacy_clk_override = 561 devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override); 562 if (IS_ERR(wiz->sup_legacy_clk_override)) { 563 dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n"); 564 return PTR_ERR(wiz->sup_legacy_clk_override); 565 } 566 } 567 568 wiz->mux_sel_field[PLL0_REFCLK] = 569 devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel); 570 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { 571 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); 572 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); 573 } 574 575 wiz->mux_sel_field[PLL1_REFCLK] = 576 devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel); 577 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { 578 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); 579 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); 580 } 581 582 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap, 583 *data->refclk_dig_sel); 584 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { 585 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); 586 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); 587 } 588 589 if (data->pma_cmn_refclk1_int_mode) { 590 wiz->pma_cmn_refclk1_int_mode = 591 devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode); 592 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) { 593 dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n"); 594 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode); 595 } 596 } 597 598 for (i = 0; i < num_lanes; i++) { 599 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, 600 p_enable[i]); 601 if (IS_ERR(wiz->p_enable[i])) { 602 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 603 return PTR_ERR(wiz->p_enable[i]); 604 } 605 606 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, 607 p_align[i]); 608 if (IS_ERR(wiz->p_align[i])) { 609 dev_err(dev, "P%d_ALIGN reg field init failed\n", i); 610 return PTR_ERR(wiz->p_align[i]); 611 } 612 613 wiz->p_raw_auto_start[i] = 614 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); 615 if (IS_ERR(wiz->p_raw_auto_start[i])) { 616 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", 617 i); 618 return PTR_ERR(wiz->p_raw_auto_start[i]); 619 } 620 621 wiz->p_standard_mode[i] = 622 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); 623 if (IS_ERR(wiz->p_standard_mode[i])) { 624 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", 625 i); 626 return PTR_ERR(wiz->p_standard_mode[i]); 627 } 628 629 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); 630 if (IS_ERR(wiz->p0_fullrt_div[i])) { 631 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i); 632 return PTR_ERR(wiz->p0_fullrt_div[i]); 633 } 634 635 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]); 636 if (IS_ERR(wiz->p0_mac_src_sel[i])) { 637 dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i); 638 return PTR_ERR(wiz->p0_mac_src_sel[i]); 639 } 640 641 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]); 642 if (IS_ERR(wiz->p0_rxfclk_sel[i])) { 643 dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i); 644 return PTR_ERR(wiz->p0_rxfclk_sel[i]); 645 } 646 647 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]); 648 if (IS_ERR(wiz->p0_refclk_sel[i])) { 649 dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i); 650 return PTR_ERR(wiz->p0_refclk_sel[i]); 651 } 652 653 wiz->p_mac_div_sel0[i] = 654 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); 655 if (IS_ERR(wiz->p_mac_div_sel0[i])) { 656 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n", 657 i); 658 return PTR_ERR(wiz->p_mac_div_sel0[i]); 659 } 660 661 wiz->p_mac_div_sel1[i] = 662 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]); 663 if (IS_ERR(wiz->p_mac_div_sel1[i])) { 664 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n", 665 i); 666 return PTR_ERR(wiz->p_mac_div_sel1[i]); 667 } 668 } 669 670 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, 671 typec_ln10_swap); 672 if (IS_ERR(wiz->typec_ln10_swap)) { 673 dev_err(dev, "LN10_SWAP reg field init failed\n"); 674 return PTR_ERR(wiz->typec_ln10_swap); 675 } 676 677 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); 678 if (IS_ERR(wiz->phy_en_refclk)) { 679 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n"); 680 return PTR_ERR(wiz->phy_en_refclk); 681 } 682 683 return 0; 684 } 685 686 static int wiz_phy_en_refclk_enable(struct clk_hw *hw) 687 { 688 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 689 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 690 691 regmap_field_write(phy_en_refclk, 1); 692 693 return 0; 694 } 695 696 static void wiz_phy_en_refclk_disable(struct clk_hw *hw) 697 { 698 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 699 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 700 701 regmap_field_write(phy_en_refclk, 0); 702 } 703 704 static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw) 705 { 706 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 707 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 708 int val; 709 710 regmap_field_read(phy_en_refclk, &val); 711 712 return !!val; 713 } 714 715 static const struct clk_ops wiz_phy_en_refclk_ops = { 716 .enable = wiz_phy_en_refclk_enable, 717 .disable = wiz_phy_en_refclk_disable, 718 .is_enabled = wiz_phy_en_refclk_is_enabled, 719 }; 720 721 static int wiz_phy_en_refclk_register(struct wiz *wiz) 722 { 723 struct wiz_phy_en_refclk *wiz_phy_en_refclk; 724 struct device *dev = wiz->dev; 725 struct clk_init_data *init; 726 struct clk *clk; 727 char *clk_name; 728 unsigned int sz; 729 730 wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL); 731 if (!wiz_phy_en_refclk) 732 return -ENOMEM; 733 734 init = &wiz_phy_en_refclk->clk_data; 735 736 init->ops = &wiz_phy_en_refclk_ops; 737 init->flags = 0; 738 739 sz = strlen(dev_name(dev)) + strlen(output_clk_names[TI_WIZ_PHY_EN_REFCLK]) + 2; 740 741 clk_name = kzalloc(sz, GFP_KERNEL); 742 if (!clk_name) 743 return -ENOMEM; 744 745 snprintf(clk_name, sz, "%s_%s", dev_name(dev), output_clk_names[TI_WIZ_PHY_EN_REFCLK]); 746 init->name = clk_name; 747 748 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; 749 wiz_phy_en_refclk->hw.init = init; 750 751 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); 752 753 kfree(clk_name); 754 755 if (IS_ERR(clk)) 756 return PTR_ERR(clk); 757 758 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk; 759 760 return 0; 761 } 762 763 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) 764 { 765 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 766 struct regmap_field *field = mux->field; 767 unsigned int val; 768 769 regmap_field_read(field, &val); 770 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val); 771 } 772 773 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) 774 { 775 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 776 struct regmap_field *field = mux->field; 777 int val; 778 779 val = mux->table[index]; 780 return regmap_field_write(field, val); 781 } 782 783 static const struct clk_ops wiz_clk_mux_ops = { 784 .set_parent = wiz_clk_mux_set_parent, 785 .get_parent = wiz_clk_mux_get_parent, 786 }; 787 788 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field, 789 const struct wiz_clk_mux_sel *mux_sel, int clk_index) 790 { 791 struct device *dev = wiz->dev; 792 struct clk_init_data *init; 793 const char **parent_names; 794 unsigned int num_parents; 795 struct wiz_clk_mux *mux; 796 char clk_name[100]; 797 struct clk *clk; 798 int ret = 0, i; 799 800 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 801 if (!mux) 802 return -ENOMEM; 803 804 num_parents = mux_sel->num_parents; 805 806 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); 807 if (!parent_names) 808 return -ENOMEM; 809 810 for (i = 0; i < num_parents; i++) { 811 clk = wiz->input_clks[mux_sel->parents[i]]; 812 if (IS_ERR_OR_NULL(clk)) { 813 dev_err(dev, "Failed to get parent clk for %s\n", 814 output_clk_names[clk_index]); 815 ret = -EINVAL; 816 goto err; 817 } 818 parent_names[i] = __clk_get_name(clk); 819 } 820 821 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]); 822 823 init = &mux->clk_data; 824 825 init->ops = &wiz_clk_mux_ops; 826 init->flags = CLK_SET_RATE_NO_REPARENT; 827 init->parent_names = parent_names; 828 init->num_parents = num_parents; 829 init->name = clk_name; 830 831 mux->field = field; 832 mux->table = mux_sel->table; 833 mux->hw.init = init; 834 835 clk = devm_clk_register(dev, &mux->hw); 836 if (IS_ERR(clk)) { 837 ret = PTR_ERR(clk); 838 goto err; 839 } 840 841 wiz->output_clks[clk_index] = clk; 842 843 err: 844 kfree(parent_names); 845 846 return ret; 847 } 848 849 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node, 850 struct regmap_field *field, const u32 *table) 851 { 852 struct device *dev = wiz->dev; 853 struct clk_init_data *init; 854 const char **parent_names; 855 unsigned int num_parents; 856 struct wiz_clk_mux *mux; 857 char clk_name[100]; 858 struct clk *clk; 859 int ret; 860 861 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 862 if (!mux) 863 return -ENOMEM; 864 865 num_parents = of_clk_get_parent_count(node); 866 if (num_parents < 2) { 867 dev_err(dev, "SERDES clock must have parents\n"); 868 return -EINVAL; 869 } 870 871 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 872 GFP_KERNEL); 873 if (!parent_names) 874 return -ENOMEM; 875 876 of_clk_parent_fill(node, parent_names, num_parents); 877 878 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 879 node->name); 880 881 init = &mux->clk_data; 882 883 init->ops = &wiz_clk_mux_ops; 884 init->flags = CLK_SET_RATE_NO_REPARENT; 885 init->parent_names = parent_names; 886 init->num_parents = num_parents; 887 init->name = clk_name; 888 889 mux->field = field; 890 mux->table = table; 891 mux->hw.init = init; 892 893 clk = devm_clk_register(dev, &mux->hw); 894 if (IS_ERR(clk)) 895 return PTR_ERR(clk); 896 897 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 898 if (ret) 899 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 900 901 return ret; 902 } 903 904 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, 905 unsigned long parent_rate) 906 { 907 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 908 struct regmap_field *field = div->field; 909 int val; 910 911 regmap_field_read(field, &val); 912 913 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); 914 } 915 916 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 917 unsigned long *prate) 918 { 919 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 920 921 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); 922 } 923 924 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 925 unsigned long parent_rate) 926 { 927 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 928 struct regmap_field *field = div->field; 929 int val; 930 931 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); 932 if (val < 0) 933 return val; 934 935 return regmap_field_write(field, val); 936 } 937 938 static const struct clk_ops wiz_clk_div_ops = { 939 .recalc_rate = wiz_clk_div_recalc_rate, 940 .round_rate = wiz_clk_div_round_rate, 941 .set_rate = wiz_clk_div_set_rate, 942 }; 943 944 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, 945 struct regmap_field *field, 946 const struct clk_div_table *table) 947 { 948 struct device *dev = wiz->dev; 949 struct wiz_clk_divider *div; 950 struct clk_init_data *init; 951 const char **parent_names; 952 char clk_name[100]; 953 struct clk *clk; 954 int ret; 955 956 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 957 if (!div) 958 return -ENOMEM; 959 960 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 961 node->name); 962 963 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 964 if (!parent_names) 965 return -ENOMEM; 966 967 of_clk_parent_fill(node, parent_names, 1); 968 969 init = &div->clk_data; 970 971 init->ops = &wiz_clk_div_ops; 972 init->flags = 0; 973 init->parent_names = parent_names; 974 init->num_parents = 1; 975 init->name = clk_name; 976 977 div->field = field; 978 div->table = table; 979 div->hw.init = init; 980 981 clk = devm_clk_register(dev, &div->hw); 982 if (IS_ERR(clk)) 983 return PTR_ERR(clk); 984 985 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 986 if (ret) 987 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 988 989 return ret; 990 } 991 992 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) 993 { 994 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 995 struct device *dev = wiz->dev; 996 struct device_node *clk_node; 997 int i; 998 999 switch (wiz->type) { 1000 case AM64_WIZ_10G: 1001 case J7200_WIZ_10G: 1002 case J784S4_WIZ_10G: 1003 of_clk_del_provider(dev->of_node); 1004 return; 1005 default: 1006 break; 1007 } 1008 1009 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 1010 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); 1011 of_clk_del_provider(clk_node); 1012 of_node_put(clk_node); 1013 } 1014 1015 for (i = 0; i < wiz->clk_div_sel_num; i++) { 1016 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name); 1017 of_clk_del_provider(clk_node); 1018 of_node_put(clk_node); 1019 } 1020 1021 of_clk_del_provider(wiz->dev->of_node); 1022 } 1023 1024 static int wiz_clock_register(struct wiz *wiz) 1025 { 1026 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1027 struct device *dev = wiz->dev; 1028 struct device_node *node = dev->of_node; 1029 int clk_index; 1030 int ret; 1031 int i; 1032 1033 clk_index = TI_WIZ_PLL0_REFCLK; 1034 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { 1035 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); 1036 if (ret) { 1037 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]); 1038 return ret; 1039 } 1040 } 1041 1042 ret = wiz_phy_en_refclk_register(wiz); 1043 if (ret) { 1044 dev_err(dev, "Failed to add phy-en-refclk\n"); 1045 return ret; 1046 } 1047 1048 wiz->clk_data.clks = wiz->output_clks; 1049 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS; 1050 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data); 1051 if (ret) 1052 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 1053 1054 return ret; 1055 } 1056 1057 static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 1058 { 1059 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1060 struct device *dev = wiz->dev; 1061 struct device_node *clk_node; 1062 const char *node_name; 1063 unsigned long rate; 1064 struct clk *clk; 1065 int ret; 1066 int i; 1067 1068 clk = devm_clk_get(dev, "core_ref_clk"); 1069 if (IS_ERR(clk)) { 1070 dev_err(dev, "core_ref_clk clock not found\n"); 1071 ret = PTR_ERR(clk); 1072 return ret; 1073 } 1074 wiz->input_clks[WIZ_CORE_REFCLK] = clk; 1075 1076 rate = clk_get_rate(clk); 1077 if (rate >= 100000000) 1078 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 1079 else 1080 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 1081 1082 switch (wiz->type) { 1083 case AM64_WIZ_10G: 1084 case J7200_WIZ_10G: 1085 switch (rate) { 1086 case REF_CLK_100MHZ: 1087 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2); 1088 break; 1089 case REF_CLK_156_25MHZ: 1090 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3); 1091 break; 1092 default: 1093 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0); 1094 break; 1095 } 1096 break; 1097 default: 1098 break; 1099 } 1100 1101 if (wiz->data->pma_cmn_refclk1_int_mode) { 1102 clk = devm_clk_get(dev, "core_ref1_clk"); 1103 if (IS_ERR(clk)) { 1104 dev_err(dev, "core_ref1_clk clock not found\n"); 1105 ret = PTR_ERR(clk); 1106 return ret; 1107 } 1108 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; 1109 1110 rate = clk_get_rate(clk); 1111 if (rate >= 100000000) 1112 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); 1113 else 1114 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); 1115 } 1116 1117 clk = devm_clk_get(dev, "ext_ref_clk"); 1118 if (IS_ERR(clk)) { 1119 dev_err(dev, "ext_ref_clk clock not found\n"); 1120 ret = PTR_ERR(clk); 1121 return ret; 1122 } 1123 wiz->input_clks[WIZ_EXT_REFCLK] = clk; 1124 1125 rate = clk_get_rate(clk); 1126 if (rate >= 100000000) 1127 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 1128 else 1129 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 1130 1131 switch (wiz->type) { 1132 case AM64_WIZ_10G: 1133 case J7200_WIZ_10G: 1134 case J784S4_WIZ_10G: 1135 ret = wiz_clock_register(wiz); 1136 if (ret) 1137 dev_err(dev, "Failed to register wiz clocks\n"); 1138 return ret; 1139 default: 1140 break; 1141 } 1142 1143 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 1144 node_name = clk_mux_sel[i].node_name; 1145 clk_node = of_get_child_by_name(node, node_name); 1146 if (!clk_node) { 1147 dev_err(dev, "Unable to get %s node\n", node_name); 1148 ret = -EINVAL; 1149 goto err; 1150 } 1151 1152 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i], 1153 clk_mux_sel[i].table); 1154 if (ret) { 1155 dev_err(dev, "Failed to register %s clock\n", 1156 node_name); 1157 of_node_put(clk_node); 1158 goto err; 1159 } 1160 1161 of_node_put(clk_node); 1162 } 1163 1164 for (i = 0; i < wiz->clk_div_sel_num; i++) { 1165 node_name = clk_div_sel[i].node_name; 1166 clk_node = of_get_child_by_name(node, node_name); 1167 if (!clk_node) { 1168 dev_err(dev, "Unable to get %s node\n", node_name); 1169 ret = -EINVAL; 1170 goto err; 1171 } 1172 1173 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i], 1174 clk_div_sel[i].table); 1175 if (ret) { 1176 dev_err(dev, "Failed to register %s clock\n", 1177 node_name); 1178 of_node_put(clk_node); 1179 goto err; 1180 } 1181 1182 of_node_put(clk_node); 1183 } 1184 1185 return 0; 1186 err: 1187 wiz_clock_cleanup(wiz, node); 1188 1189 return ret; 1190 } 1191 1192 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, 1193 unsigned long id) 1194 { 1195 struct device *dev = rcdev->dev; 1196 struct wiz *wiz = dev_get_drvdata(dev); 1197 int ret = 0; 1198 1199 if (id == 0) { 1200 ret = regmap_field_write(wiz->phy_reset_n, false); 1201 return ret; 1202 } 1203 1204 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); 1205 return ret; 1206 } 1207 1208 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) 1209 { 1210 switch (wiz->type) { 1211 case AM64_WIZ_10G: 1212 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) 1213 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); 1214 break; 1215 case J721E_WIZ_10G: 1216 case J7200_WIZ_10G: 1217 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) 1218 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); 1219 break; 1220 default: 1221 return 0; 1222 } 1223 return 0; 1224 } 1225 1226 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, 1227 unsigned long id) 1228 { 1229 struct device *dev = rcdev->dev; 1230 struct wiz *wiz = dev_get_drvdata(dev); 1231 int ret; 1232 1233 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ 1234 if (id == 0 && wiz->gpio_typec_dir) { 1235 if (wiz->typec_dir_delay) 1236 msleep_interruptible(wiz->typec_dir_delay); 1237 1238 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) 1239 regmap_field_write(wiz->typec_ln10_swap, 1); 1240 else 1241 regmap_field_write(wiz->typec_ln10_swap, 0); 1242 } 1243 1244 if (id == 0) { 1245 ret = regmap_field_write(wiz->phy_reset_n, true); 1246 return ret; 1247 } 1248 1249 ret = wiz_phy_fullrt_div(wiz, id - 1); 1250 if (ret) 1251 return ret; 1252 1253 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) 1254 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); 1255 else 1256 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); 1257 1258 return ret; 1259 } 1260 1261 static const struct reset_control_ops wiz_phy_reset_ops = { 1262 .assert = wiz_phy_reset_assert, 1263 .deassert = wiz_phy_reset_deassert, 1264 }; 1265 1266 static const struct regmap_config wiz_regmap_config = { 1267 .reg_bits = 32, 1268 .val_bits = 32, 1269 .reg_stride = 4, 1270 .fast_io = true, 1271 }; 1272 1273 static struct wiz_data j721e_16g_data = { 1274 .type = J721E_WIZ_16G, 1275 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1276 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1277 .refclk_dig_sel = &refclk_dig_sel_16g, 1278 .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div, 1279 .clk_mux_sel = clk_mux_sel_16g, 1280 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G, 1281 }; 1282 1283 static struct wiz_data j721e_10g_data = { 1284 .type = J721E_WIZ_10G, 1285 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1286 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1287 .refclk_dig_sel = &refclk_dig_sel_10g, 1288 .clk_mux_sel = clk_mux_sel_10g, 1289 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1290 }; 1291 1292 static struct wiz_data am64_10g_data = { 1293 .type = AM64_WIZ_10G, 1294 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1295 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1296 .refclk_dig_sel = &refclk_dig_sel_10g, 1297 .clk_mux_sel = clk_mux_sel_10g, 1298 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1299 }; 1300 1301 static struct wiz_data j7200_pg2_10g_data = { 1302 .type = J7200_WIZ_10G, 1303 .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel, 1304 .pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel, 1305 .refclk_dig_sel = &sup_refclk_dig_sel_10g, 1306 .pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode, 1307 .clk_mux_sel = clk_mux_sel_10g_2_refclk, 1308 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1309 }; 1310 1311 static struct wiz_data j784s4_10g_data = { 1312 .type = J784S4_WIZ_10G, 1313 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2, 1314 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2, 1315 .refclk_dig_sel = &refclk_dig_sel_16g, 1316 .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode, 1317 .clk_mux_sel = clk_mux_sel_10g_2_refclk, 1318 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1319 }; 1320 1321 static const struct of_device_id wiz_id_table[] = { 1322 { 1323 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, 1324 }, 1325 { 1326 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data, 1327 }, 1328 { 1329 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data, 1330 }, 1331 { 1332 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data, 1333 }, 1334 { 1335 .compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data, 1336 }, 1337 {} 1338 }; 1339 MODULE_DEVICE_TABLE(of, wiz_id_table); 1340 1341 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) 1342 { 1343 struct device_node *serdes, *subnode; 1344 1345 serdes = of_get_child_by_name(dev->of_node, "serdes"); 1346 if (!serdes) { 1347 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); 1348 return -EINVAL; 1349 } 1350 1351 for_each_child_of_node(serdes, subnode) { 1352 u32 reg, num_lanes = 1, phy_type = PHY_NONE; 1353 int ret, i; 1354 1355 if (!(of_node_name_eq(subnode, "phy") || 1356 of_node_name_eq(subnode, "link"))) 1357 continue; 1358 1359 ret = of_property_read_u32(subnode, "reg", ®); 1360 if (ret) { 1361 of_node_put(subnode); 1362 dev_err(dev, 1363 "%s: Reading \"reg\" from \"%s\" failed: %d\n", 1364 __func__, subnode->name, ret); 1365 return ret; 1366 } 1367 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); 1368 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); 1369 1370 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, 1371 reg, reg + num_lanes - 1, phy_type); 1372 1373 for (i = reg; i < reg + num_lanes; i++) 1374 wiz->lane_phy_type[i] = phy_type; 1375 } 1376 1377 return 0; 1378 } 1379 1380 static int wiz_probe(struct platform_device *pdev) 1381 { 1382 struct reset_controller_dev *phy_reset_dev; 1383 struct device *dev = &pdev->dev; 1384 struct device_node *node = dev->of_node; 1385 struct platform_device *serdes_pdev; 1386 bool already_configured = false; 1387 struct device_node *child_node; 1388 struct regmap *regmap; 1389 struct resource res; 1390 void __iomem *base; 1391 struct wiz *wiz; 1392 int ret, val, i; 1393 u32 num_lanes; 1394 const struct wiz_data *data; 1395 1396 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); 1397 if (!wiz) 1398 return -ENOMEM; 1399 1400 data = of_device_get_match_data(dev); 1401 if (!data) { 1402 dev_err(dev, "NULL device data\n"); 1403 return -EINVAL; 1404 } 1405 1406 wiz->data = data; 1407 wiz->type = data->type; 1408 1409 child_node = of_get_child_by_name(node, "serdes"); 1410 if (!child_node) { 1411 dev_err(dev, "Failed to get SERDES child DT node\n"); 1412 return -ENODEV; 1413 } 1414 1415 ret = of_address_to_resource(child_node, 0, &res); 1416 if (ret) { 1417 dev_err(dev, "Failed to get memory resource\n"); 1418 goto err_addr_to_resource; 1419 } 1420 1421 base = devm_ioremap(dev, res.start, resource_size(&res)); 1422 if (!base) { 1423 ret = -ENOMEM; 1424 goto err_addr_to_resource; 1425 } 1426 1427 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); 1428 if (IS_ERR(regmap)) { 1429 dev_err(dev, "Failed to initialize regmap\n"); 1430 ret = PTR_ERR(regmap); 1431 goto err_addr_to_resource; 1432 } 1433 1434 wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm"); 1435 if (IS_ERR(wiz->scm_regmap)) { 1436 if (wiz->type == J7200_WIZ_10G) { 1437 dev_err(dev, "Couldn't get ti,scm regmap\n"); 1438 ret = -ENODEV; 1439 goto err_addr_to_resource; 1440 } 1441 1442 wiz->scm_regmap = NULL; 1443 } 1444 1445 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 1446 if (ret) { 1447 dev_err(dev, "Failed to read num-lanes property\n"); 1448 goto err_addr_to_resource; 1449 } 1450 1451 if (num_lanes > WIZ_MAX_LANES) { 1452 dev_err(dev, "Cannot support %d lanes\n", num_lanes); 1453 ret = -ENODEV; 1454 goto err_addr_to_resource; 1455 } 1456 1457 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", 1458 GPIOD_IN); 1459 if (IS_ERR(wiz->gpio_typec_dir)) { 1460 ret = PTR_ERR(wiz->gpio_typec_dir); 1461 if (ret != -EPROBE_DEFER) 1462 dev_err(dev, "Failed to request typec-dir gpio: %d\n", 1463 ret); 1464 goto err_addr_to_resource; 1465 } 1466 1467 if (wiz->gpio_typec_dir) { 1468 ret = of_property_read_u32(node, "typec-dir-debounce-ms", 1469 &wiz->typec_dir_delay); 1470 if (ret && ret != -EINVAL) { 1471 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1472 goto err_addr_to_resource; 1473 } 1474 1475 /* use min. debounce from Type-C spec if not provided in DT */ 1476 if (ret == -EINVAL) 1477 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; 1478 1479 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 1480 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 1481 ret = -EINVAL; 1482 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1483 goto err_addr_to_resource; 1484 } 1485 } 1486 1487 ret = wiz_get_lane_phy_types(dev, wiz); 1488 if (ret) 1489 goto err_addr_to_resource; 1490 1491 wiz->dev = dev; 1492 wiz->regmap = regmap; 1493 wiz->num_lanes = num_lanes; 1494 wiz->clk_mux_sel = data->clk_mux_sel; 1495 wiz->clk_div_sel = clk_div_sel; 1496 wiz->clk_div_sel_num = data->clk_div_sel_num; 1497 1498 platform_set_drvdata(pdev, wiz); 1499 1500 ret = wiz_regfield_init(wiz); 1501 if (ret) { 1502 dev_err(dev, "Failed to initialize regfields\n"); 1503 goto err_addr_to_resource; 1504 } 1505 1506 /* Enable supplemental Control override if available */ 1507 if (wiz->scm_regmap) 1508 regmap_field_write(wiz->sup_legacy_clk_override, 1); 1509 1510 phy_reset_dev = &wiz->wiz_phy_reset_dev; 1511 phy_reset_dev->dev = dev; 1512 phy_reset_dev->ops = &wiz_phy_reset_ops, 1513 phy_reset_dev->owner = THIS_MODULE, 1514 phy_reset_dev->of_node = node; 1515 /* Reset for each of the lane and one for the entire SERDES */ 1516 phy_reset_dev->nr_resets = num_lanes + 1; 1517 1518 ret = devm_reset_controller_register(dev, phy_reset_dev); 1519 if (ret < 0) { 1520 dev_warn(dev, "Failed to register reset controller\n"); 1521 goto err_addr_to_resource; 1522 } 1523 1524 pm_runtime_enable(dev); 1525 ret = pm_runtime_get_sync(dev); 1526 if (ret < 0) { 1527 dev_err(dev, "pm_runtime_get_sync failed\n"); 1528 goto err_get_sync; 1529 } 1530 1531 ret = wiz_clock_init(wiz, node); 1532 if (ret < 0) { 1533 dev_warn(dev, "Failed to initialize clocks\n"); 1534 goto err_get_sync; 1535 } 1536 1537 for (i = 0; i < wiz->num_lanes; i++) { 1538 regmap_field_read(wiz->p_enable[i], &val); 1539 if (val & (P_ENABLE | P_ENABLE_FORCE)) { 1540 already_configured = true; 1541 break; 1542 } 1543 } 1544 1545 if (!already_configured) { 1546 ret = wiz_init(wiz); 1547 if (ret) { 1548 dev_err(dev, "WIZ initialization failed\n"); 1549 goto err_wiz_init; 1550 } 1551 } 1552 1553 serdes_pdev = of_platform_device_create(child_node, NULL, dev); 1554 if (!serdes_pdev) { 1555 dev_WARN(dev, "Unable to create SERDES platform device\n"); 1556 ret = -ENOMEM; 1557 goto err_wiz_init; 1558 } 1559 wiz->serdes_pdev = serdes_pdev; 1560 1561 of_node_put(child_node); 1562 return 0; 1563 1564 err_wiz_init: 1565 wiz_clock_cleanup(wiz, node); 1566 1567 err_get_sync: 1568 pm_runtime_put(dev); 1569 pm_runtime_disable(dev); 1570 1571 err_addr_to_resource: 1572 of_node_put(child_node); 1573 1574 return ret; 1575 } 1576 1577 static int wiz_remove(struct platform_device *pdev) 1578 { 1579 struct device *dev = &pdev->dev; 1580 struct device_node *node = dev->of_node; 1581 struct platform_device *serdes_pdev; 1582 struct wiz *wiz; 1583 1584 wiz = dev_get_drvdata(dev); 1585 serdes_pdev = wiz->serdes_pdev; 1586 1587 of_platform_device_destroy(&serdes_pdev->dev, NULL); 1588 wiz_clock_cleanup(wiz, node); 1589 pm_runtime_put(dev); 1590 pm_runtime_disable(dev); 1591 1592 return 0; 1593 } 1594 1595 static struct platform_driver wiz_driver = { 1596 .probe = wiz_probe, 1597 .remove = wiz_remove, 1598 .driver = { 1599 .name = "wiz", 1600 .of_match_table = wiz_id_table, 1601 }, 1602 }; 1603 module_platform_driver(wiz_driver); 1604 1605 MODULE_AUTHOR("Texas Instruments Inc."); 1606 MODULE_DESCRIPTION("TI J721E WIZ driver"); 1607 MODULE_LICENSE("GPL v2"); 1608