1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Wrapper driver for SERDES used in J721E 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-ti.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/gpio.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/mux/consumer.h> 19 #include <linux/of_address.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regmap.h> 24 #include <linux/reset-controller.h> 25 26 #define WIZ_SERDES_CTRL 0x404 27 #define WIZ_SERDES_TOP_CTRL 0x408 28 #define WIZ_SERDES_RST 0x40c 29 #define WIZ_SERDES_TYPEC 0x410 30 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) 31 #define WIZ_LANEDIV(n) (0x484 + (0x40 * (n))) 32 33 #define WIZ_MAX_INPUT_CLOCKS 4 34 /* To include mux clocks, divider clocks and gate clocks */ 35 #define WIZ_MAX_OUTPUT_CLOCKS 32 36 37 #define WIZ_MAX_LANES 4 38 #define WIZ_MUX_NUM_CLOCKS 3 39 #define WIZ_DIV_NUM_CLOCKS_16G 2 40 #define WIZ_DIV_NUM_CLOCKS_10G 1 41 42 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) 43 44 enum wiz_lane_standard_mode { 45 LANE_MODE_GEN1, 46 LANE_MODE_GEN2, 47 LANE_MODE_GEN3, 48 LANE_MODE_GEN4, 49 }; 50 51 enum wiz_refclk_mux_sel { 52 PLL0_REFCLK, 53 PLL1_REFCLK, 54 REFCLK_DIG, 55 }; 56 57 enum wiz_refclk_div_sel { 58 CMN_REFCLK_DIG_DIV, 59 CMN_REFCLK1_DIG_DIV, 60 }; 61 62 enum wiz_clock_input { 63 WIZ_CORE_REFCLK, 64 WIZ_EXT_REFCLK, 65 WIZ_CORE_REFCLK1, 66 WIZ_EXT_REFCLK1, 67 }; 68 69 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); 70 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); 71 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); 72 static const struct reg_field pll1_refclk_mux_sel = 73 REG_FIELD(WIZ_SERDES_RST, 29, 29); 74 static const struct reg_field pll0_refclk_mux_sel = 75 REG_FIELD(WIZ_SERDES_RST, 28, 28); 76 static const struct reg_field refclk_dig_sel_16g = 77 REG_FIELD(WIZ_SERDES_RST, 24, 25); 78 static const struct reg_field refclk_dig_sel_10g = 79 REG_FIELD(WIZ_SERDES_RST, 24, 24); 80 static const struct reg_field pma_cmn_refclk_int_mode = 81 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 82 static const struct reg_field pma_cmn_refclk_mode = 83 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 84 static const struct reg_field pma_cmn_refclk_dig_div = 85 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); 86 static const struct reg_field pma_cmn_refclk1_dig_div = 87 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); 88 static const char * const output_clk_names[] = { 89 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk", 90 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk", 91 [TI_WIZ_REFCLK_DIG] = "refclk-dig", 92 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk", 93 }; 94 95 static const struct reg_field p_enable[WIZ_MAX_LANES] = { 96 REG_FIELD(WIZ_LANECTL(0), 30, 31), 97 REG_FIELD(WIZ_LANECTL(1), 30, 31), 98 REG_FIELD(WIZ_LANECTL(2), 30, 31), 99 REG_FIELD(WIZ_LANECTL(3), 30, 31), 100 }; 101 102 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; 103 104 static const struct reg_field p_align[WIZ_MAX_LANES] = { 105 REG_FIELD(WIZ_LANECTL(0), 29, 29), 106 REG_FIELD(WIZ_LANECTL(1), 29, 29), 107 REG_FIELD(WIZ_LANECTL(2), 29, 29), 108 REG_FIELD(WIZ_LANECTL(3), 29, 29), 109 }; 110 111 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { 112 REG_FIELD(WIZ_LANECTL(0), 28, 28), 113 REG_FIELD(WIZ_LANECTL(1), 28, 28), 114 REG_FIELD(WIZ_LANECTL(2), 28, 28), 115 REG_FIELD(WIZ_LANECTL(3), 28, 28), 116 }; 117 118 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { 119 REG_FIELD(WIZ_LANECTL(0), 24, 25), 120 REG_FIELD(WIZ_LANECTL(1), 24, 25), 121 REG_FIELD(WIZ_LANECTL(2), 24, 25), 122 REG_FIELD(WIZ_LANECTL(3), 24, 25), 123 }; 124 125 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { 126 REG_FIELD(WIZ_LANECTL(0), 22, 23), 127 REG_FIELD(WIZ_LANECTL(1), 22, 23), 128 REG_FIELD(WIZ_LANECTL(2), 22, 23), 129 REG_FIELD(WIZ_LANECTL(3), 22, 23), 130 }; 131 132 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { 133 REG_FIELD(WIZ_LANEDIV(0), 16, 22), 134 REG_FIELD(WIZ_LANEDIV(1), 16, 22), 135 REG_FIELD(WIZ_LANEDIV(2), 16, 22), 136 REG_FIELD(WIZ_LANEDIV(3), 16, 22), 137 }; 138 139 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { 140 REG_FIELD(WIZ_LANEDIV(0), 0, 8), 141 REG_FIELD(WIZ_LANEDIV(1), 0, 8), 142 REG_FIELD(WIZ_LANEDIV(2), 0, 8), 143 REG_FIELD(WIZ_LANEDIV(3), 0, 8), 144 }; 145 146 static const struct reg_field typec_ln10_swap = 147 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 148 149 struct wiz_clk_mux { 150 struct clk_hw hw; 151 struct regmap_field *field; 152 const u32 *table; 153 struct clk_init_data clk_data; 154 }; 155 156 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) 157 158 struct wiz_clk_divider { 159 struct clk_hw hw; 160 struct regmap_field *field; 161 const struct clk_div_table *table; 162 struct clk_init_data clk_data; 163 }; 164 165 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) 166 167 struct wiz_clk_mux_sel { 168 u32 table[WIZ_MAX_INPUT_CLOCKS]; 169 const char *node_name; 170 u32 num_parents; 171 u32 parents[WIZ_MAX_INPUT_CLOCKS]; 172 }; 173 174 struct wiz_clk_div_sel { 175 const struct clk_div_table *table; 176 const char *node_name; 177 }; 178 179 struct wiz_phy_en_refclk { 180 struct clk_hw hw; 181 struct regmap_field *phy_en_refclk; 182 struct clk_init_data clk_data; 183 }; 184 185 #define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw) 186 187 static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = { 188 { 189 /* 190 * Mux value to be configured for each of the input clocks 191 * in the order populated in device tree 192 */ 193 .table = { 1, 0 }, 194 .node_name = "pll0-refclk", 195 }, 196 { 197 .table = { 1, 0 }, 198 .node_name = "pll1-refclk", 199 }, 200 { 201 .table = { 1, 3, 0, 2 }, 202 .node_name = "refclk-dig", 203 }, 204 }; 205 206 static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 207 { 208 /* 209 * Mux value to be configured for each of the input clocks 210 * in the order populated in device tree 211 */ 212 .num_parents = 2, 213 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 214 .table = { 1, 0 }, 215 .node_name = "pll0-refclk", 216 }, 217 { 218 .num_parents = 2, 219 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 220 .table = { 1, 0 }, 221 .node_name = "pll1-refclk", 222 }, 223 { 224 .num_parents = 2, 225 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 226 .table = { 1, 0 }, 227 .node_name = "refclk-dig", 228 }, 229 }; 230 231 static const struct clk_div_table clk_div_table[] = { 232 { .val = 0, .div = 1, }, 233 { .val = 1, .div = 2, }, 234 { .val = 2, .div = 4, }, 235 { .val = 3, .div = 8, }, 236 { /* sentinel */ }, 237 }; 238 239 static const struct wiz_clk_div_sel clk_div_sel[] = { 240 { 241 .table = clk_div_table, 242 .node_name = "cmn-refclk-dig-div", 243 }, 244 { 245 .table = clk_div_table, 246 .node_name = "cmn-refclk1-dig-div", 247 }, 248 }; 249 250 enum wiz_type { 251 J721E_WIZ_16G, 252 J721E_WIZ_10G, 253 AM64_WIZ_10G, 254 }; 255 256 struct wiz_data { 257 enum wiz_type type; 258 const struct reg_field *refclk_dig_sel; 259 const struct reg_field *pma_cmn_refclk1_dig_div; 260 const struct wiz_clk_mux_sel *clk_mux_sel; 261 unsigned int clk_div_sel_num; 262 }; 263 264 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ 265 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 266 267 struct wiz { 268 struct regmap *regmap; 269 enum wiz_type type; 270 const struct wiz_clk_mux_sel *clk_mux_sel; 271 const struct wiz_clk_div_sel *clk_div_sel; 272 unsigned int clk_div_sel_num; 273 struct regmap_field *por_en; 274 struct regmap_field *phy_reset_n; 275 struct regmap_field *phy_en_refclk; 276 struct regmap_field *p_enable[WIZ_MAX_LANES]; 277 struct regmap_field *p_align[WIZ_MAX_LANES]; 278 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; 279 struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; 280 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; 281 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; 282 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; 283 struct regmap_field *pma_cmn_refclk_int_mode; 284 struct regmap_field *pma_cmn_refclk_mode; 285 struct regmap_field *pma_cmn_refclk_dig_div; 286 struct regmap_field *pma_cmn_refclk1_dig_div; 287 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; 288 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; 289 struct regmap_field *typec_ln10_swap; 290 291 struct device *dev; 292 u32 num_lanes; 293 struct platform_device *serdes_pdev; 294 struct reset_controller_dev wiz_phy_reset_dev; 295 struct gpio_desc *gpio_typec_dir; 296 int typec_dir_delay; 297 u32 lane_phy_type[WIZ_MAX_LANES]; 298 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; 299 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS]; 300 struct clk_onecell_data clk_data; 301 const struct wiz_data *data; 302 }; 303 304 static int wiz_reset(struct wiz *wiz) 305 { 306 int ret; 307 308 ret = regmap_field_write(wiz->por_en, 0x1); 309 if (ret) 310 return ret; 311 312 mdelay(1); 313 314 ret = regmap_field_write(wiz->por_en, 0x0); 315 if (ret) 316 return ret; 317 318 return 0; 319 } 320 321 static int wiz_p_mac_div_sel(struct wiz *wiz) 322 { 323 u32 num_lanes = wiz->num_lanes; 324 int ret; 325 int i; 326 327 for (i = 0; i < num_lanes; i++) { 328 if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { 329 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); 330 if (ret) 331 return ret; 332 333 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); 334 if (ret) 335 return ret; 336 } 337 } 338 339 return 0; 340 } 341 342 static int wiz_mode_select(struct wiz *wiz) 343 { 344 u32 num_lanes = wiz->num_lanes; 345 enum wiz_lane_standard_mode mode; 346 int ret; 347 int i; 348 349 for (i = 0; i < num_lanes; i++) { 350 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) 351 mode = LANE_MODE_GEN1; 352 else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) 353 mode = LANE_MODE_GEN2; 354 else 355 continue; 356 357 ret = regmap_field_write(wiz->p_standard_mode[i], mode); 358 if (ret) 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int wiz_init_raw_interface(struct wiz *wiz, bool enable) 366 { 367 u32 num_lanes = wiz->num_lanes; 368 int i; 369 int ret; 370 371 for (i = 0; i < num_lanes; i++) { 372 ret = regmap_field_write(wiz->p_align[i], enable); 373 if (ret) 374 return ret; 375 376 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); 377 if (ret) 378 return ret; 379 } 380 381 return 0; 382 } 383 384 static int wiz_init(struct wiz *wiz) 385 { 386 struct device *dev = wiz->dev; 387 int ret; 388 389 ret = wiz_reset(wiz); 390 if (ret) { 391 dev_err(dev, "WIZ reset failed\n"); 392 return ret; 393 } 394 395 ret = wiz_mode_select(wiz); 396 if (ret) { 397 dev_err(dev, "WIZ mode select failed\n"); 398 return ret; 399 } 400 401 ret = wiz_p_mac_div_sel(wiz); 402 if (ret) { 403 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); 404 return ret; 405 } 406 407 ret = wiz_init_raw_interface(wiz, true); 408 if (ret) { 409 dev_err(dev, "WIZ interface initialization failed\n"); 410 return ret; 411 } 412 413 return 0; 414 } 415 416 static int wiz_regfield_init(struct wiz *wiz) 417 { 418 struct regmap *regmap = wiz->regmap; 419 int num_lanes = wiz->num_lanes; 420 struct device *dev = wiz->dev; 421 const struct wiz_data *data = wiz->data; 422 int i; 423 424 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); 425 if (IS_ERR(wiz->por_en)) { 426 dev_err(dev, "POR_EN reg field init failed\n"); 427 return PTR_ERR(wiz->por_en); 428 } 429 430 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, 431 phy_reset_n); 432 if (IS_ERR(wiz->phy_reset_n)) { 433 dev_err(dev, "PHY_RESET_N reg field init failed\n"); 434 return PTR_ERR(wiz->phy_reset_n); 435 } 436 437 wiz->pma_cmn_refclk_int_mode = 438 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); 439 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { 440 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); 441 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); 442 } 443 444 wiz->pma_cmn_refclk_mode = 445 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); 446 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { 447 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); 448 return PTR_ERR(wiz->pma_cmn_refclk_mode); 449 } 450 451 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] = 452 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div); 453 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) { 454 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); 455 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); 456 } 457 458 if (data->pma_cmn_refclk1_dig_div) { 459 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = 460 devm_regmap_field_alloc(dev, regmap, 461 *data->pma_cmn_refclk1_dig_div); 462 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { 463 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); 464 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); 465 } 466 } 467 468 wiz->mux_sel_field[PLL0_REFCLK] = 469 devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel); 470 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { 471 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); 472 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); 473 } 474 475 wiz->mux_sel_field[PLL1_REFCLK] = 476 devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel); 477 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { 478 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); 479 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); 480 } 481 482 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, regmap, 483 *data->refclk_dig_sel); 484 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { 485 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); 486 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); 487 } 488 489 for (i = 0; i < num_lanes; i++) { 490 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, 491 p_enable[i]); 492 if (IS_ERR(wiz->p_enable[i])) { 493 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 494 return PTR_ERR(wiz->p_enable[i]); 495 } 496 497 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, 498 p_align[i]); 499 if (IS_ERR(wiz->p_align[i])) { 500 dev_err(dev, "P%d_ALIGN reg field init failed\n", i); 501 return PTR_ERR(wiz->p_align[i]); 502 } 503 504 wiz->p_raw_auto_start[i] = 505 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); 506 if (IS_ERR(wiz->p_raw_auto_start[i])) { 507 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", 508 i); 509 return PTR_ERR(wiz->p_raw_auto_start[i]); 510 } 511 512 wiz->p_standard_mode[i] = 513 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); 514 if (IS_ERR(wiz->p_standard_mode[i])) { 515 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", 516 i); 517 return PTR_ERR(wiz->p_standard_mode[i]); 518 } 519 520 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); 521 if (IS_ERR(wiz->p0_fullrt_div[i])) { 522 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i); 523 return PTR_ERR(wiz->p0_fullrt_div[i]); 524 } 525 526 wiz->p_mac_div_sel0[i] = 527 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); 528 if (IS_ERR(wiz->p_mac_div_sel0[i])) { 529 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n", 530 i); 531 return PTR_ERR(wiz->p_mac_div_sel0[i]); 532 } 533 534 wiz->p_mac_div_sel1[i] = 535 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]); 536 if (IS_ERR(wiz->p_mac_div_sel1[i])) { 537 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n", 538 i); 539 return PTR_ERR(wiz->p_mac_div_sel1[i]); 540 } 541 } 542 543 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, 544 typec_ln10_swap); 545 if (IS_ERR(wiz->typec_ln10_swap)) { 546 dev_err(dev, "LN10_SWAP reg field init failed\n"); 547 return PTR_ERR(wiz->typec_ln10_swap); 548 } 549 550 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); 551 if (IS_ERR(wiz->phy_en_refclk)) { 552 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n"); 553 return PTR_ERR(wiz->phy_en_refclk); 554 } 555 556 return 0; 557 } 558 559 static int wiz_phy_en_refclk_enable(struct clk_hw *hw) 560 { 561 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 562 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 563 564 regmap_field_write(phy_en_refclk, 1); 565 566 return 0; 567 } 568 569 static void wiz_phy_en_refclk_disable(struct clk_hw *hw) 570 { 571 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 572 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 573 574 regmap_field_write(phy_en_refclk, 0); 575 } 576 577 static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw) 578 { 579 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 580 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 581 int val; 582 583 regmap_field_read(phy_en_refclk, &val); 584 585 return !!val; 586 } 587 588 static const struct clk_ops wiz_phy_en_refclk_ops = { 589 .enable = wiz_phy_en_refclk_enable, 590 .disable = wiz_phy_en_refclk_disable, 591 .is_enabled = wiz_phy_en_refclk_is_enabled, 592 }; 593 594 static int wiz_phy_en_refclk_register(struct wiz *wiz) 595 { 596 struct wiz_phy_en_refclk *wiz_phy_en_refclk; 597 struct device *dev = wiz->dev; 598 struct clk_init_data *init; 599 struct clk *clk; 600 601 wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL); 602 if (!wiz_phy_en_refclk) 603 return -ENOMEM; 604 605 init = &wiz_phy_en_refclk->clk_data; 606 607 init->ops = &wiz_phy_en_refclk_ops; 608 init->flags = 0; 609 init->name = output_clk_names[TI_WIZ_PHY_EN_REFCLK]; 610 611 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; 612 wiz_phy_en_refclk->hw.init = init; 613 614 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); 615 if (IS_ERR(clk)) 616 return PTR_ERR(clk); 617 618 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk; 619 620 return 0; 621 } 622 623 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) 624 { 625 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 626 struct regmap_field *field = mux->field; 627 unsigned int val; 628 629 regmap_field_read(field, &val); 630 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val); 631 } 632 633 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) 634 { 635 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 636 struct regmap_field *field = mux->field; 637 int val; 638 639 val = mux->table[index]; 640 return regmap_field_write(field, val); 641 } 642 643 static const struct clk_ops wiz_clk_mux_ops = { 644 .set_parent = wiz_clk_mux_set_parent, 645 .get_parent = wiz_clk_mux_get_parent, 646 }; 647 648 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field, 649 const struct wiz_clk_mux_sel *mux_sel, int clk_index) 650 { 651 struct device *dev = wiz->dev; 652 struct clk_init_data *init; 653 const char **parent_names; 654 unsigned int num_parents; 655 struct wiz_clk_mux *mux; 656 char clk_name[100]; 657 struct clk *clk; 658 int ret = 0, i; 659 660 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 661 if (!mux) 662 return -ENOMEM; 663 664 num_parents = mux_sel->num_parents; 665 666 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); 667 if (!parent_names) 668 return -ENOMEM; 669 670 for (i = 0; i < num_parents; i++) { 671 clk = wiz->input_clks[mux_sel->parents[i]]; 672 if (IS_ERR_OR_NULL(clk)) { 673 dev_err(dev, "Failed to get parent clk for %s\n", 674 output_clk_names[clk_index]); 675 ret = -EINVAL; 676 goto err; 677 } 678 parent_names[i] = __clk_get_name(clk); 679 } 680 681 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]); 682 683 init = &mux->clk_data; 684 685 init->ops = &wiz_clk_mux_ops; 686 init->flags = CLK_SET_RATE_NO_REPARENT; 687 init->parent_names = parent_names; 688 init->num_parents = num_parents; 689 init->name = clk_name; 690 691 mux->field = field; 692 mux->table = mux_sel->table; 693 mux->hw.init = init; 694 695 clk = devm_clk_register(dev, &mux->hw); 696 if (IS_ERR(clk)) { 697 ret = PTR_ERR(clk); 698 goto err; 699 } 700 701 wiz->output_clks[clk_index] = clk; 702 703 err: 704 kfree(parent_names); 705 706 return ret; 707 } 708 709 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node, 710 struct regmap_field *field, const u32 *table) 711 { 712 struct device *dev = wiz->dev; 713 struct clk_init_data *init; 714 const char **parent_names; 715 unsigned int num_parents; 716 struct wiz_clk_mux *mux; 717 char clk_name[100]; 718 struct clk *clk; 719 int ret; 720 721 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 722 if (!mux) 723 return -ENOMEM; 724 725 num_parents = of_clk_get_parent_count(node); 726 if (num_parents < 2) { 727 dev_err(dev, "SERDES clock must have parents\n"); 728 return -EINVAL; 729 } 730 731 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 732 GFP_KERNEL); 733 if (!parent_names) 734 return -ENOMEM; 735 736 of_clk_parent_fill(node, parent_names, num_parents); 737 738 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 739 node->name); 740 741 init = &mux->clk_data; 742 743 init->ops = &wiz_clk_mux_ops; 744 init->flags = CLK_SET_RATE_NO_REPARENT; 745 init->parent_names = parent_names; 746 init->num_parents = num_parents; 747 init->name = clk_name; 748 749 mux->field = field; 750 mux->table = table; 751 mux->hw.init = init; 752 753 clk = devm_clk_register(dev, &mux->hw); 754 if (IS_ERR(clk)) 755 return PTR_ERR(clk); 756 757 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 758 if (ret) 759 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 760 761 return ret; 762 } 763 764 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, 765 unsigned long parent_rate) 766 { 767 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 768 struct regmap_field *field = div->field; 769 int val; 770 771 regmap_field_read(field, &val); 772 773 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); 774 } 775 776 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 777 unsigned long *prate) 778 { 779 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 780 781 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); 782 } 783 784 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 785 unsigned long parent_rate) 786 { 787 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 788 struct regmap_field *field = div->field; 789 int val; 790 791 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); 792 if (val < 0) 793 return val; 794 795 return regmap_field_write(field, val); 796 } 797 798 static const struct clk_ops wiz_clk_div_ops = { 799 .recalc_rate = wiz_clk_div_recalc_rate, 800 .round_rate = wiz_clk_div_round_rate, 801 .set_rate = wiz_clk_div_set_rate, 802 }; 803 804 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, 805 struct regmap_field *field, 806 const struct clk_div_table *table) 807 { 808 struct device *dev = wiz->dev; 809 struct wiz_clk_divider *div; 810 struct clk_init_data *init; 811 const char **parent_names; 812 char clk_name[100]; 813 struct clk *clk; 814 int ret; 815 816 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 817 if (!div) 818 return -ENOMEM; 819 820 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 821 node->name); 822 823 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 824 if (!parent_names) 825 return -ENOMEM; 826 827 of_clk_parent_fill(node, parent_names, 1); 828 829 init = &div->clk_data; 830 831 init->ops = &wiz_clk_div_ops; 832 init->flags = 0; 833 init->parent_names = parent_names; 834 init->num_parents = 1; 835 init->name = clk_name; 836 837 div->field = field; 838 div->table = table; 839 div->hw.init = init; 840 841 clk = devm_clk_register(dev, &div->hw); 842 if (IS_ERR(clk)) 843 return PTR_ERR(clk); 844 845 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 846 if (ret) 847 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 848 849 return ret; 850 } 851 852 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) 853 { 854 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 855 struct device *dev = wiz->dev; 856 struct device_node *clk_node; 857 int i; 858 859 if (wiz->type == AM64_WIZ_10G) { 860 of_clk_del_provider(dev->of_node); 861 return; 862 } 863 864 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 865 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); 866 of_clk_del_provider(clk_node); 867 of_node_put(clk_node); 868 } 869 870 for (i = 0; i < wiz->clk_div_sel_num; i++) { 871 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name); 872 of_clk_del_provider(clk_node); 873 of_node_put(clk_node); 874 } 875 876 of_clk_del_provider(wiz->dev->of_node); 877 } 878 879 static int wiz_clock_register(struct wiz *wiz) 880 { 881 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 882 struct device *dev = wiz->dev; 883 struct device_node *node = dev->of_node; 884 int clk_index; 885 int ret; 886 int i; 887 888 if (wiz->type != AM64_WIZ_10G) 889 return 0; 890 891 clk_index = TI_WIZ_PLL0_REFCLK; 892 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { 893 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); 894 if (ret) { 895 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]); 896 return ret; 897 } 898 } 899 900 ret = wiz_phy_en_refclk_register(wiz); 901 if (ret) { 902 dev_err(dev, "Failed to add phy-en-refclk\n"); 903 return ret; 904 } 905 906 wiz->clk_data.clks = wiz->output_clks; 907 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS; 908 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data); 909 if (ret) 910 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 911 912 return ret; 913 } 914 915 static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 916 { 917 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 918 struct device *dev = wiz->dev; 919 struct device_node *clk_node; 920 const char *node_name; 921 unsigned long rate; 922 struct clk *clk; 923 int ret; 924 int i; 925 926 clk = devm_clk_get(dev, "core_ref_clk"); 927 if (IS_ERR(clk)) { 928 dev_err(dev, "core_ref_clk clock not found\n"); 929 ret = PTR_ERR(clk); 930 return ret; 931 } 932 wiz->input_clks[WIZ_CORE_REFCLK] = clk; 933 934 rate = clk_get_rate(clk); 935 if (rate >= 100000000) 936 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 937 else 938 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 939 940 clk = devm_clk_get(dev, "ext_ref_clk"); 941 if (IS_ERR(clk)) { 942 dev_err(dev, "ext_ref_clk clock not found\n"); 943 ret = PTR_ERR(clk); 944 return ret; 945 } 946 wiz->input_clks[WIZ_EXT_REFCLK] = clk; 947 948 rate = clk_get_rate(clk); 949 if (rate >= 100000000) 950 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 951 else 952 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 953 954 if (wiz->type == AM64_WIZ_10G) { 955 ret = wiz_clock_register(wiz); 956 if (ret) 957 dev_err(dev, "Failed to register wiz clocks\n"); 958 return ret; 959 } 960 961 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 962 node_name = clk_mux_sel[i].node_name; 963 clk_node = of_get_child_by_name(node, node_name); 964 if (!clk_node) { 965 dev_err(dev, "Unable to get %s node\n", node_name); 966 ret = -EINVAL; 967 goto err; 968 } 969 970 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i], 971 clk_mux_sel[i].table); 972 if (ret) { 973 dev_err(dev, "Failed to register %s clock\n", 974 node_name); 975 of_node_put(clk_node); 976 goto err; 977 } 978 979 of_node_put(clk_node); 980 } 981 982 for (i = 0; i < wiz->clk_div_sel_num; i++) { 983 node_name = clk_div_sel[i].node_name; 984 clk_node = of_get_child_by_name(node, node_name); 985 if (!clk_node) { 986 dev_err(dev, "Unable to get %s node\n", node_name); 987 ret = -EINVAL; 988 goto err; 989 } 990 991 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i], 992 clk_div_sel[i].table); 993 if (ret) { 994 dev_err(dev, "Failed to register %s clock\n", 995 node_name); 996 of_node_put(clk_node); 997 goto err; 998 } 999 1000 of_node_put(clk_node); 1001 } 1002 1003 return 0; 1004 err: 1005 wiz_clock_cleanup(wiz, node); 1006 1007 return ret; 1008 } 1009 1010 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, 1011 unsigned long id) 1012 { 1013 struct device *dev = rcdev->dev; 1014 struct wiz *wiz = dev_get_drvdata(dev); 1015 int ret = 0; 1016 1017 if (id == 0) { 1018 ret = regmap_field_write(wiz->phy_reset_n, false); 1019 return ret; 1020 } 1021 1022 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); 1023 return ret; 1024 } 1025 1026 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) 1027 { 1028 if (wiz->type != AM64_WIZ_10G) 1029 return 0; 1030 1031 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) 1032 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); 1033 1034 return 0; 1035 } 1036 1037 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, 1038 unsigned long id) 1039 { 1040 struct device *dev = rcdev->dev; 1041 struct wiz *wiz = dev_get_drvdata(dev); 1042 int ret; 1043 1044 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ 1045 if (id == 0 && wiz->gpio_typec_dir) { 1046 if (wiz->typec_dir_delay) 1047 msleep_interruptible(wiz->typec_dir_delay); 1048 1049 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) 1050 regmap_field_write(wiz->typec_ln10_swap, 1); 1051 else 1052 regmap_field_write(wiz->typec_ln10_swap, 0); 1053 } 1054 1055 if (id == 0) { 1056 ret = regmap_field_write(wiz->phy_reset_n, true); 1057 return ret; 1058 } 1059 1060 ret = wiz_phy_fullrt_div(wiz, id - 1); 1061 if (ret) 1062 return ret; 1063 1064 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) 1065 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); 1066 else 1067 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); 1068 1069 return ret; 1070 } 1071 1072 static const struct reset_control_ops wiz_phy_reset_ops = { 1073 .assert = wiz_phy_reset_assert, 1074 .deassert = wiz_phy_reset_deassert, 1075 }; 1076 1077 static const struct regmap_config wiz_regmap_config = { 1078 .reg_bits = 32, 1079 .val_bits = 32, 1080 .reg_stride = 4, 1081 .fast_io = true, 1082 }; 1083 1084 static struct wiz_data j721e_16g_data = { 1085 .type = J721E_WIZ_16G, 1086 .refclk_dig_sel = &refclk_dig_sel_16g, 1087 .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div, 1088 .clk_mux_sel = clk_mux_sel_16g, 1089 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G, 1090 }; 1091 1092 static struct wiz_data j721e_10g_data = { 1093 .type = J721E_WIZ_10G, 1094 .refclk_dig_sel = &refclk_dig_sel_10g, 1095 .clk_mux_sel = clk_mux_sel_10g, 1096 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1097 }; 1098 1099 static struct wiz_data am64_10g_data = { 1100 .type = AM64_WIZ_10G, 1101 .refclk_dig_sel = &refclk_dig_sel_10g, 1102 .clk_mux_sel = clk_mux_sel_10g, 1103 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1104 }; 1105 1106 static const struct of_device_id wiz_id_table[] = { 1107 { 1108 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, 1109 }, 1110 { 1111 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data, 1112 }, 1113 { 1114 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data, 1115 }, 1116 {} 1117 }; 1118 MODULE_DEVICE_TABLE(of, wiz_id_table); 1119 1120 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) 1121 { 1122 struct device_node *serdes, *subnode; 1123 1124 serdes = of_get_child_by_name(dev->of_node, "serdes"); 1125 if (!serdes) { 1126 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); 1127 return -EINVAL; 1128 } 1129 1130 for_each_child_of_node(serdes, subnode) { 1131 u32 reg, num_lanes = 1, phy_type = PHY_NONE; 1132 int ret, i; 1133 1134 if (!(of_node_name_eq(subnode, "phy") || 1135 of_node_name_eq(subnode, "link"))) 1136 continue; 1137 1138 ret = of_property_read_u32(subnode, "reg", ®); 1139 if (ret) { 1140 of_node_put(subnode); 1141 dev_err(dev, 1142 "%s: Reading \"reg\" from \"%s\" failed: %d\n", 1143 __func__, subnode->name, ret); 1144 return ret; 1145 } 1146 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); 1147 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); 1148 1149 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, 1150 reg, reg + num_lanes - 1, phy_type); 1151 1152 for (i = reg; i < reg + num_lanes; i++) 1153 wiz->lane_phy_type[i] = phy_type; 1154 } 1155 1156 return 0; 1157 } 1158 1159 static int wiz_probe(struct platform_device *pdev) 1160 { 1161 struct reset_controller_dev *phy_reset_dev; 1162 struct device *dev = &pdev->dev; 1163 struct device_node *node = dev->of_node; 1164 struct platform_device *serdes_pdev; 1165 bool already_configured = false; 1166 struct device_node *child_node; 1167 struct regmap *regmap; 1168 struct resource res; 1169 void __iomem *base; 1170 struct wiz *wiz; 1171 int ret, val, i; 1172 u32 num_lanes; 1173 const struct wiz_data *data; 1174 1175 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); 1176 if (!wiz) 1177 return -ENOMEM; 1178 1179 data = of_device_get_match_data(dev); 1180 if (!data) { 1181 dev_err(dev, "NULL device data\n"); 1182 return -EINVAL; 1183 } 1184 1185 wiz->data = data; 1186 wiz->type = data->type; 1187 1188 child_node = of_get_child_by_name(node, "serdes"); 1189 if (!child_node) { 1190 dev_err(dev, "Failed to get SERDES child DT node\n"); 1191 return -ENODEV; 1192 } 1193 1194 ret = of_address_to_resource(child_node, 0, &res); 1195 if (ret) { 1196 dev_err(dev, "Failed to get memory resource\n"); 1197 goto err_addr_to_resource; 1198 } 1199 1200 base = devm_ioremap(dev, res.start, resource_size(&res)); 1201 if (!base) { 1202 ret = -ENOMEM; 1203 goto err_addr_to_resource; 1204 } 1205 1206 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); 1207 if (IS_ERR(regmap)) { 1208 dev_err(dev, "Failed to initialize regmap\n"); 1209 ret = PTR_ERR(regmap); 1210 goto err_addr_to_resource; 1211 } 1212 1213 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 1214 if (ret) { 1215 dev_err(dev, "Failed to read num-lanes property\n"); 1216 goto err_addr_to_resource; 1217 } 1218 1219 if (num_lanes > WIZ_MAX_LANES) { 1220 dev_err(dev, "Cannot support %d lanes\n", num_lanes); 1221 ret = -ENODEV; 1222 goto err_addr_to_resource; 1223 } 1224 1225 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", 1226 GPIOD_IN); 1227 if (IS_ERR(wiz->gpio_typec_dir)) { 1228 ret = PTR_ERR(wiz->gpio_typec_dir); 1229 if (ret != -EPROBE_DEFER) 1230 dev_err(dev, "Failed to request typec-dir gpio: %d\n", 1231 ret); 1232 goto err_addr_to_resource; 1233 } 1234 1235 if (wiz->gpio_typec_dir) { 1236 ret = of_property_read_u32(node, "typec-dir-debounce-ms", 1237 &wiz->typec_dir_delay); 1238 if (ret && ret != -EINVAL) { 1239 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1240 goto err_addr_to_resource; 1241 } 1242 1243 /* use min. debounce from Type-C spec if not provided in DT */ 1244 if (ret == -EINVAL) 1245 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; 1246 1247 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 1248 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 1249 ret = -EINVAL; 1250 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1251 goto err_addr_to_resource; 1252 } 1253 } 1254 1255 ret = wiz_get_lane_phy_types(dev, wiz); 1256 if (ret) 1257 return ret; 1258 1259 wiz->dev = dev; 1260 wiz->regmap = regmap; 1261 wiz->num_lanes = num_lanes; 1262 wiz->clk_mux_sel = data->clk_mux_sel; 1263 wiz->clk_div_sel = clk_div_sel; 1264 wiz->clk_div_sel_num = data->clk_div_sel_num; 1265 1266 platform_set_drvdata(pdev, wiz); 1267 1268 ret = wiz_regfield_init(wiz); 1269 if (ret) { 1270 dev_err(dev, "Failed to initialize regfields\n"); 1271 goto err_addr_to_resource; 1272 } 1273 1274 phy_reset_dev = &wiz->wiz_phy_reset_dev; 1275 phy_reset_dev->dev = dev; 1276 phy_reset_dev->ops = &wiz_phy_reset_ops, 1277 phy_reset_dev->owner = THIS_MODULE, 1278 phy_reset_dev->of_node = node; 1279 /* Reset for each of the lane and one for the entire SERDES */ 1280 phy_reset_dev->nr_resets = num_lanes + 1; 1281 1282 ret = devm_reset_controller_register(dev, phy_reset_dev); 1283 if (ret < 0) { 1284 dev_warn(dev, "Failed to register reset controller\n"); 1285 goto err_addr_to_resource; 1286 } 1287 1288 pm_runtime_enable(dev); 1289 ret = pm_runtime_get_sync(dev); 1290 if (ret < 0) { 1291 dev_err(dev, "pm_runtime_get_sync failed\n"); 1292 goto err_get_sync; 1293 } 1294 1295 ret = wiz_clock_init(wiz, node); 1296 if (ret < 0) { 1297 dev_warn(dev, "Failed to initialize clocks\n"); 1298 goto err_get_sync; 1299 } 1300 1301 for (i = 0; i < wiz->num_lanes; i++) { 1302 regmap_field_read(wiz->p_enable[i], &val); 1303 if (val & (P_ENABLE | P_ENABLE_FORCE)) { 1304 already_configured = true; 1305 break; 1306 } 1307 } 1308 1309 if (!already_configured) { 1310 ret = wiz_init(wiz); 1311 if (ret) { 1312 dev_err(dev, "WIZ initialization failed\n"); 1313 goto err_wiz_init; 1314 } 1315 } 1316 1317 serdes_pdev = of_platform_device_create(child_node, NULL, dev); 1318 if (!serdes_pdev) { 1319 dev_WARN(dev, "Unable to create SERDES platform device\n"); 1320 ret = -ENOMEM; 1321 goto err_wiz_init; 1322 } 1323 wiz->serdes_pdev = serdes_pdev; 1324 1325 of_node_put(child_node); 1326 return 0; 1327 1328 err_wiz_init: 1329 wiz_clock_cleanup(wiz, node); 1330 1331 err_get_sync: 1332 pm_runtime_put(dev); 1333 pm_runtime_disable(dev); 1334 1335 err_addr_to_resource: 1336 of_node_put(child_node); 1337 1338 return ret; 1339 } 1340 1341 static int wiz_remove(struct platform_device *pdev) 1342 { 1343 struct device *dev = &pdev->dev; 1344 struct device_node *node = dev->of_node; 1345 struct platform_device *serdes_pdev; 1346 struct wiz *wiz; 1347 1348 wiz = dev_get_drvdata(dev); 1349 serdes_pdev = wiz->serdes_pdev; 1350 1351 of_platform_device_destroy(&serdes_pdev->dev, NULL); 1352 wiz_clock_cleanup(wiz, node); 1353 pm_runtime_put(dev); 1354 pm_runtime_disable(dev); 1355 1356 return 0; 1357 } 1358 1359 static struct platform_driver wiz_driver = { 1360 .probe = wiz_probe, 1361 .remove = wiz_remove, 1362 .driver = { 1363 .name = "wiz", 1364 .of_match_table = wiz_id_table, 1365 }, 1366 }; 1367 module_platform_driver(wiz_driver); 1368 1369 MODULE_AUTHOR("Texas Instruments Inc."); 1370 MODULE_DESCRIPTION("TI J721E WIZ driver"); 1371 MODULE_LICENSE("GPL v2"); 1372