1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Wrapper driver for SERDES used in J721E 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-ti.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/gpio.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/mux/consumer.h> 19 #include <linux/of_address.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regmap.h> 24 #include <linux/reset-controller.h> 25 26 #define WIZ_SERDES_CTRL 0x404 27 #define WIZ_SERDES_TOP_CTRL 0x408 28 #define WIZ_SERDES_RST 0x40c 29 #define WIZ_SERDES_TYPEC 0x410 30 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) 31 #define WIZ_LANEDIV(n) (0x484 + (0x40 * (n))) 32 33 #define WIZ_MAX_INPUT_CLOCKS 4 34 /* To include mux clocks, divider clocks and gate clocks */ 35 #define WIZ_MAX_OUTPUT_CLOCKS 32 36 37 #define WIZ_MAX_LANES 4 38 #define WIZ_MUX_NUM_CLOCKS 3 39 #define WIZ_DIV_NUM_CLOCKS_16G 2 40 #define WIZ_DIV_NUM_CLOCKS_10G 1 41 42 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) 43 44 enum wiz_lane_standard_mode { 45 LANE_MODE_GEN1, 46 LANE_MODE_GEN2, 47 LANE_MODE_GEN3, 48 LANE_MODE_GEN4, 49 }; 50 51 enum wiz_refclk_mux_sel { 52 PLL0_REFCLK, 53 PLL1_REFCLK, 54 REFCLK_DIG, 55 }; 56 57 enum wiz_refclk_div_sel { 58 CMN_REFCLK_DIG_DIV, 59 CMN_REFCLK1_DIG_DIV, 60 }; 61 62 enum wiz_clock_input { 63 WIZ_CORE_REFCLK, 64 WIZ_EXT_REFCLK, 65 WIZ_CORE_REFCLK1, 66 WIZ_EXT_REFCLK1, 67 }; 68 69 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); 70 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); 71 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); 72 static const struct reg_field pll1_refclk_mux_sel = 73 REG_FIELD(WIZ_SERDES_RST, 29, 29); 74 static const struct reg_field pll0_refclk_mux_sel = 75 REG_FIELD(WIZ_SERDES_RST, 28, 28); 76 static const struct reg_field refclk_dig_sel_16g = 77 REG_FIELD(WIZ_SERDES_RST, 24, 25); 78 static const struct reg_field refclk_dig_sel_10g = 79 REG_FIELD(WIZ_SERDES_RST, 24, 24); 80 static const struct reg_field pma_cmn_refclk_int_mode = 81 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 82 static const struct reg_field pma_cmn_refclk_mode = 83 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 84 static const struct reg_field pma_cmn_refclk_dig_div = 85 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); 86 static const struct reg_field pma_cmn_refclk1_dig_div = 87 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); 88 static const char * const output_clk_names[] = { 89 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk", 90 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk", 91 [TI_WIZ_REFCLK_DIG] = "refclk-dig", 92 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk", 93 }; 94 95 static const struct reg_field p_enable[WIZ_MAX_LANES] = { 96 REG_FIELD(WIZ_LANECTL(0), 30, 31), 97 REG_FIELD(WIZ_LANECTL(1), 30, 31), 98 REG_FIELD(WIZ_LANECTL(2), 30, 31), 99 REG_FIELD(WIZ_LANECTL(3), 30, 31), 100 }; 101 102 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; 103 104 static const struct reg_field p_align[WIZ_MAX_LANES] = { 105 REG_FIELD(WIZ_LANECTL(0), 29, 29), 106 REG_FIELD(WIZ_LANECTL(1), 29, 29), 107 REG_FIELD(WIZ_LANECTL(2), 29, 29), 108 REG_FIELD(WIZ_LANECTL(3), 29, 29), 109 }; 110 111 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { 112 REG_FIELD(WIZ_LANECTL(0), 28, 28), 113 REG_FIELD(WIZ_LANECTL(1), 28, 28), 114 REG_FIELD(WIZ_LANECTL(2), 28, 28), 115 REG_FIELD(WIZ_LANECTL(3), 28, 28), 116 }; 117 118 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { 119 REG_FIELD(WIZ_LANECTL(0), 24, 25), 120 REG_FIELD(WIZ_LANECTL(1), 24, 25), 121 REG_FIELD(WIZ_LANECTL(2), 24, 25), 122 REG_FIELD(WIZ_LANECTL(3), 24, 25), 123 }; 124 125 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { 126 REG_FIELD(WIZ_LANECTL(0), 22, 23), 127 REG_FIELD(WIZ_LANECTL(1), 22, 23), 128 REG_FIELD(WIZ_LANECTL(2), 22, 23), 129 REG_FIELD(WIZ_LANECTL(3), 22, 23), 130 }; 131 132 static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = { 133 REG_FIELD(WIZ_LANECTL(0), 20, 21), 134 REG_FIELD(WIZ_LANECTL(1), 20, 21), 135 REG_FIELD(WIZ_LANECTL(2), 20, 21), 136 REG_FIELD(WIZ_LANECTL(3), 20, 21), 137 }; 138 139 static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = { 140 REG_FIELD(WIZ_LANECTL(0), 6, 7), 141 REG_FIELD(WIZ_LANECTL(1), 6, 7), 142 REG_FIELD(WIZ_LANECTL(2), 6, 7), 143 REG_FIELD(WIZ_LANECTL(3), 6, 7), 144 }; 145 146 static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = { 147 REG_FIELD(WIZ_LANECTL(0), 18, 19), 148 REG_FIELD(WIZ_LANECTL(1), 18, 19), 149 REG_FIELD(WIZ_LANECTL(2), 18, 19), 150 REG_FIELD(WIZ_LANECTL(3), 18, 19), 151 }; 152 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { 153 REG_FIELD(WIZ_LANEDIV(0), 16, 22), 154 REG_FIELD(WIZ_LANEDIV(1), 16, 22), 155 REG_FIELD(WIZ_LANEDIV(2), 16, 22), 156 REG_FIELD(WIZ_LANEDIV(3), 16, 22), 157 }; 158 159 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { 160 REG_FIELD(WIZ_LANEDIV(0), 0, 8), 161 REG_FIELD(WIZ_LANEDIV(1), 0, 8), 162 REG_FIELD(WIZ_LANEDIV(2), 0, 8), 163 REG_FIELD(WIZ_LANEDIV(3), 0, 8), 164 }; 165 166 static const struct reg_field typec_ln10_swap = 167 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 168 169 struct wiz_clk_mux { 170 struct clk_hw hw; 171 struct regmap_field *field; 172 const u32 *table; 173 struct clk_init_data clk_data; 174 }; 175 176 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) 177 178 struct wiz_clk_divider { 179 struct clk_hw hw; 180 struct regmap_field *field; 181 const struct clk_div_table *table; 182 struct clk_init_data clk_data; 183 }; 184 185 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) 186 187 struct wiz_clk_mux_sel { 188 u32 table[WIZ_MAX_INPUT_CLOCKS]; 189 const char *node_name; 190 u32 num_parents; 191 u32 parents[WIZ_MAX_INPUT_CLOCKS]; 192 }; 193 194 struct wiz_clk_div_sel { 195 const struct clk_div_table *table; 196 const char *node_name; 197 }; 198 199 struct wiz_phy_en_refclk { 200 struct clk_hw hw; 201 struct regmap_field *phy_en_refclk; 202 struct clk_init_data clk_data; 203 }; 204 205 #define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw) 206 207 static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = { 208 { 209 /* 210 * Mux value to be configured for each of the input clocks 211 * in the order populated in device tree 212 */ 213 .table = { 1, 0 }, 214 .node_name = "pll0-refclk", 215 }, 216 { 217 .table = { 1, 0 }, 218 .node_name = "pll1-refclk", 219 }, 220 { 221 .table = { 1, 3, 0, 2 }, 222 .node_name = "refclk-dig", 223 }, 224 }; 225 226 static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 227 { 228 /* 229 * Mux value to be configured for each of the input clocks 230 * in the order populated in device tree 231 */ 232 .num_parents = 2, 233 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 234 .table = { 1, 0 }, 235 .node_name = "pll0-refclk", 236 }, 237 { 238 .num_parents = 2, 239 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 240 .table = { 1, 0 }, 241 .node_name = "pll1-refclk", 242 }, 243 { 244 .num_parents = 2, 245 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 246 .table = { 1, 0 }, 247 .node_name = "refclk-dig", 248 }, 249 }; 250 251 static const struct clk_div_table clk_div_table[] = { 252 { .val = 0, .div = 1, }, 253 { .val = 1, .div = 2, }, 254 { .val = 2, .div = 4, }, 255 { .val = 3, .div = 8, }, 256 { /* sentinel */ }, 257 }; 258 259 static const struct wiz_clk_div_sel clk_div_sel[] = { 260 { 261 .table = clk_div_table, 262 .node_name = "cmn-refclk-dig-div", 263 }, 264 { 265 .table = clk_div_table, 266 .node_name = "cmn-refclk1-dig-div", 267 }, 268 }; 269 270 enum wiz_type { 271 J721E_WIZ_16G, 272 J721E_WIZ_10G, 273 AM64_WIZ_10G, 274 }; 275 276 struct wiz_data { 277 enum wiz_type type; 278 const struct reg_field *refclk_dig_sel; 279 const struct reg_field *pma_cmn_refclk1_dig_div; 280 const struct wiz_clk_mux_sel *clk_mux_sel; 281 unsigned int clk_div_sel_num; 282 }; 283 284 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ 285 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 286 287 struct wiz { 288 struct regmap *regmap; 289 enum wiz_type type; 290 const struct wiz_clk_mux_sel *clk_mux_sel; 291 const struct wiz_clk_div_sel *clk_div_sel; 292 unsigned int clk_div_sel_num; 293 struct regmap_field *por_en; 294 struct regmap_field *phy_reset_n; 295 struct regmap_field *phy_en_refclk; 296 struct regmap_field *p_enable[WIZ_MAX_LANES]; 297 struct regmap_field *p_align[WIZ_MAX_LANES]; 298 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; 299 struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; 300 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; 301 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; 302 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; 303 struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES]; 304 struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; 305 struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; 306 struct regmap_field *pma_cmn_refclk_int_mode; 307 struct regmap_field *pma_cmn_refclk_mode; 308 struct regmap_field *pma_cmn_refclk_dig_div; 309 struct regmap_field *pma_cmn_refclk1_dig_div; 310 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; 311 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; 312 struct regmap_field *typec_ln10_swap; 313 314 struct device *dev; 315 u32 num_lanes; 316 struct platform_device *serdes_pdev; 317 struct reset_controller_dev wiz_phy_reset_dev; 318 struct gpio_desc *gpio_typec_dir; 319 int typec_dir_delay; 320 u32 lane_phy_type[WIZ_MAX_LANES]; 321 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; 322 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS]; 323 struct clk_onecell_data clk_data; 324 const struct wiz_data *data; 325 }; 326 327 static int wiz_reset(struct wiz *wiz) 328 { 329 int ret; 330 331 ret = regmap_field_write(wiz->por_en, 0x1); 332 if (ret) 333 return ret; 334 335 mdelay(1); 336 337 ret = regmap_field_write(wiz->por_en, 0x0); 338 if (ret) 339 return ret; 340 341 return 0; 342 } 343 344 static int wiz_p_mac_div_sel(struct wiz *wiz) 345 { 346 u32 num_lanes = wiz->num_lanes; 347 int ret; 348 int i; 349 350 for (i = 0; i < num_lanes; i++) { 351 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || 352 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII || 353 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 354 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); 355 if (ret) 356 return ret; 357 358 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); 359 if (ret) 360 return ret; 361 } 362 } 363 364 return 0; 365 } 366 367 static int wiz_mode_select(struct wiz *wiz) 368 { 369 u32 num_lanes = wiz->num_lanes; 370 enum wiz_lane_standard_mode mode; 371 int ret; 372 int i; 373 374 for (i = 0; i < num_lanes; i++) { 375 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) 376 mode = LANE_MODE_GEN1; 377 else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) 378 mode = LANE_MODE_GEN2; 379 else 380 continue; 381 382 if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 383 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); 384 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); 385 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3); 386 mode = LANE_MODE_GEN1; 387 } 388 389 ret = regmap_field_write(wiz->p_standard_mode[i], mode); 390 if (ret) 391 return ret; 392 } 393 394 return 0; 395 } 396 397 static int wiz_init_raw_interface(struct wiz *wiz, bool enable) 398 { 399 u32 num_lanes = wiz->num_lanes; 400 int i; 401 int ret; 402 403 for (i = 0; i < num_lanes; i++) { 404 ret = regmap_field_write(wiz->p_align[i], enable); 405 if (ret) 406 return ret; 407 408 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); 409 if (ret) 410 return ret; 411 } 412 413 return 0; 414 } 415 416 static int wiz_init(struct wiz *wiz) 417 { 418 struct device *dev = wiz->dev; 419 int ret; 420 421 ret = wiz_reset(wiz); 422 if (ret) { 423 dev_err(dev, "WIZ reset failed\n"); 424 return ret; 425 } 426 427 ret = wiz_mode_select(wiz); 428 if (ret) { 429 dev_err(dev, "WIZ mode select failed\n"); 430 return ret; 431 } 432 433 ret = wiz_p_mac_div_sel(wiz); 434 if (ret) { 435 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); 436 return ret; 437 } 438 439 ret = wiz_init_raw_interface(wiz, true); 440 if (ret) { 441 dev_err(dev, "WIZ interface initialization failed\n"); 442 return ret; 443 } 444 445 return 0; 446 } 447 448 static int wiz_regfield_init(struct wiz *wiz) 449 { 450 struct regmap *regmap = wiz->regmap; 451 int num_lanes = wiz->num_lanes; 452 struct device *dev = wiz->dev; 453 const struct wiz_data *data = wiz->data; 454 int i; 455 456 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); 457 if (IS_ERR(wiz->por_en)) { 458 dev_err(dev, "POR_EN reg field init failed\n"); 459 return PTR_ERR(wiz->por_en); 460 } 461 462 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, 463 phy_reset_n); 464 if (IS_ERR(wiz->phy_reset_n)) { 465 dev_err(dev, "PHY_RESET_N reg field init failed\n"); 466 return PTR_ERR(wiz->phy_reset_n); 467 } 468 469 wiz->pma_cmn_refclk_int_mode = 470 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); 471 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { 472 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); 473 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); 474 } 475 476 wiz->pma_cmn_refclk_mode = 477 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); 478 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { 479 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); 480 return PTR_ERR(wiz->pma_cmn_refclk_mode); 481 } 482 483 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] = 484 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div); 485 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) { 486 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); 487 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); 488 } 489 490 if (data->pma_cmn_refclk1_dig_div) { 491 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = 492 devm_regmap_field_alloc(dev, regmap, 493 *data->pma_cmn_refclk1_dig_div); 494 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { 495 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); 496 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); 497 } 498 } 499 500 wiz->mux_sel_field[PLL0_REFCLK] = 501 devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel); 502 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { 503 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); 504 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); 505 } 506 507 wiz->mux_sel_field[PLL1_REFCLK] = 508 devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel); 509 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { 510 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); 511 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); 512 } 513 514 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, regmap, 515 *data->refclk_dig_sel); 516 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { 517 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); 518 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); 519 } 520 521 for (i = 0; i < num_lanes; i++) { 522 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, 523 p_enable[i]); 524 if (IS_ERR(wiz->p_enable[i])) { 525 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 526 return PTR_ERR(wiz->p_enable[i]); 527 } 528 529 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, 530 p_align[i]); 531 if (IS_ERR(wiz->p_align[i])) { 532 dev_err(dev, "P%d_ALIGN reg field init failed\n", i); 533 return PTR_ERR(wiz->p_align[i]); 534 } 535 536 wiz->p_raw_auto_start[i] = 537 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); 538 if (IS_ERR(wiz->p_raw_auto_start[i])) { 539 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", 540 i); 541 return PTR_ERR(wiz->p_raw_auto_start[i]); 542 } 543 544 wiz->p_standard_mode[i] = 545 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); 546 if (IS_ERR(wiz->p_standard_mode[i])) { 547 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", 548 i); 549 return PTR_ERR(wiz->p_standard_mode[i]); 550 } 551 552 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); 553 if (IS_ERR(wiz->p0_fullrt_div[i])) { 554 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i); 555 return PTR_ERR(wiz->p0_fullrt_div[i]); 556 } 557 558 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]); 559 if (IS_ERR(wiz->p0_mac_src_sel[i])) { 560 dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i); 561 return PTR_ERR(wiz->p0_mac_src_sel[i]); 562 } 563 564 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]); 565 if (IS_ERR(wiz->p0_rxfclk_sel[i])) { 566 dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i); 567 return PTR_ERR(wiz->p0_rxfclk_sel[i]); 568 } 569 570 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]); 571 if (IS_ERR(wiz->p0_refclk_sel[i])) { 572 dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i); 573 return PTR_ERR(wiz->p0_refclk_sel[i]); 574 } 575 576 wiz->p_mac_div_sel0[i] = 577 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); 578 if (IS_ERR(wiz->p_mac_div_sel0[i])) { 579 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n", 580 i); 581 return PTR_ERR(wiz->p_mac_div_sel0[i]); 582 } 583 584 wiz->p_mac_div_sel1[i] = 585 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]); 586 if (IS_ERR(wiz->p_mac_div_sel1[i])) { 587 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n", 588 i); 589 return PTR_ERR(wiz->p_mac_div_sel1[i]); 590 } 591 } 592 593 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, 594 typec_ln10_swap); 595 if (IS_ERR(wiz->typec_ln10_swap)) { 596 dev_err(dev, "LN10_SWAP reg field init failed\n"); 597 return PTR_ERR(wiz->typec_ln10_swap); 598 } 599 600 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); 601 if (IS_ERR(wiz->phy_en_refclk)) { 602 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n"); 603 return PTR_ERR(wiz->phy_en_refclk); 604 } 605 606 return 0; 607 } 608 609 static int wiz_phy_en_refclk_enable(struct clk_hw *hw) 610 { 611 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 612 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 613 614 regmap_field_write(phy_en_refclk, 1); 615 616 return 0; 617 } 618 619 static void wiz_phy_en_refclk_disable(struct clk_hw *hw) 620 { 621 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 622 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 623 624 regmap_field_write(phy_en_refclk, 0); 625 } 626 627 static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw) 628 { 629 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 630 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 631 int val; 632 633 regmap_field_read(phy_en_refclk, &val); 634 635 return !!val; 636 } 637 638 static const struct clk_ops wiz_phy_en_refclk_ops = { 639 .enable = wiz_phy_en_refclk_enable, 640 .disable = wiz_phy_en_refclk_disable, 641 .is_enabled = wiz_phy_en_refclk_is_enabled, 642 }; 643 644 static int wiz_phy_en_refclk_register(struct wiz *wiz) 645 { 646 struct wiz_phy_en_refclk *wiz_phy_en_refclk; 647 struct device *dev = wiz->dev; 648 struct clk_init_data *init; 649 struct clk *clk; 650 651 wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL); 652 if (!wiz_phy_en_refclk) 653 return -ENOMEM; 654 655 init = &wiz_phy_en_refclk->clk_data; 656 657 init->ops = &wiz_phy_en_refclk_ops; 658 init->flags = 0; 659 init->name = output_clk_names[TI_WIZ_PHY_EN_REFCLK]; 660 661 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; 662 wiz_phy_en_refclk->hw.init = init; 663 664 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); 665 if (IS_ERR(clk)) 666 return PTR_ERR(clk); 667 668 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk; 669 670 return 0; 671 } 672 673 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) 674 { 675 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 676 struct regmap_field *field = mux->field; 677 unsigned int val; 678 679 regmap_field_read(field, &val); 680 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val); 681 } 682 683 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) 684 { 685 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 686 struct regmap_field *field = mux->field; 687 int val; 688 689 val = mux->table[index]; 690 return regmap_field_write(field, val); 691 } 692 693 static const struct clk_ops wiz_clk_mux_ops = { 694 .set_parent = wiz_clk_mux_set_parent, 695 .get_parent = wiz_clk_mux_get_parent, 696 }; 697 698 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field, 699 const struct wiz_clk_mux_sel *mux_sel, int clk_index) 700 { 701 struct device *dev = wiz->dev; 702 struct clk_init_data *init; 703 const char **parent_names; 704 unsigned int num_parents; 705 struct wiz_clk_mux *mux; 706 char clk_name[100]; 707 struct clk *clk; 708 int ret = 0, i; 709 710 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 711 if (!mux) 712 return -ENOMEM; 713 714 num_parents = mux_sel->num_parents; 715 716 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); 717 if (!parent_names) 718 return -ENOMEM; 719 720 for (i = 0; i < num_parents; i++) { 721 clk = wiz->input_clks[mux_sel->parents[i]]; 722 if (IS_ERR_OR_NULL(clk)) { 723 dev_err(dev, "Failed to get parent clk for %s\n", 724 output_clk_names[clk_index]); 725 ret = -EINVAL; 726 goto err; 727 } 728 parent_names[i] = __clk_get_name(clk); 729 } 730 731 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]); 732 733 init = &mux->clk_data; 734 735 init->ops = &wiz_clk_mux_ops; 736 init->flags = CLK_SET_RATE_NO_REPARENT; 737 init->parent_names = parent_names; 738 init->num_parents = num_parents; 739 init->name = clk_name; 740 741 mux->field = field; 742 mux->table = mux_sel->table; 743 mux->hw.init = init; 744 745 clk = devm_clk_register(dev, &mux->hw); 746 if (IS_ERR(clk)) { 747 ret = PTR_ERR(clk); 748 goto err; 749 } 750 751 wiz->output_clks[clk_index] = clk; 752 753 err: 754 kfree(parent_names); 755 756 return ret; 757 } 758 759 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node, 760 struct regmap_field *field, const u32 *table) 761 { 762 struct device *dev = wiz->dev; 763 struct clk_init_data *init; 764 const char **parent_names; 765 unsigned int num_parents; 766 struct wiz_clk_mux *mux; 767 char clk_name[100]; 768 struct clk *clk; 769 int ret; 770 771 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 772 if (!mux) 773 return -ENOMEM; 774 775 num_parents = of_clk_get_parent_count(node); 776 if (num_parents < 2) { 777 dev_err(dev, "SERDES clock must have parents\n"); 778 return -EINVAL; 779 } 780 781 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 782 GFP_KERNEL); 783 if (!parent_names) 784 return -ENOMEM; 785 786 of_clk_parent_fill(node, parent_names, num_parents); 787 788 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 789 node->name); 790 791 init = &mux->clk_data; 792 793 init->ops = &wiz_clk_mux_ops; 794 init->flags = CLK_SET_RATE_NO_REPARENT; 795 init->parent_names = parent_names; 796 init->num_parents = num_parents; 797 init->name = clk_name; 798 799 mux->field = field; 800 mux->table = table; 801 mux->hw.init = init; 802 803 clk = devm_clk_register(dev, &mux->hw); 804 if (IS_ERR(clk)) 805 return PTR_ERR(clk); 806 807 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 808 if (ret) 809 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 810 811 return ret; 812 } 813 814 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, 815 unsigned long parent_rate) 816 { 817 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 818 struct regmap_field *field = div->field; 819 int val; 820 821 regmap_field_read(field, &val); 822 823 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); 824 } 825 826 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 827 unsigned long *prate) 828 { 829 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 830 831 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); 832 } 833 834 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 835 unsigned long parent_rate) 836 { 837 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 838 struct regmap_field *field = div->field; 839 int val; 840 841 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); 842 if (val < 0) 843 return val; 844 845 return regmap_field_write(field, val); 846 } 847 848 static const struct clk_ops wiz_clk_div_ops = { 849 .recalc_rate = wiz_clk_div_recalc_rate, 850 .round_rate = wiz_clk_div_round_rate, 851 .set_rate = wiz_clk_div_set_rate, 852 }; 853 854 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, 855 struct regmap_field *field, 856 const struct clk_div_table *table) 857 { 858 struct device *dev = wiz->dev; 859 struct wiz_clk_divider *div; 860 struct clk_init_data *init; 861 const char **parent_names; 862 char clk_name[100]; 863 struct clk *clk; 864 int ret; 865 866 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 867 if (!div) 868 return -ENOMEM; 869 870 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 871 node->name); 872 873 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 874 if (!parent_names) 875 return -ENOMEM; 876 877 of_clk_parent_fill(node, parent_names, 1); 878 879 init = &div->clk_data; 880 881 init->ops = &wiz_clk_div_ops; 882 init->flags = 0; 883 init->parent_names = parent_names; 884 init->num_parents = 1; 885 init->name = clk_name; 886 887 div->field = field; 888 div->table = table; 889 div->hw.init = init; 890 891 clk = devm_clk_register(dev, &div->hw); 892 if (IS_ERR(clk)) 893 return PTR_ERR(clk); 894 895 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 896 if (ret) 897 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 898 899 return ret; 900 } 901 902 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) 903 { 904 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 905 struct device *dev = wiz->dev; 906 struct device_node *clk_node; 907 int i; 908 909 if (wiz->type == AM64_WIZ_10G) { 910 of_clk_del_provider(dev->of_node); 911 return; 912 } 913 914 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 915 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); 916 of_clk_del_provider(clk_node); 917 of_node_put(clk_node); 918 } 919 920 for (i = 0; i < wiz->clk_div_sel_num; i++) { 921 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name); 922 of_clk_del_provider(clk_node); 923 of_node_put(clk_node); 924 } 925 926 of_clk_del_provider(wiz->dev->of_node); 927 } 928 929 static int wiz_clock_register(struct wiz *wiz) 930 { 931 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 932 struct device *dev = wiz->dev; 933 struct device_node *node = dev->of_node; 934 int clk_index; 935 int ret; 936 int i; 937 938 if (wiz->type != AM64_WIZ_10G) 939 return 0; 940 941 clk_index = TI_WIZ_PLL0_REFCLK; 942 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { 943 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); 944 if (ret) { 945 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]); 946 return ret; 947 } 948 } 949 950 ret = wiz_phy_en_refclk_register(wiz); 951 if (ret) { 952 dev_err(dev, "Failed to add phy-en-refclk\n"); 953 return ret; 954 } 955 956 wiz->clk_data.clks = wiz->output_clks; 957 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS; 958 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data); 959 if (ret) 960 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 961 962 return ret; 963 } 964 965 static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 966 { 967 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 968 struct device *dev = wiz->dev; 969 struct device_node *clk_node; 970 const char *node_name; 971 unsigned long rate; 972 struct clk *clk; 973 int ret; 974 int i; 975 976 clk = devm_clk_get(dev, "core_ref_clk"); 977 if (IS_ERR(clk)) { 978 dev_err(dev, "core_ref_clk clock not found\n"); 979 ret = PTR_ERR(clk); 980 return ret; 981 } 982 wiz->input_clks[WIZ_CORE_REFCLK] = clk; 983 984 rate = clk_get_rate(clk); 985 if (rate >= 100000000) 986 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 987 else 988 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 989 990 clk = devm_clk_get(dev, "ext_ref_clk"); 991 if (IS_ERR(clk)) { 992 dev_err(dev, "ext_ref_clk clock not found\n"); 993 ret = PTR_ERR(clk); 994 return ret; 995 } 996 wiz->input_clks[WIZ_EXT_REFCLK] = clk; 997 998 rate = clk_get_rate(clk); 999 if (rate >= 100000000) 1000 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 1001 else 1002 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 1003 1004 if (wiz->type == AM64_WIZ_10G) { 1005 ret = wiz_clock_register(wiz); 1006 if (ret) 1007 dev_err(dev, "Failed to register wiz clocks\n"); 1008 return ret; 1009 } 1010 1011 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 1012 node_name = clk_mux_sel[i].node_name; 1013 clk_node = of_get_child_by_name(node, node_name); 1014 if (!clk_node) { 1015 dev_err(dev, "Unable to get %s node\n", node_name); 1016 ret = -EINVAL; 1017 goto err; 1018 } 1019 1020 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i], 1021 clk_mux_sel[i].table); 1022 if (ret) { 1023 dev_err(dev, "Failed to register %s clock\n", 1024 node_name); 1025 of_node_put(clk_node); 1026 goto err; 1027 } 1028 1029 of_node_put(clk_node); 1030 } 1031 1032 for (i = 0; i < wiz->clk_div_sel_num; i++) { 1033 node_name = clk_div_sel[i].node_name; 1034 clk_node = of_get_child_by_name(node, node_name); 1035 if (!clk_node) { 1036 dev_err(dev, "Unable to get %s node\n", node_name); 1037 ret = -EINVAL; 1038 goto err; 1039 } 1040 1041 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i], 1042 clk_div_sel[i].table); 1043 if (ret) { 1044 dev_err(dev, "Failed to register %s clock\n", 1045 node_name); 1046 of_node_put(clk_node); 1047 goto err; 1048 } 1049 1050 of_node_put(clk_node); 1051 } 1052 1053 return 0; 1054 err: 1055 wiz_clock_cleanup(wiz, node); 1056 1057 return ret; 1058 } 1059 1060 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, 1061 unsigned long id) 1062 { 1063 struct device *dev = rcdev->dev; 1064 struct wiz *wiz = dev_get_drvdata(dev); 1065 int ret = 0; 1066 1067 if (id == 0) { 1068 ret = regmap_field_write(wiz->phy_reset_n, false); 1069 return ret; 1070 } 1071 1072 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); 1073 return ret; 1074 } 1075 1076 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) 1077 { 1078 switch (wiz->type) { 1079 case AM64_WIZ_10G: 1080 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) 1081 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); 1082 break; 1083 case J721E_WIZ_10G: 1084 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) 1085 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); 1086 break; 1087 default: 1088 return 0; 1089 } 1090 return 0; 1091 } 1092 1093 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, 1094 unsigned long id) 1095 { 1096 struct device *dev = rcdev->dev; 1097 struct wiz *wiz = dev_get_drvdata(dev); 1098 int ret; 1099 1100 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ 1101 if (id == 0 && wiz->gpio_typec_dir) { 1102 if (wiz->typec_dir_delay) 1103 msleep_interruptible(wiz->typec_dir_delay); 1104 1105 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) 1106 regmap_field_write(wiz->typec_ln10_swap, 1); 1107 else 1108 regmap_field_write(wiz->typec_ln10_swap, 0); 1109 } 1110 1111 if (id == 0) { 1112 ret = regmap_field_write(wiz->phy_reset_n, true); 1113 return ret; 1114 } 1115 1116 ret = wiz_phy_fullrt_div(wiz, id - 1); 1117 if (ret) 1118 return ret; 1119 1120 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) 1121 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); 1122 else 1123 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); 1124 1125 return ret; 1126 } 1127 1128 static const struct reset_control_ops wiz_phy_reset_ops = { 1129 .assert = wiz_phy_reset_assert, 1130 .deassert = wiz_phy_reset_deassert, 1131 }; 1132 1133 static const struct regmap_config wiz_regmap_config = { 1134 .reg_bits = 32, 1135 .val_bits = 32, 1136 .reg_stride = 4, 1137 .fast_io = true, 1138 }; 1139 1140 static struct wiz_data j721e_16g_data = { 1141 .type = J721E_WIZ_16G, 1142 .refclk_dig_sel = &refclk_dig_sel_16g, 1143 .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div, 1144 .clk_mux_sel = clk_mux_sel_16g, 1145 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G, 1146 }; 1147 1148 static struct wiz_data j721e_10g_data = { 1149 .type = J721E_WIZ_10G, 1150 .refclk_dig_sel = &refclk_dig_sel_10g, 1151 .clk_mux_sel = clk_mux_sel_10g, 1152 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1153 }; 1154 1155 static struct wiz_data am64_10g_data = { 1156 .type = AM64_WIZ_10G, 1157 .refclk_dig_sel = &refclk_dig_sel_10g, 1158 .clk_mux_sel = clk_mux_sel_10g, 1159 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1160 }; 1161 1162 static const struct of_device_id wiz_id_table[] = { 1163 { 1164 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, 1165 }, 1166 { 1167 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data, 1168 }, 1169 { 1170 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data, 1171 }, 1172 {} 1173 }; 1174 MODULE_DEVICE_TABLE(of, wiz_id_table); 1175 1176 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) 1177 { 1178 struct device_node *serdes, *subnode; 1179 1180 serdes = of_get_child_by_name(dev->of_node, "serdes"); 1181 if (!serdes) { 1182 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); 1183 return -EINVAL; 1184 } 1185 1186 for_each_child_of_node(serdes, subnode) { 1187 u32 reg, num_lanes = 1, phy_type = PHY_NONE; 1188 int ret, i; 1189 1190 if (!(of_node_name_eq(subnode, "phy") || 1191 of_node_name_eq(subnode, "link"))) 1192 continue; 1193 1194 ret = of_property_read_u32(subnode, "reg", ®); 1195 if (ret) { 1196 of_node_put(subnode); 1197 dev_err(dev, 1198 "%s: Reading \"reg\" from \"%s\" failed: %d\n", 1199 __func__, subnode->name, ret); 1200 return ret; 1201 } 1202 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); 1203 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); 1204 1205 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, 1206 reg, reg + num_lanes - 1, phy_type); 1207 1208 for (i = reg; i < reg + num_lanes; i++) 1209 wiz->lane_phy_type[i] = phy_type; 1210 } 1211 1212 return 0; 1213 } 1214 1215 static int wiz_probe(struct platform_device *pdev) 1216 { 1217 struct reset_controller_dev *phy_reset_dev; 1218 struct device *dev = &pdev->dev; 1219 struct device_node *node = dev->of_node; 1220 struct platform_device *serdes_pdev; 1221 bool already_configured = false; 1222 struct device_node *child_node; 1223 struct regmap *regmap; 1224 struct resource res; 1225 void __iomem *base; 1226 struct wiz *wiz; 1227 int ret, val, i; 1228 u32 num_lanes; 1229 const struct wiz_data *data; 1230 1231 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); 1232 if (!wiz) 1233 return -ENOMEM; 1234 1235 data = of_device_get_match_data(dev); 1236 if (!data) { 1237 dev_err(dev, "NULL device data\n"); 1238 return -EINVAL; 1239 } 1240 1241 wiz->data = data; 1242 wiz->type = data->type; 1243 1244 child_node = of_get_child_by_name(node, "serdes"); 1245 if (!child_node) { 1246 dev_err(dev, "Failed to get SERDES child DT node\n"); 1247 return -ENODEV; 1248 } 1249 1250 ret = of_address_to_resource(child_node, 0, &res); 1251 if (ret) { 1252 dev_err(dev, "Failed to get memory resource\n"); 1253 goto err_addr_to_resource; 1254 } 1255 1256 base = devm_ioremap(dev, res.start, resource_size(&res)); 1257 if (!base) { 1258 ret = -ENOMEM; 1259 goto err_addr_to_resource; 1260 } 1261 1262 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); 1263 if (IS_ERR(regmap)) { 1264 dev_err(dev, "Failed to initialize regmap\n"); 1265 ret = PTR_ERR(regmap); 1266 goto err_addr_to_resource; 1267 } 1268 1269 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 1270 if (ret) { 1271 dev_err(dev, "Failed to read num-lanes property\n"); 1272 goto err_addr_to_resource; 1273 } 1274 1275 if (num_lanes > WIZ_MAX_LANES) { 1276 dev_err(dev, "Cannot support %d lanes\n", num_lanes); 1277 ret = -ENODEV; 1278 goto err_addr_to_resource; 1279 } 1280 1281 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", 1282 GPIOD_IN); 1283 if (IS_ERR(wiz->gpio_typec_dir)) { 1284 ret = PTR_ERR(wiz->gpio_typec_dir); 1285 if (ret != -EPROBE_DEFER) 1286 dev_err(dev, "Failed to request typec-dir gpio: %d\n", 1287 ret); 1288 goto err_addr_to_resource; 1289 } 1290 1291 if (wiz->gpio_typec_dir) { 1292 ret = of_property_read_u32(node, "typec-dir-debounce-ms", 1293 &wiz->typec_dir_delay); 1294 if (ret && ret != -EINVAL) { 1295 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1296 goto err_addr_to_resource; 1297 } 1298 1299 /* use min. debounce from Type-C spec if not provided in DT */ 1300 if (ret == -EINVAL) 1301 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; 1302 1303 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 1304 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 1305 ret = -EINVAL; 1306 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1307 goto err_addr_to_resource; 1308 } 1309 } 1310 1311 ret = wiz_get_lane_phy_types(dev, wiz); 1312 if (ret) 1313 return ret; 1314 1315 wiz->dev = dev; 1316 wiz->regmap = regmap; 1317 wiz->num_lanes = num_lanes; 1318 wiz->clk_mux_sel = data->clk_mux_sel; 1319 wiz->clk_div_sel = clk_div_sel; 1320 wiz->clk_div_sel_num = data->clk_div_sel_num; 1321 1322 platform_set_drvdata(pdev, wiz); 1323 1324 ret = wiz_regfield_init(wiz); 1325 if (ret) { 1326 dev_err(dev, "Failed to initialize regfields\n"); 1327 goto err_addr_to_resource; 1328 } 1329 1330 phy_reset_dev = &wiz->wiz_phy_reset_dev; 1331 phy_reset_dev->dev = dev; 1332 phy_reset_dev->ops = &wiz_phy_reset_ops, 1333 phy_reset_dev->owner = THIS_MODULE, 1334 phy_reset_dev->of_node = node; 1335 /* Reset for each of the lane and one for the entire SERDES */ 1336 phy_reset_dev->nr_resets = num_lanes + 1; 1337 1338 ret = devm_reset_controller_register(dev, phy_reset_dev); 1339 if (ret < 0) { 1340 dev_warn(dev, "Failed to register reset controller\n"); 1341 goto err_addr_to_resource; 1342 } 1343 1344 pm_runtime_enable(dev); 1345 ret = pm_runtime_get_sync(dev); 1346 if (ret < 0) { 1347 dev_err(dev, "pm_runtime_get_sync failed\n"); 1348 goto err_get_sync; 1349 } 1350 1351 ret = wiz_clock_init(wiz, node); 1352 if (ret < 0) { 1353 dev_warn(dev, "Failed to initialize clocks\n"); 1354 goto err_get_sync; 1355 } 1356 1357 for (i = 0; i < wiz->num_lanes; i++) { 1358 regmap_field_read(wiz->p_enable[i], &val); 1359 if (val & (P_ENABLE | P_ENABLE_FORCE)) { 1360 already_configured = true; 1361 break; 1362 } 1363 } 1364 1365 if (!already_configured) { 1366 ret = wiz_init(wiz); 1367 if (ret) { 1368 dev_err(dev, "WIZ initialization failed\n"); 1369 goto err_wiz_init; 1370 } 1371 } 1372 1373 serdes_pdev = of_platform_device_create(child_node, NULL, dev); 1374 if (!serdes_pdev) { 1375 dev_WARN(dev, "Unable to create SERDES platform device\n"); 1376 ret = -ENOMEM; 1377 goto err_wiz_init; 1378 } 1379 wiz->serdes_pdev = serdes_pdev; 1380 1381 of_node_put(child_node); 1382 return 0; 1383 1384 err_wiz_init: 1385 wiz_clock_cleanup(wiz, node); 1386 1387 err_get_sync: 1388 pm_runtime_put(dev); 1389 pm_runtime_disable(dev); 1390 1391 err_addr_to_resource: 1392 of_node_put(child_node); 1393 1394 return ret; 1395 } 1396 1397 static int wiz_remove(struct platform_device *pdev) 1398 { 1399 struct device *dev = &pdev->dev; 1400 struct device_node *node = dev->of_node; 1401 struct platform_device *serdes_pdev; 1402 struct wiz *wiz; 1403 1404 wiz = dev_get_drvdata(dev); 1405 serdes_pdev = wiz->serdes_pdev; 1406 1407 of_platform_device_destroy(&serdes_pdev->dev, NULL); 1408 wiz_clock_cleanup(wiz, node); 1409 pm_runtime_put(dev); 1410 pm_runtime_disable(dev); 1411 1412 return 0; 1413 } 1414 1415 static struct platform_driver wiz_driver = { 1416 .probe = wiz_probe, 1417 .remove = wiz_remove, 1418 .driver = { 1419 .name = "wiz", 1420 .of_match_table = wiz_id_table, 1421 }, 1422 }; 1423 module_platform_driver(wiz_driver); 1424 1425 MODULE_AUTHOR("Texas Instruments Inc."); 1426 MODULE_DESCRIPTION("TI J721E WIZ driver"); 1427 MODULE_LICENSE("GPL v2"); 1428