1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Wrapper driver for SERDES used in J721E 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-ti.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/gpio.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/mux/consumer.h> 20 #include <linux/of_address.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/reset-controller.h> 26 27 #define REF_CLK_19_2MHZ 19200000 28 #define REF_CLK_25MHZ 25000000 29 #define REF_CLK_100MHZ 100000000 30 #define REF_CLK_156_25MHZ 156250000 31 32 /* SCM offsets */ 33 #define SERDES_SUP_CTRL 0x4400 34 35 /* SERDES offsets */ 36 #define WIZ_SERDES_CTRL 0x404 37 #define WIZ_SERDES_TOP_CTRL 0x408 38 #define WIZ_SERDES_RST 0x40c 39 #define WIZ_SERDES_TYPEC 0x410 40 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) 41 #define WIZ_LANEDIV(n) (0x484 + (0x40 * (n))) 42 43 #define WIZ_MAX_INPUT_CLOCKS 4 44 /* To include mux clocks, divider clocks and gate clocks */ 45 #define WIZ_MAX_OUTPUT_CLOCKS 32 46 47 #define WIZ_MAX_LANES 4 48 #define WIZ_MUX_NUM_CLOCKS 3 49 #define WIZ_DIV_NUM_CLOCKS_16G 2 50 #define WIZ_DIV_NUM_CLOCKS_10G 1 51 52 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) 53 54 enum wiz_lane_standard_mode { 55 LANE_MODE_GEN1, 56 LANE_MODE_GEN2, 57 LANE_MODE_GEN3, 58 LANE_MODE_GEN4, 59 }; 60 61 enum wiz_refclk_mux_sel { 62 PLL0_REFCLK, 63 PLL1_REFCLK, 64 REFCLK_DIG, 65 }; 66 67 enum wiz_refclk_div_sel { 68 CMN_REFCLK_DIG_DIV, 69 CMN_REFCLK1_DIG_DIV, 70 }; 71 72 enum wiz_clock_input { 73 WIZ_CORE_REFCLK, 74 WIZ_EXT_REFCLK, 75 WIZ_CORE_REFCLK1, 76 WIZ_EXT_REFCLK1, 77 }; 78 79 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); 80 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); 81 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); 82 static const struct reg_field pll1_refclk_mux_sel = 83 REG_FIELD(WIZ_SERDES_RST, 29, 29); 84 static const struct reg_field pll0_refclk_mux_sel = 85 REG_FIELD(WIZ_SERDES_RST, 28, 28); 86 static const struct reg_field refclk_dig_sel_16g = 87 REG_FIELD(WIZ_SERDES_RST, 24, 25); 88 static const struct reg_field refclk_dig_sel_10g = 89 REG_FIELD(WIZ_SERDES_RST, 24, 24); 90 static const struct reg_field pma_cmn_refclk_int_mode = 91 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 92 static const struct reg_field pma_cmn_refclk_mode = 93 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 94 static const struct reg_field pma_cmn_refclk_dig_div = 95 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); 96 static const struct reg_field pma_cmn_refclk1_dig_div = 97 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); 98 99 static const struct reg_field sup_pll0_refclk_mux_sel = 100 REG_FIELD(SERDES_SUP_CTRL, 0, 1); 101 static const struct reg_field sup_pll1_refclk_mux_sel = 102 REG_FIELD(SERDES_SUP_CTRL, 2, 3); 103 static const struct reg_field sup_pma_cmn_refclk1_int_mode = 104 REG_FIELD(SERDES_SUP_CTRL, 4, 5); 105 static const struct reg_field sup_refclk_dig_sel_10g = 106 REG_FIELD(SERDES_SUP_CTRL, 6, 7); 107 static const struct reg_field sup_legacy_clk_override = 108 REG_FIELD(SERDES_SUP_CTRL, 8, 8); 109 110 static const char * const output_clk_names[] = { 111 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk", 112 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk", 113 [TI_WIZ_REFCLK_DIG] = "refclk-dig", 114 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk", 115 }; 116 117 static const struct reg_field p_enable[WIZ_MAX_LANES] = { 118 REG_FIELD(WIZ_LANECTL(0), 30, 31), 119 REG_FIELD(WIZ_LANECTL(1), 30, 31), 120 REG_FIELD(WIZ_LANECTL(2), 30, 31), 121 REG_FIELD(WIZ_LANECTL(3), 30, 31), 122 }; 123 124 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; 125 126 static const struct reg_field p_align[WIZ_MAX_LANES] = { 127 REG_FIELD(WIZ_LANECTL(0), 29, 29), 128 REG_FIELD(WIZ_LANECTL(1), 29, 29), 129 REG_FIELD(WIZ_LANECTL(2), 29, 29), 130 REG_FIELD(WIZ_LANECTL(3), 29, 29), 131 }; 132 133 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { 134 REG_FIELD(WIZ_LANECTL(0), 28, 28), 135 REG_FIELD(WIZ_LANECTL(1), 28, 28), 136 REG_FIELD(WIZ_LANECTL(2), 28, 28), 137 REG_FIELD(WIZ_LANECTL(3), 28, 28), 138 }; 139 140 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { 141 REG_FIELD(WIZ_LANECTL(0), 24, 25), 142 REG_FIELD(WIZ_LANECTL(1), 24, 25), 143 REG_FIELD(WIZ_LANECTL(2), 24, 25), 144 REG_FIELD(WIZ_LANECTL(3), 24, 25), 145 }; 146 147 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { 148 REG_FIELD(WIZ_LANECTL(0), 22, 23), 149 REG_FIELD(WIZ_LANECTL(1), 22, 23), 150 REG_FIELD(WIZ_LANECTL(2), 22, 23), 151 REG_FIELD(WIZ_LANECTL(3), 22, 23), 152 }; 153 154 static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = { 155 REG_FIELD(WIZ_LANECTL(0), 20, 21), 156 REG_FIELD(WIZ_LANECTL(1), 20, 21), 157 REG_FIELD(WIZ_LANECTL(2), 20, 21), 158 REG_FIELD(WIZ_LANECTL(3), 20, 21), 159 }; 160 161 static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = { 162 REG_FIELD(WIZ_LANECTL(0), 6, 7), 163 REG_FIELD(WIZ_LANECTL(1), 6, 7), 164 REG_FIELD(WIZ_LANECTL(2), 6, 7), 165 REG_FIELD(WIZ_LANECTL(3), 6, 7), 166 }; 167 168 static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = { 169 REG_FIELD(WIZ_LANECTL(0), 18, 19), 170 REG_FIELD(WIZ_LANECTL(1), 18, 19), 171 REG_FIELD(WIZ_LANECTL(2), 18, 19), 172 REG_FIELD(WIZ_LANECTL(3), 18, 19), 173 }; 174 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { 175 REG_FIELD(WIZ_LANEDIV(0), 16, 22), 176 REG_FIELD(WIZ_LANEDIV(1), 16, 22), 177 REG_FIELD(WIZ_LANEDIV(2), 16, 22), 178 REG_FIELD(WIZ_LANEDIV(3), 16, 22), 179 }; 180 181 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { 182 REG_FIELD(WIZ_LANEDIV(0), 0, 8), 183 REG_FIELD(WIZ_LANEDIV(1), 0, 8), 184 REG_FIELD(WIZ_LANEDIV(2), 0, 8), 185 REG_FIELD(WIZ_LANEDIV(3), 0, 8), 186 }; 187 188 static const struct reg_field typec_ln10_swap = 189 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 190 191 struct wiz_clk_mux { 192 struct clk_hw hw; 193 struct regmap_field *field; 194 const u32 *table; 195 struct clk_init_data clk_data; 196 }; 197 198 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) 199 200 struct wiz_clk_divider { 201 struct clk_hw hw; 202 struct regmap_field *field; 203 const struct clk_div_table *table; 204 struct clk_init_data clk_data; 205 }; 206 207 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) 208 209 struct wiz_clk_mux_sel { 210 u32 table[WIZ_MAX_INPUT_CLOCKS]; 211 const char *node_name; 212 u32 num_parents; 213 u32 parents[WIZ_MAX_INPUT_CLOCKS]; 214 }; 215 216 struct wiz_clk_div_sel { 217 const struct clk_div_table *table; 218 const char *node_name; 219 }; 220 221 struct wiz_phy_en_refclk { 222 struct clk_hw hw; 223 struct regmap_field *phy_en_refclk; 224 struct clk_init_data clk_data; 225 }; 226 227 #define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw) 228 229 static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = { 230 { 231 /* 232 * Mux value to be configured for each of the input clocks 233 * in the order populated in device tree 234 */ 235 .table = { 1, 0 }, 236 .node_name = "pll0-refclk", 237 }, 238 { 239 .table = { 1, 0 }, 240 .node_name = "pll1-refclk", 241 }, 242 { 243 .table = { 1, 3, 0, 2 }, 244 .node_name = "refclk-dig", 245 }, 246 }; 247 248 static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 249 { 250 /* 251 * Mux value to be configured for each of the input clocks 252 * in the order populated in device tree 253 */ 254 .num_parents = 2, 255 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 256 .table = { 1, 0 }, 257 .node_name = "pll0-refclk", 258 }, 259 { 260 .num_parents = 2, 261 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 262 .table = { 1, 0 }, 263 .node_name = "pll1-refclk", 264 }, 265 { 266 .num_parents = 2, 267 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 268 .table = { 1, 0 }, 269 .node_name = "refclk-dig", 270 }, 271 }; 272 273 static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = { 274 { 275 .num_parents = 3, 276 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 277 .table = { 2, 3, 0 }, 278 .node_name = "pll0-refclk", 279 }, 280 { 281 .num_parents = 3, 282 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 283 .table = { 2, 3, 0 }, 284 .node_name = "pll1-refclk", 285 }, 286 { 287 .num_parents = 3, 288 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 289 .table = { 2, 3, 0 }, 290 .node_name = "refclk-dig", 291 }, 292 }; 293 294 static const struct clk_div_table clk_div_table[] = { 295 { .val = 0, .div = 1, }, 296 { .val = 1, .div = 2, }, 297 { .val = 2, .div = 4, }, 298 { .val = 3, .div = 8, }, 299 { /* sentinel */ }, 300 }; 301 302 static const struct wiz_clk_div_sel clk_div_sel[] = { 303 { 304 .table = clk_div_table, 305 .node_name = "cmn-refclk-dig-div", 306 }, 307 { 308 .table = clk_div_table, 309 .node_name = "cmn-refclk1-dig-div", 310 }, 311 }; 312 313 enum wiz_type { 314 J721E_WIZ_16G, 315 J721E_WIZ_10G, /* Also for J7200 SR1.0 */ 316 AM64_WIZ_10G, 317 J7200_WIZ_10G, /* J7200 SR2.0 */ 318 }; 319 320 struct wiz_data { 321 enum wiz_type type; 322 const struct reg_field *pll0_refclk_mux_sel; 323 const struct reg_field *pll1_refclk_mux_sel; 324 const struct reg_field *refclk_dig_sel; 325 const struct reg_field *pma_cmn_refclk1_dig_div; 326 const struct reg_field *pma_cmn_refclk1_int_mode; 327 const struct wiz_clk_mux_sel *clk_mux_sel; 328 unsigned int clk_div_sel_num; 329 }; 330 331 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ 332 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 333 334 struct wiz { 335 struct regmap *regmap; 336 struct regmap *scm_regmap; 337 enum wiz_type type; 338 const struct wiz_clk_mux_sel *clk_mux_sel; 339 const struct wiz_clk_div_sel *clk_div_sel; 340 unsigned int clk_div_sel_num; 341 struct regmap_field *por_en; 342 struct regmap_field *phy_reset_n; 343 struct regmap_field *phy_en_refclk; 344 struct regmap_field *p_enable[WIZ_MAX_LANES]; 345 struct regmap_field *p_align[WIZ_MAX_LANES]; 346 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; 347 struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; 348 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; 349 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; 350 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; 351 struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES]; 352 struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; 353 struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; 354 struct regmap_field *pma_cmn_refclk_int_mode; 355 struct regmap_field *pma_cmn_refclk1_int_mode; 356 struct regmap_field *pma_cmn_refclk_mode; 357 struct regmap_field *pma_cmn_refclk_dig_div; 358 struct regmap_field *pma_cmn_refclk1_dig_div; 359 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; 360 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; 361 struct regmap_field *typec_ln10_swap; 362 struct regmap_field *sup_legacy_clk_override; 363 364 struct device *dev; 365 u32 num_lanes; 366 struct platform_device *serdes_pdev; 367 struct reset_controller_dev wiz_phy_reset_dev; 368 struct gpio_desc *gpio_typec_dir; 369 int typec_dir_delay; 370 u32 lane_phy_type[WIZ_MAX_LANES]; 371 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; 372 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS]; 373 struct clk_onecell_data clk_data; 374 const struct wiz_data *data; 375 }; 376 377 static int wiz_reset(struct wiz *wiz) 378 { 379 int ret; 380 381 ret = regmap_field_write(wiz->por_en, 0x1); 382 if (ret) 383 return ret; 384 385 mdelay(1); 386 387 ret = regmap_field_write(wiz->por_en, 0x0); 388 if (ret) 389 return ret; 390 391 return 0; 392 } 393 394 static int wiz_p_mac_div_sel(struct wiz *wiz) 395 { 396 u32 num_lanes = wiz->num_lanes; 397 int ret; 398 int i; 399 400 for (i = 0; i < num_lanes; i++) { 401 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || 402 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII || 403 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 404 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); 405 if (ret) 406 return ret; 407 408 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); 409 if (ret) 410 return ret; 411 } 412 } 413 414 return 0; 415 } 416 417 static int wiz_mode_select(struct wiz *wiz) 418 { 419 u32 num_lanes = wiz->num_lanes; 420 enum wiz_lane_standard_mode mode; 421 int ret; 422 int i; 423 424 for (i = 0; i < num_lanes; i++) { 425 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) 426 mode = LANE_MODE_GEN1; 427 else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) 428 mode = LANE_MODE_GEN2; 429 else 430 continue; 431 432 if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 433 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); 434 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); 435 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3); 436 mode = LANE_MODE_GEN1; 437 } 438 439 ret = regmap_field_write(wiz->p_standard_mode[i], mode); 440 if (ret) 441 return ret; 442 } 443 444 return 0; 445 } 446 447 static int wiz_init_raw_interface(struct wiz *wiz, bool enable) 448 { 449 u32 num_lanes = wiz->num_lanes; 450 int i; 451 int ret; 452 453 for (i = 0; i < num_lanes; i++) { 454 ret = regmap_field_write(wiz->p_align[i], enable); 455 if (ret) 456 return ret; 457 458 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); 459 if (ret) 460 return ret; 461 } 462 463 return 0; 464 } 465 466 static int wiz_init(struct wiz *wiz) 467 { 468 struct device *dev = wiz->dev; 469 int ret; 470 471 ret = wiz_reset(wiz); 472 if (ret) { 473 dev_err(dev, "WIZ reset failed\n"); 474 return ret; 475 } 476 477 ret = wiz_mode_select(wiz); 478 if (ret) { 479 dev_err(dev, "WIZ mode select failed\n"); 480 return ret; 481 } 482 483 ret = wiz_p_mac_div_sel(wiz); 484 if (ret) { 485 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); 486 return ret; 487 } 488 489 ret = wiz_init_raw_interface(wiz, true); 490 if (ret) { 491 dev_err(dev, "WIZ interface initialization failed\n"); 492 return ret; 493 } 494 495 return 0; 496 } 497 498 static int wiz_regfield_init(struct wiz *wiz) 499 { 500 struct regmap *regmap = wiz->regmap; 501 struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */ 502 int num_lanes = wiz->num_lanes; 503 struct device *dev = wiz->dev; 504 const struct wiz_data *data = wiz->data; 505 int i; 506 507 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); 508 if (IS_ERR(wiz->por_en)) { 509 dev_err(dev, "POR_EN reg field init failed\n"); 510 return PTR_ERR(wiz->por_en); 511 } 512 513 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, 514 phy_reset_n); 515 if (IS_ERR(wiz->phy_reset_n)) { 516 dev_err(dev, "PHY_RESET_N reg field init failed\n"); 517 return PTR_ERR(wiz->phy_reset_n); 518 } 519 520 wiz->pma_cmn_refclk_int_mode = 521 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); 522 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { 523 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); 524 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); 525 } 526 527 wiz->pma_cmn_refclk_mode = 528 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); 529 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { 530 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); 531 return PTR_ERR(wiz->pma_cmn_refclk_mode); 532 } 533 534 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] = 535 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div); 536 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) { 537 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); 538 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); 539 } 540 541 if (data->pma_cmn_refclk1_dig_div) { 542 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = 543 devm_regmap_field_alloc(dev, regmap, 544 *data->pma_cmn_refclk1_dig_div); 545 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { 546 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); 547 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); 548 } 549 } 550 551 if (wiz->scm_regmap) { 552 scm_regmap = wiz->scm_regmap; 553 wiz->sup_legacy_clk_override = 554 devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override); 555 if (IS_ERR(wiz->sup_legacy_clk_override)) { 556 dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n"); 557 return PTR_ERR(wiz->sup_legacy_clk_override); 558 } 559 } 560 561 wiz->mux_sel_field[PLL0_REFCLK] = 562 devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel); 563 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { 564 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); 565 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); 566 } 567 568 wiz->mux_sel_field[PLL1_REFCLK] = 569 devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel); 570 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { 571 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); 572 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); 573 } 574 575 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap, 576 *data->refclk_dig_sel); 577 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { 578 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); 579 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); 580 } 581 582 if (data->pma_cmn_refclk1_int_mode) { 583 wiz->pma_cmn_refclk1_int_mode = 584 devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode); 585 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) { 586 dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n"); 587 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode); 588 } 589 } 590 591 for (i = 0; i < num_lanes; i++) { 592 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, 593 p_enable[i]); 594 if (IS_ERR(wiz->p_enable[i])) { 595 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 596 return PTR_ERR(wiz->p_enable[i]); 597 } 598 599 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, 600 p_align[i]); 601 if (IS_ERR(wiz->p_align[i])) { 602 dev_err(dev, "P%d_ALIGN reg field init failed\n", i); 603 return PTR_ERR(wiz->p_align[i]); 604 } 605 606 wiz->p_raw_auto_start[i] = 607 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); 608 if (IS_ERR(wiz->p_raw_auto_start[i])) { 609 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", 610 i); 611 return PTR_ERR(wiz->p_raw_auto_start[i]); 612 } 613 614 wiz->p_standard_mode[i] = 615 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); 616 if (IS_ERR(wiz->p_standard_mode[i])) { 617 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", 618 i); 619 return PTR_ERR(wiz->p_standard_mode[i]); 620 } 621 622 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); 623 if (IS_ERR(wiz->p0_fullrt_div[i])) { 624 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i); 625 return PTR_ERR(wiz->p0_fullrt_div[i]); 626 } 627 628 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]); 629 if (IS_ERR(wiz->p0_mac_src_sel[i])) { 630 dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i); 631 return PTR_ERR(wiz->p0_mac_src_sel[i]); 632 } 633 634 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]); 635 if (IS_ERR(wiz->p0_rxfclk_sel[i])) { 636 dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i); 637 return PTR_ERR(wiz->p0_rxfclk_sel[i]); 638 } 639 640 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]); 641 if (IS_ERR(wiz->p0_refclk_sel[i])) { 642 dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i); 643 return PTR_ERR(wiz->p0_refclk_sel[i]); 644 } 645 646 wiz->p_mac_div_sel0[i] = 647 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); 648 if (IS_ERR(wiz->p_mac_div_sel0[i])) { 649 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n", 650 i); 651 return PTR_ERR(wiz->p_mac_div_sel0[i]); 652 } 653 654 wiz->p_mac_div_sel1[i] = 655 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]); 656 if (IS_ERR(wiz->p_mac_div_sel1[i])) { 657 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n", 658 i); 659 return PTR_ERR(wiz->p_mac_div_sel1[i]); 660 } 661 } 662 663 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, 664 typec_ln10_swap); 665 if (IS_ERR(wiz->typec_ln10_swap)) { 666 dev_err(dev, "LN10_SWAP reg field init failed\n"); 667 return PTR_ERR(wiz->typec_ln10_swap); 668 } 669 670 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); 671 if (IS_ERR(wiz->phy_en_refclk)) { 672 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n"); 673 return PTR_ERR(wiz->phy_en_refclk); 674 } 675 676 return 0; 677 } 678 679 static int wiz_phy_en_refclk_enable(struct clk_hw *hw) 680 { 681 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 682 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 683 684 regmap_field_write(phy_en_refclk, 1); 685 686 return 0; 687 } 688 689 static void wiz_phy_en_refclk_disable(struct clk_hw *hw) 690 { 691 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 692 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 693 694 regmap_field_write(phy_en_refclk, 0); 695 } 696 697 static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw) 698 { 699 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 700 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 701 int val; 702 703 regmap_field_read(phy_en_refclk, &val); 704 705 return !!val; 706 } 707 708 static const struct clk_ops wiz_phy_en_refclk_ops = { 709 .enable = wiz_phy_en_refclk_enable, 710 .disable = wiz_phy_en_refclk_disable, 711 .is_enabled = wiz_phy_en_refclk_is_enabled, 712 }; 713 714 static int wiz_phy_en_refclk_register(struct wiz *wiz) 715 { 716 struct wiz_phy_en_refclk *wiz_phy_en_refclk; 717 struct device *dev = wiz->dev; 718 struct clk_init_data *init; 719 struct clk *clk; 720 721 wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL); 722 if (!wiz_phy_en_refclk) 723 return -ENOMEM; 724 725 init = &wiz_phy_en_refclk->clk_data; 726 727 init->ops = &wiz_phy_en_refclk_ops; 728 init->flags = 0; 729 init->name = output_clk_names[TI_WIZ_PHY_EN_REFCLK]; 730 731 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; 732 wiz_phy_en_refclk->hw.init = init; 733 734 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); 735 if (IS_ERR(clk)) 736 return PTR_ERR(clk); 737 738 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk; 739 740 return 0; 741 } 742 743 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) 744 { 745 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 746 struct regmap_field *field = mux->field; 747 unsigned int val; 748 749 regmap_field_read(field, &val); 750 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val); 751 } 752 753 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) 754 { 755 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 756 struct regmap_field *field = mux->field; 757 int val; 758 759 val = mux->table[index]; 760 return regmap_field_write(field, val); 761 } 762 763 static const struct clk_ops wiz_clk_mux_ops = { 764 .set_parent = wiz_clk_mux_set_parent, 765 .get_parent = wiz_clk_mux_get_parent, 766 }; 767 768 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field, 769 const struct wiz_clk_mux_sel *mux_sel, int clk_index) 770 { 771 struct device *dev = wiz->dev; 772 struct clk_init_data *init; 773 const char **parent_names; 774 unsigned int num_parents; 775 struct wiz_clk_mux *mux; 776 char clk_name[100]; 777 struct clk *clk; 778 int ret = 0, i; 779 780 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 781 if (!mux) 782 return -ENOMEM; 783 784 num_parents = mux_sel->num_parents; 785 786 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); 787 if (!parent_names) 788 return -ENOMEM; 789 790 for (i = 0; i < num_parents; i++) { 791 clk = wiz->input_clks[mux_sel->parents[i]]; 792 if (IS_ERR_OR_NULL(clk)) { 793 dev_err(dev, "Failed to get parent clk for %s\n", 794 output_clk_names[clk_index]); 795 ret = -EINVAL; 796 goto err; 797 } 798 parent_names[i] = __clk_get_name(clk); 799 } 800 801 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]); 802 803 init = &mux->clk_data; 804 805 init->ops = &wiz_clk_mux_ops; 806 init->flags = CLK_SET_RATE_NO_REPARENT; 807 init->parent_names = parent_names; 808 init->num_parents = num_parents; 809 init->name = clk_name; 810 811 mux->field = field; 812 mux->table = mux_sel->table; 813 mux->hw.init = init; 814 815 clk = devm_clk_register(dev, &mux->hw); 816 if (IS_ERR(clk)) { 817 ret = PTR_ERR(clk); 818 goto err; 819 } 820 821 wiz->output_clks[clk_index] = clk; 822 823 err: 824 kfree(parent_names); 825 826 return ret; 827 } 828 829 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node, 830 struct regmap_field *field, const u32 *table) 831 { 832 struct device *dev = wiz->dev; 833 struct clk_init_data *init; 834 const char **parent_names; 835 unsigned int num_parents; 836 struct wiz_clk_mux *mux; 837 char clk_name[100]; 838 struct clk *clk; 839 int ret; 840 841 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 842 if (!mux) 843 return -ENOMEM; 844 845 num_parents = of_clk_get_parent_count(node); 846 if (num_parents < 2) { 847 dev_err(dev, "SERDES clock must have parents\n"); 848 return -EINVAL; 849 } 850 851 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 852 GFP_KERNEL); 853 if (!parent_names) 854 return -ENOMEM; 855 856 of_clk_parent_fill(node, parent_names, num_parents); 857 858 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 859 node->name); 860 861 init = &mux->clk_data; 862 863 init->ops = &wiz_clk_mux_ops; 864 init->flags = CLK_SET_RATE_NO_REPARENT; 865 init->parent_names = parent_names; 866 init->num_parents = num_parents; 867 init->name = clk_name; 868 869 mux->field = field; 870 mux->table = table; 871 mux->hw.init = init; 872 873 clk = devm_clk_register(dev, &mux->hw); 874 if (IS_ERR(clk)) 875 return PTR_ERR(clk); 876 877 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 878 if (ret) 879 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 880 881 return ret; 882 } 883 884 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, 885 unsigned long parent_rate) 886 { 887 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 888 struct regmap_field *field = div->field; 889 int val; 890 891 regmap_field_read(field, &val); 892 893 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); 894 } 895 896 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 897 unsigned long *prate) 898 { 899 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 900 901 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); 902 } 903 904 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 905 unsigned long parent_rate) 906 { 907 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 908 struct regmap_field *field = div->field; 909 int val; 910 911 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); 912 if (val < 0) 913 return val; 914 915 return regmap_field_write(field, val); 916 } 917 918 static const struct clk_ops wiz_clk_div_ops = { 919 .recalc_rate = wiz_clk_div_recalc_rate, 920 .round_rate = wiz_clk_div_round_rate, 921 .set_rate = wiz_clk_div_set_rate, 922 }; 923 924 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, 925 struct regmap_field *field, 926 const struct clk_div_table *table) 927 { 928 struct device *dev = wiz->dev; 929 struct wiz_clk_divider *div; 930 struct clk_init_data *init; 931 const char **parent_names; 932 char clk_name[100]; 933 struct clk *clk; 934 int ret; 935 936 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 937 if (!div) 938 return -ENOMEM; 939 940 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 941 node->name); 942 943 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 944 if (!parent_names) 945 return -ENOMEM; 946 947 of_clk_parent_fill(node, parent_names, 1); 948 949 init = &div->clk_data; 950 951 init->ops = &wiz_clk_div_ops; 952 init->flags = 0; 953 init->parent_names = parent_names; 954 init->num_parents = 1; 955 init->name = clk_name; 956 957 div->field = field; 958 div->table = table; 959 div->hw.init = init; 960 961 clk = devm_clk_register(dev, &div->hw); 962 if (IS_ERR(clk)) 963 return PTR_ERR(clk); 964 965 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 966 if (ret) 967 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 968 969 return ret; 970 } 971 972 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) 973 { 974 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 975 struct device *dev = wiz->dev; 976 struct device_node *clk_node; 977 int i; 978 979 switch (wiz->type) { 980 case AM64_WIZ_10G: 981 case J7200_WIZ_10G: 982 of_clk_del_provider(dev->of_node); 983 return; 984 default: 985 break; 986 } 987 988 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 989 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); 990 of_clk_del_provider(clk_node); 991 of_node_put(clk_node); 992 } 993 994 for (i = 0; i < wiz->clk_div_sel_num; i++) { 995 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name); 996 of_clk_del_provider(clk_node); 997 of_node_put(clk_node); 998 } 999 1000 of_clk_del_provider(wiz->dev->of_node); 1001 } 1002 1003 static int wiz_clock_register(struct wiz *wiz) 1004 { 1005 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1006 struct device *dev = wiz->dev; 1007 struct device_node *node = dev->of_node; 1008 int clk_index; 1009 int ret; 1010 int i; 1011 1012 clk_index = TI_WIZ_PLL0_REFCLK; 1013 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { 1014 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); 1015 if (ret) { 1016 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]); 1017 return ret; 1018 } 1019 } 1020 1021 ret = wiz_phy_en_refclk_register(wiz); 1022 if (ret) { 1023 dev_err(dev, "Failed to add phy-en-refclk\n"); 1024 return ret; 1025 } 1026 1027 wiz->clk_data.clks = wiz->output_clks; 1028 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS; 1029 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data); 1030 if (ret) 1031 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 1032 1033 return ret; 1034 } 1035 1036 static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 1037 { 1038 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1039 struct device *dev = wiz->dev; 1040 struct device_node *clk_node; 1041 const char *node_name; 1042 unsigned long rate; 1043 struct clk *clk; 1044 int ret; 1045 int i; 1046 1047 clk = devm_clk_get(dev, "core_ref_clk"); 1048 if (IS_ERR(clk)) { 1049 dev_err(dev, "core_ref_clk clock not found\n"); 1050 ret = PTR_ERR(clk); 1051 return ret; 1052 } 1053 wiz->input_clks[WIZ_CORE_REFCLK] = clk; 1054 1055 rate = clk_get_rate(clk); 1056 if (rate >= 100000000) 1057 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 1058 else 1059 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 1060 1061 switch (wiz->type) { 1062 case AM64_WIZ_10G: 1063 case J7200_WIZ_10G: 1064 switch (rate) { 1065 case REF_CLK_100MHZ: 1066 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2); 1067 break; 1068 case REF_CLK_156_25MHZ: 1069 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3); 1070 break; 1071 default: 1072 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0); 1073 break; 1074 } 1075 break; 1076 default: 1077 break; 1078 } 1079 1080 if (wiz->data->pma_cmn_refclk1_int_mode) { 1081 clk = devm_clk_get(dev, "core_ref1_clk"); 1082 if (IS_ERR(clk)) { 1083 dev_err(dev, "core_ref1_clk clock not found\n"); 1084 ret = PTR_ERR(clk); 1085 return ret; 1086 } 1087 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; 1088 1089 rate = clk_get_rate(clk); 1090 if (rate >= 100000000) 1091 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); 1092 else 1093 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); 1094 } 1095 1096 clk = devm_clk_get(dev, "ext_ref_clk"); 1097 if (IS_ERR(clk)) { 1098 dev_err(dev, "ext_ref_clk clock not found\n"); 1099 ret = PTR_ERR(clk); 1100 return ret; 1101 } 1102 wiz->input_clks[WIZ_EXT_REFCLK] = clk; 1103 1104 rate = clk_get_rate(clk); 1105 if (rate >= 100000000) 1106 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 1107 else 1108 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 1109 1110 switch (wiz->type) { 1111 case AM64_WIZ_10G: 1112 case J7200_WIZ_10G: 1113 ret = wiz_clock_register(wiz); 1114 if (ret) 1115 dev_err(dev, "Failed to register wiz clocks\n"); 1116 return ret; 1117 default: 1118 break; 1119 } 1120 1121 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 1122 node_name = clk_mux_sel[i].node_name; 1123 clk_node = of_get_child_by_name(node, node_name); 1124 if (!clk_node) { 1125 dev_err(dev, "Unable to get %s node\n", node_name); 1126 ret = -EINVAL; 1127 goto err; 1128 } 1129 1130 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i], 1131 clk_mux_sel[i].table); 1132 if (ret) { 1133 dev_err(dev, "Failed to register %s clock\n", 1134 node_name); 1135 of_node_put(clk_node); 1136 goto err; 1137 } 1138 1139 of_node_put(clk_node); 1140 } 1141 1142 for (i = 0; i < wiz->clk_div_sel_num; i++) { 1143 node_name = clk_div_sel[i].node_name; 1144 clk_node = of_get_child_by_name(node, node_name); 1145 if (!clk_node) { 1146 dev_err(dev, "Unable to get %s node\n", node_name); 1147 ret = -EINVAL; 1148 goto err; 1149 } 1150 1151 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i], 1152 clk_div_sel[i].table); 1153 if (ret) { 1154 dev_err(dev, "Failed to register %s clock\n", 1155 node_name); 1156 of_node_put(clk_node); 1157 goto err; 1158 } 1159 1160 of_node_put(clk_node); 1161 } 1162 1163 return 0; 1164 err: 1165 wiz_clock_cleanup(wiz, node); 1166 1167 return ret; 1168 } 1169 1170 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, 1171 unsigned long id) 1172 { 1173 struct device *dev = rcdev->dev; 1174 struct wiz *wiz = dev_get_drvdata(dev); 1175 int ret = 0; 1176 1177 if (id == 0) { 1178 ret = regmap_field_write(wiz->phy_reset_n, false); 1179 return ret; 1180 } 1181 1182 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); 1183 return ret; 1184 } 1185 1186 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) 1187 { 1188 switch (wiz->type) { 1189 case AM64_WIZ_10G: 1190 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) 1191 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); 1192 break; 1193 case J721E_WIZ_10G: 1194 case J7200_WIZ_10G: 1195 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) 1196 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); 1197 break; 1198 default: 1199 return 0; 1200 } 1201 return 0; 1202 } 1203 1204 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, 1205 unsigned long id) 1206 { 1207 struct device *dev = rcdev->dev; 1208 struct wiz *wiz = dev_get_drvdata(dev); 1209 int ret; 1210 1211 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ 1212 if (id == 0 && wiz->gpio_typec_dir) { 1213 if (wiz->typec_dir_delay) 1214 msleep_interruptible(wiz->typec_dir_delay); 1215 1216 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) 1217 regmap_field_write(wiz->typec_ln10_swap, 1); 1218 else 1219 regmap_field_write(wiz->typec_ln10_swap, 0); 1220 } 1221 1222 if (id == 0) { 1223 ret = regmap_field_write(wiz->phy_reset_n, true); 1224 return ret; 1225 } 1226 1227 ret = wiz_phy_fullrt_div(wiz, id - 1); 1228 if (ret) 1229 return ret; 1230 1231 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) 1232 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); 1233 else 1234 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); 1235 1236 return ret; 1237 } 1238 1239 static const struct reset_control_ops wiz_phy_reset_ops = { 1240 .assert = wiz_phy_reset_assert, 1241 .deassert = wiz_phy_reset_deassert, 1242 }; 1243 1244 static const struct regmap_config wiz_regmap_config = { 1245 .reg_bits = 32, 1246 .val_bits = 32, 1247 .reg_stride = 4, 1248 .fast_io = true, 1249 }; 1250 1251 static struct wiz_data j721e_16g_data = { 1252 .type = J721E_WIZ_16G, 1253 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1254 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1255 .refclk_dig_sel = &refclk_dig_sel_16g, 1256 .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div, 1257 .clk_mux_sel = clk_mux_sel_16g, 1258 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G, 1259 }; 1260 1261 static struct wiz_data j721e_10g_data = { 1262 .type = J721E_WIZ_10G, 1263 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1264 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1265 .refclk_dig_sel = &refclk_dig_sel_10g, 1266 .clk_mux_sel = clk_mux_sel_10g, 1267 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1268 }; 1269 1270 static struct wiz_data am64_10g_data = { 1271 .type = AM64_WIZ_10G, 1272 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1273 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1274 .refclk_dig_sel = &refclk_dig_sel_10g, 1275 .clk_mux_sel = clk_mux_sel_10g, 1276 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1277 }; 1278 1279 static struct wiz_data j7200_pg2_10g_data = { 1280 .type = J7200_WIZ_10G, 1281 .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel, 1282 .pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel, 1283 .refclk_dig_sel = &sup_refclk_dig_sel_10g, 1284 .pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode, 1285 .clk_mux_sel = clk_mux_sel_10g_2_refclk, 1286 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1287 }; 1288 1289 static const struct of_device_id wiz_id_table[] = { 1290 { 1291 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, 1292 }, 1293 { 1294 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data, 1295 }, 1296 { 1297 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data, 1298 }, 1299 { 1300 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data, 1301 }, 1302 {} 1303 }; 1304 MODULE_DEVICE_TABLE(of, wiz_id_table); 1305 1306 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) 1307 { 1308 struct device_node *serdes, *subnode; 1309 1310 serdes = of_get_child_by_name(dev->of_node, "serdes"); 1311 if (!serdes) { 1312 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); 1313 return -EINVAL; 1314 } 1315 1316 for_each_child_of_node(serdes, subnode) { 1317 u32 reg, num_lanes = 1, phy_type = PHY_NONE; 1318 int ret, i; 1319 1320 if (!(of_node_name_eq(subnode, "phy") || 1321 of_node_name_eq(subnode, "link"))) 1322 continue; 1323 1324 ret = of_property_read_u32(subnode, "reg", ®); 1325 if (ret) { 1326 of_node_put(subnode); 1327 dev_err(dev, 1328 "%s: Reading \"reg\" from \"%s\" failed: %d\n", 1329 __func__, subnode->name, ret); 1330 return ret; 1331 } 1332 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); 1333 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); 1334 1335 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, 1336 reg, reg + num_lanes - 1, phy_type); 1337 1338 for (i = reg; i < reg + num_lanes; i++) 1339 wiz->lane_phy_type[i] = phy_type; 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int wiz_probe(struct platform_device *pdev) 1346 { 1347 struct reset_controller_dev *phy_reset_dev; 1348 struct device *dev = &pdev->dev; 1349 struct device_node *node = dev->of_node; 1350 struct platform_device *serdes_pdev; 1351 bool already_configured = false; 1352 struct device_node *child_node; 1353 struct regmap *regmap; 1354 struct resource res; 1355 void __iomem *base; 1356 struct wiz *wiz; 1357 int ret, val, i; 1358 u32 num_lanes; 1359 const struct wiz_data *data; 1360 1361 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); 1362 if (!wiz) 1363 return -ENOMEM; 1364 1365 data = of_device_get_match_data(dev); 1366 if (!data) { 1367 dev_err(dev, "NULL device data\n"); 1368 return -EINVAL; 1369 } 1370 1371 wiz->data = data; 1372 wiz->type = data->type; 1373 1374 child_node = of_get_child_by_name(node, "serdes"); 1375 if (!child_node) { 1376 dev_err(dev, "Failed to get SERDES child DT node\n"); 1377 return -ENODEV; 1378 } 1379 1380 ret = of_address_to_resource(child_node, 0, &res); 1381 if (ret) { 1382 dev_err(dev, "Failed to get memory resource\n"); 1383 goto err_addr_to_resource; 1384 } 1385 1386 base = devm_ioremap(dev, res.start, resource_size(&res)); 1387 if (!base) { 1388 ret = -ENOMEM; 1389 goto err_addr_to_resource; 1390 } 1391 1392 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); 1393 if (IS_ERR(regmap)) { 1394 dev_err(dev, "Failed to initialize regmap\n"); 1395 ret = PTR_ERR(regmap); 1396 goto err_addr_to_resource; 1397 } 1398 1399 wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm"); 1400 if (IS_ERR(wiz->scm_regmap)) { 1401 if (wiz->type == J7200_WIZ_10G) { 1402 dev_err(dev, "Couldn't get ti,scm regmap\n"); 1403 return -ENODEV; 1404 } 1405 1406 wiz->scm_regmap = NULL; 1407 } 1408 1409 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 1410 if (ret) { 1411 dev_err(dev, "Failed to read num-lanes property\n"); 1412 goto err_addr_to_resource; 1413 } 1414 1415 if (num_lanes > WIZ_MAX_LANES) { 1416 dev_err(dev, "Cannot support %d lanes\n", num_lanes); 1417 ret = -ENODEV; 1418 goto err_addr_to_resource; 1419 } 1420 1421 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", 1422 GPIOD_IN); 1423 if (IS_ERR(wiz->gpio_typec_dir)) { 1424 ret = PTR_ERR(wiz->gpio_typec_dir); 1425 if (ret != -EPROBE_DEFER) 1426 dev_err(dev, "Failed to request typec-dir gpio: %d\n", 1427 ret); 1428 goto err_addr_to_resource; 1429 } 1430 1431 if (wiz->gpio_typec_dir) { 1432 ret = of_property_read_u32(node, "typec-dir-debounce-ms", 1433 &wiz->typec_dir_delay); 1434 if (ret && ret != -EINVAL) { 1435 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1436 goto err_addr_to_resource; 1437 } 1438 1439 /* use min. debounce from Type-C spec if not provided in DT */ 1440 if (ret == -EINVAL) 1441 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; 1442 1443 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 1444 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 1445 ret = -EINVAL; 1446 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1447 goto err_addr_to_resource; 1448 } 1449 } 1450 1451 ret = wiz_get_lane_phy_types(dev, wiz); 1452 if (ret) 1453 return ret; 1454 1455 wiz->dev = dev; 1456 wiz->regmap = regmap; 1457 wiz->num_lanes = num_lanes; 1458 wiz->clk_mux_sel = data->clk_mux_sel; 1459 wiz->clk_div_sel = clk_div_sel; 1460 wiz->clk_div_sel_num = data->clk_div_sel_num; 1461 1462 platform_set_drvdata(pdev, wiz); 1463 1464 ret = wiz_regfield_init(wiz); 1465 if (ret) { 1466 dev_err(dev, "Failed to initialize regfields\n"); 1467 goto err_addr_to_resource; 1468 } 1469 1470 /* Enable supplemental Control override if available */ 1471 if (wiz->scm_regmap) 1472 regmap_field_write(wiz->sup_legacy_clk_override, 1); 1473 1474 phy_reset_dev = &wiz->wiz_phy_reset_dev; 1475 phy_reset_dev->dev = dev; 1476 phy_reset_dev->ops = &wiz_phy_reset_ops, 1477 phy_reset_dev->owner = THIS_MODULE, 1478 phy_reset_dev->of_node = node; 1479 /* Reset for each of the lane and one for the entire SERDES */ 1480 phy_reset_dev->nr_resets = num_lanes + 1; 1481 1482 ret = devm_reset_controller_register(dev, phy_reset_dev); 1483 if (ret < 0) { 1484 dev_warn(dev, "Failed to register reset controller\n"); 1485 goto err_addr_to_resource; 1486 } 1487 1488 pm_runtime_enable(dev); 1489 ret = pm_runtime_get_sync(dev); 1490 if (ret < 0) { 1491 dev_err(dev, "pm_runtime_get_sync failed\n"); 1492 goto err_get_sync; 1493 } 1494 1495 ret = wiz_clock_init(wiz, node); 1496 if (ret < 0) { 1497 dev_warn(dev, "Failed to initialize clocks\n"); 1498 goto err_get_sync; 1499 } 1500 1501 for (i = 0; i < wiz->num_lanes; i++) { 1502 regmap_field_read(wiz->p_enable[i], &val); 1503 if (val & (P_ENABLE | P_ENABLE_FORCE)) { 1504 already_configured = true; 1505 break; 1506 } 1507 } 1508 1509 if (!already_configured) { 1510 ret = wiz_init(wiz); 1511 if (ret) { 1512 dev_err(dev, "WIZ initialization failed\n"); 1513 goto err_wiz_init; 1514 } 1515 } 1516 1517 serdes_pdev = of_platform_device_create(child_node, NULL, dev); 1518 if (!serdes_pdev) { 1519 dev_WARN(dev, "Unable to create SERDES platform device\n"); 1520 ret = -ENOMEM; 1521 goto err_wiz_init; 1522 } 1523 wiz->serdes_pdev = serdes_pdev; 1524 1525 of_node_put(child_node); 1526 return 0; 1527 1528 err_wiz_init: 1529 wiz_clock_cleanup(wiz, node); 1530 1531 err_get_sync: 1532 pm_runtime_put(dev); 1533 pm_runtime_disable(dev); 1534 1535 err_addr_to_resource: 1536 of_node_put(child_node); 1537 1538 return ret; 1539 } 1540 1541 static int wiz_remove(struct platform_device *pdev) 1542 { 1543 struct device *dev = &pdev->dev; 1544 struct device_node *node = dev->of_node; 1545 struct platform_device *serdes_pdev; 1546 struct wiz *wiz; 1547 1548 wiz = dev_get_drvdata(dev); 1549 serdes_pdev = wiz->serdes_pdev; 1550 1551 of_platform_device_destroy(&serdes_pdev->dev, NULL); 1552 wiz_clock_cleanup(wiz, node); 1553 pm_runtime_put(dev); 1554 pm_runtime_disable(dev); 1555 1556 return 0; 1557 } 1558 1559 static struct platform_driver wiz_driver = { 1560 .probe = wiz_probe, 1561 .remove = wiz_remove, 1562 .driver = { 1563 .name = "wiz", 1564 .of_match_table = wiz_id_table, 1565 }, 1566 }; 1567 module_platform_driver(wiz_driver); 1568 1569 MODULE_AUTHOR("Texas Instruments Inc."); 1570 MODULE_DESCRIPTION("TI J721E WIZ driver"); 1571 MODULE_LICENSE("GPL v2"); 1572