1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * Wrapper driver for SERDES used in J721E 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/gpio.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/mux/consumer.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/reset-controller.h> 23 24 #define WIZ_SERDES_CTRL 0x404 25 #define WIZ_SERDES_TOP_CTRL 0x408 26 #define WIZ_SERDES_RST 0x40c 27 #define WIZ_SERDES_TYPEC 0x410 28 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) 29 30 #define WIZ_MAX_LANES 4 31 #define WIZ_MUX_NUM_CLOCKS 3 32 #define WIZ_DIV_NUM_CLOCKS_16G 2 33 #define WIZ_DIV_NUM_CLOCKS_10G 1 34 35 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) 36 37 enum wiz_lane_standard_mode { 38 LANE_MODE_GEN1, 39 LANE_MODE_GEN2, 40 LANE_MODE_GEN3, 41 LANE_MODE_GEN4, 42 }; 43 44 enum wiz_refclk_mux_sel { 45 PLL0_REFCLK, 46 PLL1_REFCLK, 47 REFCLK_DIG, 48 }; 49 50 enum wiz_refclk_div_sel { 51 CMN_REFCLK_DIG_DIV, 52 CMN_REFCLK1_DIG_DIV, 53 }; 54 55 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); 56 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); 57 static const struct reg_field pll1_refclk_mux_sel = 58 REG_FIELD(WIZ_SERDES_RST, 29, 29); 59 static const struct reg_field pll0_refclk_mux_sel = 60 REG_FIELD(WIZ_SERDES_RST, 28, 28); 61 static const struct reg_field refclk_dig_sel_16g = 62 REG_FIELD(WIZ_SERDES_RST, 24, 25); 63 static const struct reg_field refclk_dig_sel_10g = 64 REG_FIELD(WIZ_SERDES_RST, 24, 24); 65 static const struct reg_field pma_cmn_refclk_int_mode = 66 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 67 static const struct reg_field pma_cmn_refclk_mode = 68 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 69 static const struct reg_field pma_cmn_refclk_dig_div = 70 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); 71 static const struct reg_field pma_cmn_refclk1_dig_div = 72 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); 73 74 static const struct reg_field p_enable[WIZ_MAX_LANES] = { 75 REG_FIELD(WIZ_LANECTL(0), 30, 31), 76 REG_FIELD(WIZ_LANECTL(1), 30, 31), 77 REG_FIELD(WIZ_LANECTL(2), 30, 31), 78 REG_FIELD(WIZ_LANECTL(3), 30, 31), 79 }; 80 81 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; 82 83 static const struct reg_field p_align[WIZ_MAX_LANES] = { 84 REG_FIELD(WIZ_LANECTL(0), 29, 29), 85 REG_FIELD(WIZ_LANECTL(1), 29, 29), 86 REG_FIELD(WIZ_LANECTL(2), 29, 29), 87 REG_FIELD(WIZ_LANECTL(3), 29, 29), 88 }; 89 90 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { 91 REG_FIELD(WIZ_LANECTL(0), 28, 28), 92 REG_FIELD(WIZ_LANECTL(1), 28, 28), 93 REG_FIELD(WIZ_LANECTL(2), 28, 28), 94 REG_FIELD(WIZ_LANECTL(3), 28, 28), 95 }; 96 97 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { 98 REG_FIELD(WIZ_LANECTL(0), 24, 25), 99 REG_FIELD(WIZ_LANECTL(1), 24, 25), 100 REG_FIELD(WIZ_LANECTL(2), 24, 25), 101 REG_FIELD(WIZ_LANECTL(3), 24, 25), 102 }; 103 104 static const struct reg_field typec_ln10_swap = 105 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 106 107 struct wiz_clk_mux { 108 struct clk_hw hw; 109 struct regmap_field *field; 110 u32 *table; 111 struct clk_init_data clk_data; 112 }; 113 114 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) 115 116 struct wiz_clk_divider { 117 struct clk_hw hw; 118 struct regmap_field *field; 119 const struct clk_div_table *table; 120 struct clk_init_data clk_data; 121 }; 122 123 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) 124 125 struct wiz_clk_mux_sel { 126 struct regmap_field *field; 127 u32 table[4]; 128 const char *node_name; 129 }; 130 131 struct wiz_clk_div_sel { 132 struct regmap_field *field; 133 const struct clk_div_table *table; 134 const char *node_name; 135 }; 136 137 static struct wiz_clk_mux_sel clk_mux_sel_16g[] = { 138 { 139 /* 140 * Mux value to be configured for each of the input clocks 141 * in the order populated in device tree 142 */ 143 .table = { 1, 0 }, 144 .node_name = "pll0-refclk", 145 }, 146 { 147 .table = { 1, 0 }, 148 .node_name = "pll1-refclk", 149 }, 150 { 151 .table = { 1, 3, 0, 2 }, 152 .node_name = "refclk-dig", 153 }, 154 }; 155 156 static struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 157 { 158 /* 159 * Mux value to be configured for each of the input clocks 160 * in the order populated in device tree 161 */ 162 .table = { 1, 0 }, 163 .node_name = "pll0-refclk", 164 }, 165 { 166 .table = { 1, 0 }, 167 .node_name = "pll1-refclk", 168 }, 169 { 170 .table = { 1, 0 }, 171 .node_name = "refclk-dig", 172 }, 173 }; 174 175 static const struct clk_div_table clk_div_table[] = { 176 { .val = 0, .div = 1, }, 177 { .val = 1, .div = 2, }, 178 { .val = 2, .div = 4, }, 179 { .val = 3, .div = 8, }, 180 }; 181 182 static struct wiz_clk_div_sel clk_div_sel[] = { 183 { 184 .table = clk_div_table, 185 .node_name = "cmn-refclk-dig-div", 186 }, 187 { 188 .table = clk_div_table, 189 .node_name = "cmn-refclk1-dig-div", 190 }, 191 }; 192 193 enum wiz_type { 194 J721E_WIZ_16G, 195 J721E_WIZ_10G, 196 }; 197 198 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ 199 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 200 201 struct wiz { 202 struct regmap *regmap; 203 enum wiz_type type; 204 struct wiz_clk_mux_sel *clk_mux_sel; 205 struct wiz_clk_div_sel *clk_div_sel; 206 unsigned int clk_div_sel_num; 207 struct regmap_field *por_en; 208 struct regmap_field *phy_reset_n; 209 struct regmap_field *p_enable[WIZ_MAX_LANES]; 210 struct regmap_field *p_align[WIZ_MAX_LANES]; 211 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; 212 struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; 213 struct regmap_field *pma_cmn_refclk_int_mode; 214 struct regmap_field *pma_cmn_refclk_mode; 215 struct regmap_field *pma_cmn_refclk_dig_div; 216 struct regmap_field *pma_cmn_refclk1_dig_div; 217 struct regmap_field *typec_ln10_swap; 218 219 struct device *dev; 220 u32 num_lanes; 221 struct platform_device *serdes_pdev; 222 struct reset_controller_dev wiz_phy_reset_dev; 223 struct gpio_desc *gpio_typec_dir; 224 int typec_dir_delay; 225 u32 lane_phy_type[WIZ_MAX_LANES]; 226 }; 227 228 static int wiz_reset(struct wiz *wiz) 229 { 230 int ret; 231 232 ret = regmap_field_write(wiz->por_en, 0x1); 233 if (ret) 234 return ret; 235 236 mdelay(1); 237 238 ret = regmap_field_write(wiz->por_en, 0x0); 239 if (ret) 240 return ret; 241 242 return 0; 243 } 244 245 static int wiz_mode_select(struct wiz *wiz) 246 { 247 u32 num_lanes = wiz->num_lanes; 248 enum wiz_lane_standard_mode mode; 249 int ret; 250 int i; 251 252 for (i = 0; i < num_lanes; i++) { 253 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) 254 mode = LANE_MODE_GEN1; 255 else 256 mode = LANE_MODE_GEN4; 257 258 ret = regmap_field_write(wiz->p_standard_mode[i], mode); 259 if (ret) 260 return ret; 261 } 262 263 return 0; 264 } 265 266 static int wiz_init_raw_interface(struct wiz *wiz, bool enable) 267 { 268 u32 num_lanes = wiz->num_lanes; 269 int i; 270 int ret; 271 272 for (i = 0; i < num_lanes; i++) { 273 ret = regmap_field_write(wiz->p_align[i], enable); 274 if (ret) 275 return ret; 276 277 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); 278 if (ret) 279 return ret; 280 } 281 282 return 0; 283 } 284 285 static int wiz_init(struct wiz *wiz) 286 { 287 struct device *dev = wiz->dev; 288 int ret; 289 290 ret = wiz_reset(wiz); 291 if (ret) { 292 dev_err(dev, "WIZ reset failed\n"); 293 return ret; 294 } 295 296 ret = wiz_mode_select(wiz); 297 if (ret) { 298 dev_err(dev, "WIZ mode select failed\n"); 299 return ret; 300 } 301 302 ret = wiz_init_raw_interface(wiz, true); 303 if (ret) { 304 dev_err(dev, "WIZ interface initialization failed\n"); 305 return ret; 306 } 307 308 return 0; 309 } 310 311 static int wiz_regfield_init(struct wiz *wiz) 312 { 313 struct wiz_clk_mux_sel *clk_mux_sel; 314 struct wiz_clk_div_sel *clk_div_sel; 315 struct regmap *regmap = wiz->regmap; 316 int num_lanes = wiz->num_lanes; 317 struct device *dev = wiz->dev; 318 int i; 319 320 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); 321 if (IS_ERR(wiz->por_en)) { 322 dev_err(dev, "POR_EN reg field init failed\n"); 323 return PTR_ERR(wiz->por_en); 324 } 325 326 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, 327 phy_reset_n); 328 if (IS_ERR(wiz->phy_reset_n)) { 329 dev_err(dev, "PHY_RESET_N reg field init failed\n"); 330 return PTR_ERR(wiz->phy_reset_n); 331 } 332 333 wiz->pma_cmn_refclk_int_mode = 334 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); 335 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { 336 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); 337 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); 338 } 339 340 wiz->pma_cmn_refclk_mode = 341 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); 342 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { 343 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); 344 return PTR_ERR(wiz->pma_cmn_refclk_mode); 345 } 346 347 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV]; 348 clk_div_sel->field = devm_regmap_field_alloc(dev, regmap, 349 pma_cmn_refclk_dig_div); 350 if (IS_ERR(clk_div_sel->field)) { 351 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); 352 return PTR_ERR(clk_div_sel->field); 353 } 354 355 if (wiz->type == J721E_WIZ_16G) { 356 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV]; 357 clk_div_sel->field = 358 devm_regmap_field_alloc(dev, regmap, 359 pma_cmn_refclk1_dig_div); 360 if (IS_ERR(clk_div_sel->field)) { 361 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); 362 return PTR_ERR(clk_div_sel->field); 363 } 364 } 365 366 clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK]; 367 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, 368 pll0_refclk_mux_sel); 369 if (IS_ERR(clk_mux_sel->field)) { 370 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); 371 return PTR_ERR(clk_mux_sel->field); 372 } 373 374 clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK]; 375 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, 376 pll1_refclk_mux_sel); 377 if (IS_ERR(clk_mux_sel->field)) { 378 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); 379 return PTR_ERR(clk_mux_sel->field); 380 } 381 382 clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG]; 383 if (wiz->type == J721E_WIZ_10G) 384 clk_mux_sel->field = 385 devm_regmap_field_alloc(dev, regmap, 386 refclk_dig_sel_10g); 387 else 388 clk_mux_sel->field = 389 devm_regmap_field_alloc(dev, regmap, 390 refclk_dig_sel_16g); 391 392 if (IS_ERR(clk_mux_sel->field)) { 393 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); 394 return PTR_ERR(clk_mux_sel->field); 395 } 396 397 for (i = 0; i < num_lanes; i++) { 398 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, 399 p_enable[i]); 400 if (IS_ERR(wiz->p_enable[i])) { 401 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 402 return PTR_ERR(wiz->p_enable[i]); 403 } 404 405 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, 406 p_align[i]); 407 if (IS_ERR(wiz->p_align[i])) { 408 dev_err(dev, "P%d_ALIGN reg field init failed\n", i); 409 return PTR_ERR(wiz->p_align[i]); 410 } 411 412 wiz->p_raw_auto_start[i] = 413 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); 414 if (IS_ERR(wiz->p_raw_auto_start[i])) { 415 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", 416 i); 417 return PTR_ERR(wiz->p_raw_auto_start[i]); 418 } 419 420 wiz->p_standard_mode[i] = 421 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); 422 if (IS_ERR(wiz->p_standard_mode[i])) { 423 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", 424 i); 425 return PTR_ERR(wiz->p_standard_mode[i]); 426 } 427 } 428 429 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, 430 typec_ln10_swap); 431 if (IS_ERR(wiz->typec_ln10_swap)) { 432 dev_err(dev, "LN10_SWAP reg field init failed\n"); 433 return PTR_ERR(wiz->typec_ln10_swap); 434 } 435 436 return 0; 437 } 438 439 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) 440 { 441 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 442 struct regmap_field *field = mux->field; 443 unsigned int val; 444 445 regmap_field_read(field, &val); 446 return clk_mux_val_to_index(hw, mux->table, 0, val); 447 } 448 449 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) 450 { 451 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 452 struct regmap_field *field = mux->field; 453 int val; 454 455 val = mux->table[index]; 456 return regmap_field_write(field, val); 457 } 458 459 static const struct clk_ops wiz_clk_mux_ops = { 460 .set_parent = wiz_clk_mux_set_parent, 461 .get_parent = wiz_clk_mux_get_parent, 462 }; 463 464 static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node, 465 struct regmap_field *field, u32 *table) 466 { 467 struct device *dev = wiz->dev; 468 struct clk_init_data *init; 469 const char **parent_names; 470 unsigned int num_parents; 471 struct wiz_clk_mux *mux; 472 char clk_name[100]; 473 struct clk *clk; 474 int ret; 475 476 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 477 if (!mux) 478 return -ENOMEM; 479 480 num_parents = of_clk_get_parent_count(node); 481 if (num_parents < 2) { 482 dev_err(dev, "SERDES clock must have parents\n"); 483 return -EINVAL; 484 } 485 486 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 487 GFP_KERNEL); 488 if (!parent_names) 489 return -ENOMEM; 490 491 of_clk_parent_fill(node, parent_names, num_parents); 492 493 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 494 node->name); 495 496 init = &mux->clk_data; 497 498 init->ops = &wiz_clk_mux_ops; 499 init->flags = CLK_SET_RATE_NO_REPARENT; 500 init->parent_names = parent_names; 501 init->num_parents = num_parents; 502 init->name = clk_name; 503 504 mux->field = field; 505 mux->table = table; 506 mux->hw.init = init; 507 508 clk = devm_clk_register(dev, &mux->hw); 509 if (IS_ERR(clk)) 510 return PTR_ERR(clk); 511 512 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 513 if (ret) 514 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 515 516 return ret; 517 } 518 519 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, 520 unsigned long parent_rate) 521 { 522 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 523 struct regmap_field *field = div->field; 524 int val; 525 526 regmap_field_read(field, &val); 527 528 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); 529 } 530 531 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 532 unsigned long *prate) 533 { 534 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 535 536 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); 537 } 538 539 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 540 unsigned long parent_rate) 541 { 542 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 543 struct regmap_field *field = div->field; 544 int val; 545 546 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); 547 if (val < 0) 548 return val; 549 550 return regmap_field_write(field, val); 551 } 552 553 static const struct clk_ops wiz_clk_div_ops = { 554 .recalc_rate = wiz_clk_div_recalc_rate, 555 .round_rate = wiz_clk_div_round_rate, 556 .set_rate = wiz_clk_div_set_rate, 557 }; 558 559 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, 560 struct regmap_field *field, 561 const struct clk_div_table *table) 562 { 563 struct device *dev = wiz->dev; 564 struct wiz_clk_divider *div; 565 struct clk_init_data *init; 566 const char **parent_names; 567 char clk_name[100]; 568 struct clk *clk; 569 int ret; 570 571 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 572 if (!div) 573 return -ENOMEM; 574 575 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 576 node->name); 577 578 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 579 if (!parent_names) 580 return -ENOMEM; 581 582 of_clk_parent_fill(node, parent_names, 1); 583 584 init = &div->clk_data; 585 586 init->ops = &wiz_clk_div_ops; 587 init->flags = 0; 588 init->parent_names = parent_names; 589 init->num_parents = 1; 590 init->name = clk_name; 591 592 div->field = field; 593 div->table = table; 594 div->hw.init = init; 595 596 clk = devm_clk_register(dev, &div->hw); 597 if (IS_ERR(clk)) 598 return PTR_ERR(clk); 599 600 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 601 if (ret) 602 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 603 604 return ret; 605 } 606 607 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) 608 { 609 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 610 struct device_node *clk_node; 611 int i; 612 613 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 614 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); 615 of_clk_del_provider(clk_node); 616 of_node_put(clk_node); 617 } 618 } 619 620 static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 621 { 622 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 623 struct device *dev = wiz->dev; 624 struct device_node *clk_node; 625 const char *node_name; 626 unsigned long rate; 627 struct clk *clk; 628 int ret; 629 int i; 630 631 clk = devm_clk_get(dev, "core_ref_clk"); 632 if (IS_ERR(clk)) { 633 dev_err(dev, "core_ref_clk clock not found\n"); 634 ret = PTR_ERR(clk); 635 return ret; 636 } 637 638 rate = clk_get_rate(clk); 639 if (rate >= 100000000) 640 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 641 else 642 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 643 644 clk = devm_clk_get(dev, "ext_ref_clk"); 645 if (IS_ERR(clk)) { 646 dev_err(dev, "ext_ref_clk clock not found\n"); 647 ret = PTR_ERR(clk); 648 return ret; 649 } 650 651 rate = clk_get_rate(clk); 652 if (rate >= 100000000) 653 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 654 else 655 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 656 657 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 658 node_name = clk_mux_sel[i].node_name; 659 clk_node = of_get_child_by_name(node, node_name); 660 if (!clk_node) { 661 dev_err(dev, "Unable to get %s node\n", node_name); 662 ret = -EINVAL; 663 goto err; 664 } 665 666 ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field, 667 clk_mux_sel[i].table); 668 if (ret) { 669 dev_err(dev, "Failed to register %s clock\n", 670 node_name); 671 of_node_put(clk_node); 672 goto err; 673 } 674 675 of_node_put(clk_node); 676 } 677 678 for (i = 0; i < wiz->clk_div_sel_num; i++) { 679 node_name = clk_div_sel[i].node_name; 680 clk_node = of_get_child_by_name(node, node_name); 681 if (!clk_node) { 682 dev_err(dev, "Unable to get %s node\n", node_name); 683 ret = -EINVAL; 684 goto err; 685 } 686 687 ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field, 688 clk_div_sel[i].table); 689 if (ret) { 690 dev_err(dev, "Failed to register %s clock\n", 691 node_name); 692 of_node_put(clk_node); 693 goto err; 694 } 695 696 of_node_put(clk_node); 697 } 698 699 return 0; 700 err: 701 wiz_clock_cleanup(wiz, node); 702 703 return ret; 704 } 705 706 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, 707 unsigned long id) 708 { 709 struct device *dev = rcdev->dev; 710 struct wiz *wiz = dev_get_drvdata(dev); 711 int ret = 0; 712 713 if (id == 0) { 714 ret = regmap_field_write(wiz->phy_reset_n, false); 715 return ret; 716 } 717 718 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); 719 return ret; 720 } 721 722 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, 723 unsigned long id) 724 { 725 struct device *dev = rcdev->dev; 726 struct wiz *wiz = dev_get_drvdata(dev); 727 int ret; 728 729 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ 730 if (id == 0 && wiz->gpio_typec_dir) { 731 if (wiz->typec_dir_delay) 732 msleep_interruptible(wiz->typec_dir_delay); 733 734 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) 735 regmap_field_write(wiz->typec_ln10_swap, 1); 736 else 737 regmap_field_write(wiz->typec_ln10_swap, 0); 738 } 739 740 if (id == 0) { 741 ret = regmap_field_write(wiz->phy_reset_n, true); 742 return ret; 743 } 744 745 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) 746 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); 747 else 748 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); 749 750 return ret; 751 } 752 753 static const struct reset_control_ops wiz_phy_reset_ops = { 754 .assert = wiz_phy_reset_assert, 755 .deassert = wiz_phy_reset_deassert, 756 }; 757 758 static const struct regmap_config wiz_regmap_config = { 759 .reg_bits = 32, 760 .val_bits = 32, 761 .reg_stride = 4, 762 .fast_io = true, 763 }; 764 765 static const struct of_device_id wiz_id_table[] = { 766 { 767 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G 768 }, 769 { 770 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G 771 }, 772 {} 773 }; 774 MODULE_DEVICE_TABLE(of, wiz_id_table); 775 776 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) 777 { 778 struct device_node *serdes, *subnode; 779 780 serdes = of_get_child_by_name(dev->of_node, "serdes"); 781 if (!serdes) { 782 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); 783 return -EINVAL; 784 } 785 786 for_each_child_of_node(serdes, subnode) { 787 u32 reg, num_lanes = 1, phy_type = PHY_NONE; 788 int ret, i; 789 790 ret = of_property_read_u32(subnode, "reg", ®); 791 if (ret) { 792 dev_err(dev, 793 "%s: Reading \"reg\" from \"%s\" failed: %d\n", 794 __func__, subnode->name, ret); 795 of_node_put(subnode); 796 return ret; 797 } 798 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); 799 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); 800 801 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, 802 reg, reg + num_lanes - 1, phy_type); 803 804 for (i = reg; i < reg + num_lanes; i++) 805 wiz->lane_phy_type[i] = phy_type; 806 } 807 808 return 0; 809 } 810 811 static int wiz_probe(struct platform_device *pdev) 812 { 813 struct reset_controller_dev *phy_reset_dev; 814 struct device *dev = &pdev->dev; 815 struct device_node *node = dev->of_node; 816 struct platform_device *serdes_pdev; 817 struct device_node *child_node; 818 struct regmap *regmap; 819 struct resource res; 820 void __iomem *base; 821 struct wiz *wiz; 822 u32 num_lanes; 823 int ret; 824 825 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); 826 if (!wiz) 827 return -ENOMEM; 828 829 wiz->type = (enum wiz_type)of_device_get_match_data(dev); 830 831 child_node = of_get_child_by_name(node, "serdes"); 832 if (!child_node) { 833 dev_err(dev, "Failed to get SERDES child DT node\n"); 834 return -ENODEV; 835 } 836 837 ret = of_address_to_resource(child_node, 0, &res); 838 if (ret) { 839 dev_err(dev, "Failed to get memory resource\n"); 840 goto err_addr_to_resource; 841 } 842 843 base = devm_ioremap(dev, res.start, resource_size(&res)); 844 if (!base) { 845 ret = -ENOMEM; 846 goto err_addr_to_resource; 847 } 848 849 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); 850 if (IS_ERR(regmap)) { 851 dev_err(dev, "Failed to initialize regmap\n"); 852 ret = PTR_ERR(regmap); 853 goto err_addr_to_resource; 854 } 855 856 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 857 if (ret) { 858 dev_err(dev, "Failed to read num-lanes property\n"); 859 goto err_addr_to_resource; 860 } 861 862 if (num_lanes > WIZ_MAX_LANES) { 863 dev_err(dev, "Cannot support %d lanes\n", num_lanes); 864 ret = -ENODEV; 865 goto err_addr_to_resource; 866 } 867 868 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", 869 GPIOD_IN); 870 if (IS_ERR(wiz->gpio_typec_dir)) { 871 ret = PTR_ERR(wiz->gpio_typec_dir); 872 if (ret != -EPROBE_DEFER) 873 dev_err(dev, "Failed to request typec-dir gpio: %d\n", 874 ret); 875 goto err_addr_to_resource; 876 } 877 878 if (wiz->gpio_typec_dir) { 879 ret = of_property_read_u32(node, "typec-dir-debounce-ms", 880 &wiz->typec_dir_delay); 881 if (ret && ret != -EINVAL) { 882 dev_err(dev, "Invalid typec-dir-debounce property\n"); 883 goto err_addr_to_resource; 884 } 885 886 /* use min. debounce from Type-C spec if not provided in DT */ 887 if (ret == -EINVAL) 888 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; 889 890 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 891 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 892 dev_err(dev, "Invalid typec-dir-debounce property\n"); 893 goto err_addr_to_resource; 894 } 895 } 896 897 ret = wiz_get_lane_phy_types(dev, wiz); 898 if (ret) 899 return ret; 900 901 wiz->dev = dev; 902 wiz->regmap = regmap; 903 wiz->num_lanes = num_lanes; 904 if (wiz->type == J721E_WIZ_10G) 905 wiz->clk_mux_sel = clk_mux_sel_10g; 906 else 907 wiz->clk_mux_sel = clk_mux_sel_16g; 908 909 wiz->clk_div_sel = clk_div_sel; 910 911 if (wiz->type == J721E_WIZ_10G) 912 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G; 913 else 914 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G; 915 916 platform_set_drvdata(pdev, wiz); 917 918 ret = wiz_regfield_init(wiz); 919 if (ret) { 920 dev_err(dev, "Failed to initialize regfields\n"); 921 goto err_addr_to_resource; 922 } 923 924 phy_reset_dev = &wiz->wiz_phy_reset_dev; 925 phy_reset_dev->dev = dev; 926 phy_reset_dev->ops = &wiz_phy_reset_ops, 927 phy_reset_dev->owner = THIS_MODULE, 928 phy_reset_dev->of_node = node; 929 /* Reset for each of the lane and one for the entire SERDES */ 930 phy_reset_dev->nr_resets = num_lanes + 1; 931 932 ret = devm_reset_controller_register(dev, phy_reset_dev); 933 if (ret < 0) { 934 dev_warn(dev, "Failed to register reset controller\n"); 935 goto err_addr_to_resource; 936 } 937 938 pm_runtime_enable(dev); 939 ret = pm_runtime_get_sync(dev); 940 if (ret < 0) { 941 dev_err(dev, "pm_runtime_get_sync failed\n"); 942 goto err_get_sync; 943 } 944 945 ret = wiz_clock_init(wiz, node); 946 if (ret < 0) { 947 dev_warn(dev, "Failed to initialize clocks\n"); 948 goto err_get_sync; 949 } 950 951 serdes_pdev = of_platform_device_create(child_node, NULL, dev); 952 if (!serdes_pdev) { 953 dev_WARN(dev, "Unable to create SERDES platform device\n"); 954 ret = -ENOMEM; 955 goto err_pdev_create; 956 } 957 wiz->serdes_pdev = serdes_pdev; 958 959 ret = wiz_init(wiz); 960 if (ret) { 961 dev_err(dev, "WIZ initialization failed\n"); 962 goto err_wiz_init; 963 } 964 965 of_node_put(child_node); 966 return 0; 967 968 err_wiz_init: 969 of_platform_device_destroy(&serdes_pdev->dev, NULL); 970 971 err_pdev_create: 972 wiz_clock_cleanup(wiz, node); 973 974 err_get_sync: 975 pm_runtime_put(dev); 976 pm_runtime_disable(dev); 977 978 err_addr_to_resource: 979 of_node_put(child_node); 980 981 return ret; 982 } 983 984 static int wiz_remove(struct platform_device *pdev) 985 { 986 struct device *dev = &pdev->dev; 987 struct device_node *node = dev->of_node; 988 struct platform_device *serdes_pdev; 989 struct wiz *wiz; 990 991 wiz = dev_get_drvdata(dev); 992 serdes_pdev = wiz->serdes_pdev; 993 994 of_platform_device_destroy(&serdes_pdev->dev, NULL); 995 wiz_clock_cleanup(wiz, node); 996 pm_runtime_put(dev); 997 pm_runtime_disable(dev); 998 999 return 0; 1000 } 1001 1002 static struct platform_driver wiz_driver = { 1003 .probe = wiz_probe, 1004 .remove = wiz_remove, 1005 .driver = { 1006 .name = "wiz", 1007 .of_match_table = wiz_id_table, 1008 }, 1009 }; 1010 module_platform_driver(wiz_driver); 1011 1012 MODULE_AUTHOR("Texas Instruments Inc."); 1013 MODULE_DESCRIPTION("TI J721E WIZ driver"); 1014 MODULE_LICENSE("GPL v2"); 1015