1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe SERDES driver for AM654x SoC 4 * 5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/mux/consumer.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 22 #define CMU_R004 0x4 23 #define CMU_R060 0x60 24 #define CMU_R07C 0x7c 25 #define CMU_R088 0x88 26 #define CMU_R0D0 0xd0 27 #define CMU_R0E8 0xe8 28 29 #define LANE_R048 0x248 30 #define LANE_R058 0x258 31 #define LANE_R06c 0x26c 32 #define LANE_R070 0x270 33 #define LANE_R19C 0x39c 34 35 #define COMLANE_R004 0xa04 36 #define COMLANE_R138 0xb38 37 #define VERSION_VAL 0x70 38 39 #define COMLANE_R190 0xb90 40 #define COMLANE_R194 0xb94 41 42 #define COMRXEQ_R004 0x1404 43 #define COMRXEQ_R008 0x1408 44 #define COMRXEQ_R00C 0x140c 45 #define COMRXEQ_R014 0x1414 46 #define COMRXEQ_R018 0x1418 47 #define COMRXEQ_R01C 0x141c 48 #define COMRXEQ_R04C 0x144c 49 #define COMRXEQ_R088 0x1488 50 #define COMRXEQ_R094 0x1494 51 #define COMRXEQ_R098 0x1498 52 53 #define SERDES_CTRL 0x1fd0 54 55 #define WIZ_LANEXCTL_STS 0x1fe0 56 #define TX0_DISABLE_STATE 0x4 57 #define TX0_SLEEP_STATE 0x5 58 #define TX0_SNOOZE_STATE 0x6 59 #define TX0_ENABLE_STATE 0x7 60 61 #define RX0_DISABLE_STATE 0x4 62 #define RX0_SLEEP_STATE 0x5 63 #define RX0_SNOOZE_STATE 0x6 64 #define RX0_ENABLE_STATE 0x7 65 66 #define WIZ_PLL_CTRL 0x1ff4 67 #define PLL_DISABLE_STATE 0x4 68 #define PLL_SLEEP_STATE 0x5 69 #define PLL_SNOOZE_STATE 0x6 70 #define PLL_ENABLE_STATE 0x7 71 72 #define PLL_LOCK_TIME 100000 /* in microseconds */ 73 #define SLEEP_TIME 100 /* in microseconds */ 74 75 #define LANE_USB3 0x0 76 #define LANE_PCIE0_LANE0 0x1 77 78 #define LANE_PCIE1_LANE0 0x0 79 #define LANE_PCIE0_LANE1 0x1 80 81 #define SERDES_NUM_CLOCKS 3 82 83 #define AM654_SERDES_CTRL_CLKSEL_MASK GENMASK(7, 4) 84 #define AM654_SERDES_CTRL_CLKSEL_SHIFT 4 85 86 struct serdes_am654_clk_mux { 87 struct clk_hw hw; 88 struct regmap *regmap; 89 unsigned int reg; 90 int clk_id; 91 struct clk_init_data clk_data; 92 }; 93 94 #define to_serdes_am654_clk_mux(_hw) \ 95 container_of(_hw, struct serdes_am654_clk_mux, hw) 96 97 static const struct regmap_config serdes_am654_regmap_config = { 98 .reg_bits = 32, 99 .val_bits = 32, 100 .reg_stride = 4, 101 .fast_io = true, 102 .max_register = 0x1ffc, 103 }; 104 105 enum serdes_am654_fields { 106 /* CMU PLL Control */ 107 CMU_PLL_CTRL, 108 109 LANE_PLL_CTRL_RXEQ_RXIDLE, 110 111 /* CMU VCO bias current and VREG setting */ 112 AHB_PMA_CM_VCO_VBIAS_VREG, 113 AHB_PMA_CM_VCO_BIAS_VREG, 114 115 AHB_PMA_CM_SR, 116 AHB_SSC_GEN_Z_O_20_13, 117 118 /* AHB PMA Lane Configuration */ 119 AHB_PMA_LN_AGC_THSEL_VREGH, 120 121 /* AGC and Signal detect threshold for Gen3 */ 122 AHB_PMA_LN_GEN3_AGC_SD_THSEL, 123 124 AHB_PMA_LN_RX_SELR_GEN3, 125 AHB_PMA_LN_TX_DRV, 126 127 /* CMU Master Reset */ 128 CMU_MASTER_CDN, 129 130 /* P2S ring buffer initial startup pointer difference */ 131 P2S_RBUF_PTR_DIFF, 132 133 CONFIG_VERSION, 134 135 /* Lane 1 Master Reset */ 136 L1_MASTER_CDN, 137 138 /* CMU OK Status */ 139 CMU_OK_I_0, 140 141 /* Mid-speed initial calibration control */ 142 COMRXEQ_MS_INIT_CTRL_7_0, 143 144 /* High-speed initial calibration control */ 145 COMRXEQ_HS_INIT_CAL_7_0, 146 147 /* Mid-speed recalibration control */ 148 COMRXEQ_MS_RECAL_CTRL_7_0, 149 150 /* High-speed recalibration control */ 151 COMRXEQ_HS_RECAL_CTRL_7_0, 152 153 /* ATT configuration */ 154 COMRXEQ_CSR_ATT_CONFIG, 155 156 /* Edge based boost adaptation window length */ 157 COMRXEQ_CSR_EBSTADAPT_WIN_LEN, 158 159 /* COMRXEQ control 3 & 4 */ 160 COMRXEQ_CTRL_3_4, 161 162 /* COMRXEQ control 14, 15 and 16*/ 163 COMRXEQ_CTRL_14_15_16, 164 165 /* Threshold for errors in pattern data */ 166 COMRXEQ_CSR_DLEV_ERR_THRESH, 167 168 /* COMRXEQ control 25 */ 169 COMRXEQ_CTRL_25, 170 171 /* Mid-speed rate change calibration control */ 172 CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O, 173 174 /* High-speed rate change calibration control */ 175 COMRXEQ_HS_RCHANGE_CTRL_7_0, 176 177 /* Serdes reset */ 178 POR_EN, 179 180 /* Tx Enable Value */ 181 TX0_ENABLE, 182 183 /* Rx Enable Value */ 184 RX0_ENABLE, 185 186 /* PLL Enable Value */ 187 PLL_ENABLE, 188 189 /* PLL ready for use */ 190 PLL_OK, 191 192 /* sentinel */ 193 MAX_FIELDS 194 195 }; 196 197 static const struct reg_field serdes_am654_reg_fields[] = { 198 [CMU_PLL_CTRL] = REG_FIELD(CMU_R004, 8, 15), 199 [AHB_PMA_CM_VCO_VBIAS_VREG] = REG_FIELD(CMU_R060, 8, 15), 200 [CMU_MASTER_CDN] = REG_FIELD(CMU_R07C, 24, 31), 201 [AHB_PMA_CM_VCO_BIAS_VREG] = REG_FIELD(CMU_R088, 24, 31), 202 [AHB_PMA_CM_SR] = REG_FIELD(CMU_R0D0, 24, 31), 203 [AHB_SSC_GEN_Z_O_20_13] = REG_FIELD(CMU_R0E8, 8, 15), 204 [LANE_PLL_CTRL_RXEQ_RXIDLE] = REG_FIELD(LANE_R048, 8, 15), 205 [AHB_PMA_LN_AGC_THSEL_VREGH] = REG_FIELD(LANE_R058, 16, 23), 206 [AHB_PMA_LN_GEN3_AGC_SD_THSEL] = REG_FIELD(LANE_R06c, 0, 7), 207 [AHB_PMA_LN_RX_SELR_GEN3] = REG_FIELD(LANE_R070, 16, 23), 208 [AHB_PMA_LN_TX_DRV] = REG_FIELD(LANE_R19C, 16, 23), 209 [P2S_RBUF_PTR_DIFF] = REG_FIELD(COMLANE_R004, 0, 7), 210 [CONFIG_VERSION] = REG_FIELD(COMLANE_R138, 16, 23), 211 [L1_MASTER_CDN] = REG_FIELD(COMLANE_R190, 8, 15), 212 [CMU_OK_I_0] = REG_FIELD(COMLANE_R194, 19, 19), 213 [COMRXEQ_MS_INIT_CTRL_7_0] = REG_FIELD(COMRXEQ_R004, 24, 31), 214 [COMRXEQ_HS_INIT_CAL_7_0] = REG_FIELD(COMRXEQ_R008, 0, 7), 215 [COMRXEQ_MS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 8, 15), 216 [COMRXEQ_HS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 16, 23), 217 [COMRXEQ_CSR_ATT_CONFIG] = REG_FIELD(COMRXEQ_R014, 16, 23), 218 [COMRXEQ_CSR_EBSTADAPT_WIN_LEN] = REG_FIELD(COMRXEQ_R018, 16, 23), 219 [COMRXEQ_CTRL_3_4] = REG_FIELD(COMRXEQ_R01C, 8, 15), 220 [COMRXEQ_CTRL_14_15_16] = REG_FIELD(COMRXEQ_R04C, 0, 7), 221 [COMRXEQ_CSR_DLEV_ERR_THRESH] = REG_FIELD(COMRXEQ_R088, 16, 23), 222 [COMRXEQ_CTRL_25] = REG_FIELD(COMRXEQ_R094, 24, 31), 223 [CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O] = REG_FIELD(COMRXEQ_R098, 8, 15), 224 [COMRXEQ_HS_RCHANGE_CTRL_7_0] = REG_FIELD(COMRXEQ_R098, 16, 23), 225 [POR_EN] = REG_FIELD(SERDES_CTRL, 29, 29), 226 [TX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 29, 31), 227 [RX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 13, 15), 228 [PLL_ENABLE] = REG_FIELD(WIZ_PLL_CTRL, 29, 31), 229 [PLL_OK] = REG_FIELD(WIZ_PLL_CTRL, 28, 28), 230 }; 231 232 struct serdes_am654 { 233 struct regmap *regmap; 234 struct regmap_field *fields[MAX_FIELDS]; 235 236 struct device *dev; 237 struct mux_control *control; 238 bool busy; 239 u32 type; 240 struct device_node *of_node; 241 struct clk_onecell_data clk_data; 242 struct clk *clks[SERDES_NUM_CLOCKS]; 243 }; 244 245 static int serdes_am654_enable_pll(struct serdes_am654 *phy) 246 { 247 int ret; 248 u32 val; 249 250 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE); 251 if (ret) 252 return ret; 253 254 return regmap_field_read_poll_timeout(phy->fields[PLL_OK], val, val, 255 1000, PLL_LOCK_TIME); 256 } 257 258 static void serdes_am654_disable_pll(struct serdes_am654 *phy) 259 { 260 struct device *dev = phy->dev; 261 int ret; 262 263 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE); 264 if (ret) 265 dev_err(dev, "Failed to disable PLL\n"); 266 } 267 268 static int serdes_am654_enable_txrx(struct serdes_am654 *phy) 269 { 270 int ret = 0; 271 272 /* Enable TX */ 273 ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_ENABLE_STATE); 274 275 /* Enable RX */ 276 ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_ENABLE_STATE); 277 278 if (ret) 279 return -EIO; 280 281 return 0; 282 } 283 284 static int serdes_am654_disable_txrx(struct serdes_am654 *phy) 285 { 286 int ret = 0; 287 288 /* Disable TX */ 289 ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_DISABLE_STATE); 290 291 /* Disable RX */ 292 ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_DISABLE_STATE); 293 294 if (ret) 295 return -EIO; 296 297 return 0; 298 } 299 300 static int serdes_am654_power_on(struct phy *x) 301 { 302 struct serdes_am654 *phy = phy_get_drvdata(x); 303 struct device *dev = phy->dev; 304 int ret; 305 u32 val; 306 307 ret = serdes_am654_enable_pll(phy); 308 if (ret) { 309 dev_err(dev, "Failed to enable PLL\n"); 310 return ret; 311 } 312 313 ret = serdes_am654_enable_txrx(phy); 314 if (ret) { 315 dev_err(dev, "Failed to enable TX RX\n"); 316 return ret; 317 } 318 319 return regmap_field_read_poll_timeout(phy->fields[CMU_OK_I_0], val, 320 val, SLEEP_TIME, PLL_LOCK_TIME); 321 } 322 323 static int serdes_am654_power_off(struct phy *x) 324 { 325 struct serdes_am654 *phy = phy_get_drvdata(x); 326 327 serdes_am654_disable_txrx(phy); 328 serdes_am654_disable_pll(phy); 329 330 return 0; 331 } 332 333 #define SERDES_AM654_CFG(offset, a, b, val) \ 334 regmap_update_bits(phy->regmap, (offset),\ 335 GENMASK((a), (b)), (val) << (b)) 336 337 static int serdes_am654_usb3_init(struct serdes_am654 *phy) 338 { 339 SERDES_AM654_CFG(0x0000, 31, 24, 0x17); 340 SERDES_AM654_CFG(0x0004, 15, 8, 0x02); 341 SERDES_AM654_CFG(0x0004, 7, 0, 0x0e); 342 SERDES_AM654_CFG(0x0008, 23, 16, 0x2e); 343 SERDES_AM654_CFG(0x0008, 31, 24, 0x2e); 344 SERDES_AM654_CFG(0x0060, 7, 0, 0x4b); 345 SERDES_AM654_CFG(0x0060, 15, 8, 0x98); 346 SERDES_AM654_CFG(0x0060, 23, 16, 0x60); 347 SERDES_AM654_CFG(0x00d0, 31, 24, 0x45); 348 SERDES_AM654_CFG(0x00e8, 15, 8, 0x0e); 349 SERDES_AM654_CFG(0x0220, 7, 0, 0x34); 350 SERDES_AM654_CFG(0x0220, 15, 8, 0x34); 351 SERDES_AM654_CFG(0x0220, 31, 24, 0x37); 352 SERDES_AM654_CFG(0x0224, 7, 0, 0x37); 353 SERDES_AM654_CFG(0x0224, 15, 8, 0x37); 354 SERDES_AM654_CFG(0x0228, 23, 16, 0x37); 355 SERDES_AM654_CFG(0x0228, 31, 24, 0x37); 356 SERDES_AM654_CFG(0x022c, 7, 0, 0x37); 357 SERDES_AM654_CFG(0x022c, 15, 8, 0x37); 358 SERDES_AM654_CFG(0x0230, 15, 8, 0x2a); 359 SERDES_AM654_CFG(0x0230, 23, 16, 0x2a); 360 SERDES_AM654_CFG(0x0240, 23, 16, 0x10); 361 SERDES_AM654_CFG(0x0240, 31, 24, 0x34); 362 SERDES_AM654_CFG(0x0244, 7, 0, 0x40); 363 SERDES_AM654_CFG(0x0244, 23, 16, 0x34); 364 SERDES_AM654_CFG(0x0248, 15, 8, 0x0d); 365 SERDES_AM654_CFG(0x0258, 15, 8, 0x16); 366 SERDES_AM654_CFG(0x0258, 23, 16, 0x84); 367 SERDES_AM654_CFG(0x0258, 31, 24, 0xf2); 368 SERDES_AM654_CFG(0x025c, 7, 0, 0x21); 369 SERDES_AM654_CFG(0x0260, 7, 0, 0x27); 370 SERDES_AM654_CFG(0x0260, 15, 8, 0x04); 371 SERDES_AM654_CFG(0x0268, 15, 8, 0x04); 372 SERDES_AM654_CFG(0x0288, 15, 8, 0x2c); 373 SERDES_AM654_CFG(0x0330, 31, 24, 0xa0); 374 SERDES_AM654_CFG(0x0338, 23, 16, 0x03); 375 SERDES_AM654_CFG(0x0338, 31, 24, 0x00); 376 SERDES_AM654_CFG(0x033c, 7, 0, 0x00); 377 SERDES_AM654_CFG(0x0344, 31, 24, 0x18); 378 SERDES_AM654_CFG(0x034c, 7, 0, 0x18); 379 SERDES_AM654_CFG(0x039c, 23, 16, 0x3b); 380 SERDES_AM654_CFG(0x0a04, 7, 0, 0x03); 381 SERDES_AM654_CFG(0x0a14, 31, 24, 0x3c); 382 SERDES_AM654_CFG(0x0a18, 15, 8, 0x3c); 383 SERDES_AM654_CFG(0x0a38, 7, 0, 0x3e); 384 SERDES_AM654_CFG(0x0a38, 15, 8, 0x3e); 385 SERDES_AM654_CFG(0x0ae0, 7, 0, 0x07); 386 SERDES_AM654_CFG(0x0b6c, 23, 16, 0xcd); 387 SERDES_AM654_CFG(0x0b6c, 31, 24, 0x04); 388 SERDES_AM654_CFG(0x0b98, 23, 16, 0x03); 389 SERDES_AM654_CFG(0x1400, 7, 0, 0x3f); 390 SERDES_AM654_CFG(0x1404, 23, 16, 0x6f); 391 SERDES_AM654_CFG(0x1404, 31, 24, 0x6f); 392 SERDES_AM654_CFG(0x140c, 7, 0, 0x6f); 393 SERDES_AM654_CFG(0x140c, 15, 8, 0x6f); 394 SERDES_AM654_CFG(0x1410, 15, 8, 0x27); 395 SERDES_AM654_CFG(0x1414, 7, 0, 0x0c); 396 SERDES_AM654_CFG(0x1414, 23, 16, 0x07); 397 SERDES_AM654_CFG(0x1418, 23, 16, 0x40); 398 SERDES_AM654_CFG(0x141c, 7, 0, 0x00); 399 SERDES_AM654_CFG(0x141c, 15, 8, 0x1f); 400 SERDES_AM654_CFG(0x1428, 31, 24, 0x08); 401 SERDES_AM654_CFG(0x1434, 31, 24, 0x00); 402 SERDES_AM654_CFG(0x1444, 7, 0, 0x94); 403 SERDES_AM654_CFG(0x1460, 31, 24, 0x7f); 404 SERDES_AM654_CFG(0x1464, 7, 0, 0x43); 405 SERDES_AM654_CFG(0x1464, 23, 16, 0x6f); 406 SERDES_AM654_CFG(0x1464, 31, 24, 0x43); 407 SERDES_AM654_CFG(0x1484, 23, 16, 0x8f); 408 SERDES_AM654_CFG(0x1498, 7, 0, 0x4f); 409 SERDES_AM654_CFG(0x1498, 23, 16, 0x4f); 410 SERDES_AM654_CFG(0x007c, 31, 24, 0x0d); 411 SERDES_AM654_CFG(0x0b90, 15, 8, 0x0f); 412 413 return 0; 414 } 415 416 static int serdes_am654_pcie_init(struct serdes_am654 *phy) 417 { 418 int ret = 0; 419 420 ret |= regmap_field_write(phy->fields[CMU_PLL_CTRL], 0x2); 421 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_VBIAS_VREG], 0x98); 422 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_BIAS_VREG], 0x98); 423 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_SR], 0x45); 424 ret |= regmap_field_write(phy->fields[AHB_SSC_GEN_Z_O_20_13], 0xe); 425 ret |= regmap_field_write(phy->fields[LANE_PLL_CTRL_RXEQ_RXIDLE], 0x5); 426 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_AGC_THSEL_VREGH], 0x83); 427 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_GEN3_AGC_SD_THSEL], 0x83); 428 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_RX_SELR_GEN3], 0x81); 429 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_TX_DRV], 0x3b); 430 ret |= regmap_field_write(phy->fields[P2S_RBUF_PTR_DIFF], 0x3); 431 ret |= regmap_field_write(phy->fields[CONFIG_VERSION], VERSION_VAL); 432 ret |= regmap_field_write(phy->fields[COMRXEQ_MS_INIT_CTRL_7_0], 0xf); 433 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_INIT_CAL_7_0], 0x4f); 434 ret |= regmap_field_write(phy->fields[COMRXEQ_MS_RECAL_CTRL_7_0], 0xf); 435 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RECAL_CTRL_7_0], 0x4f); 436 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_ATT_CONFIG], 0x7); 437 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_EBSTADAPT_WIN_LEN], 0x7f); 438 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_3_4], 0xf); 439 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_14_15_16], 0x9a); 440 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_DLEV_ERR_THRESH], 0x32); 441 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_25], 0x80); 442 ret |= regmap_field_write(phy->fields[CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O], 0xf); 443 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RCHANGE_CTRL_7_0], 0x4f); 444 ret |= regmap_field_write(phy->fields[CMU_MASTER_CDN], 0x1); 445 ret |= regmap_field_write(phy->fields[L1_MASTER_CDN], 0x2); 446 447 if (ret) 448 return -EIO; 449 450 return 0; 451 } 452 453 static int serdes_am654_init(struct phy *x) 454 { 455 struct serdes_am654 *phy = phy_get_drvdata(x); 456 457 switch (phy->type) { 458 case PHY_TYPE_PCIE: 459 return serdes_am654_pcie_init(phy); 460 case PHY_TYPE_USB3: 461 return serdes_am654_usb3_init(phy); 462 default: 463 return -EINVAL; 464 } 465 } 466 467 static int serdes_am654_reset(struct phy *x) 468 { 469 struct serdes_am654 *phy = phy_get_drvdata(x); 470 int ret = 0; 471 472 serdes_am654_disable_pll(phy); 473 serdes_am654_disable_txrx(phy); 474 475 ret |= regmap_field_write(phy->fields[POR_EN], 0x1); 476 477 mdelay(1); 478 479 ret |= regmap_field_write(phy->fields[POR_EN], 0x0); 480 481 if (ret) 482 return -EIO; 483 484 return 0; 485 } 486 487 static void serdes_am654_release(struct phy *x) 488 { 489 struct serdes_am654 *phy = phy_get_drvdata(x); 490 491 phy->type = PHY_NONE; 492 phy->busy = false; 493 mux_control_deselect(phy->control); 494 } 495 496 static struct phy *serdes_am654_xlate(struct device *dev, 497 const struct of_phandle_args *args) 498 { 499 struct serdes_am654 *am654_phy; 500 struct phy *phy; 501 int ret; 502 503 phy = of_phy_simple_xlate(dev, args); 504 if (IS_ERR(phy)) 505 return phy; 506 507 am654_phy = phy_get_drvdata(phy); 508 if (am654_phy->busy) 509 return ERR_PTR(-EBUSY); 510 511 ret = mux_control_select(am654_phy->control, args->args[1]); 512 if (ret) { 513 dev_err(dev, "Failed to select SERDES Lane Function\n"); 514 return ERR_PTR(ret); 515 } 516 517 am654_phy->busy = true; 518 am654_phy->type = args->args[0]; 519 520 return phy; 521 } 522 523 static const struct phy_ops ops = { 524 .reset = serdes_am654_reset, 525 .init = serdes_am654_init, 526 .power_on = serdes_am654_power_on, 527 .power_off = serdes_am654_power_off, 528 .release = serdes_am654_release, 529 .owner = THIS_MODULE, 530 }; 531 532 #define SERDES_NUM_MUX_COMBINATIONS 16 533 534 #define LICLK 0 535 #define EXT_REFCLK 1 536 #define RICLK 2 537 538 static const int 539 serdes_am654_mux_table[SERDES_NUM_MUX_COMBINATIONS][SERDES_NUM_CLOCKS] = { 540 /* 541 * Each combination maps to one of 542 * "Figure 12-1986. SerDes Reference Clock Distribution" 543 * in TRM. 544 */ 545 /* Parent of CMU refclk, Left output, Right output 546 * either of EXT_REFCLK, LICLK, RICLK 547 */ 548 { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0000 */ 549 { RICLK, EXT_REFCLK, EXT_REFCLK }, /* 0001 */ 550 { EXT_REFCLK, RICLK, LICLK }, /* 0010 */ 551 { RICLK, RICLK, EXT_REFCLK }, /* 0011 */ 552 { LICLK, EXT_REFCLK, EXT_REFCLK }, /* 0100 */ 553 { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0101 */ 554 { LICLK, RICLK, LICLK }, /* 0110 */ 555 { EXT_REFCLK, RICLK, LICLK }, /* 0111 */ 556 { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1000 */ 557 { RICLK, EXT_REFCLK, LICLK }, /* 1001 */ 558 { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1010 */ 559 { RICLK, RICLK, EXT_REFCLK }, /* 1011 */ 560 { LICLK, EXT_REFCLK, LICLK }, /* 1100 */ 561 { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1101 */ 562 { LICLK, RICLK, EXT_REFCLK }, /* 1110 */ 563 { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1111 */ 564 }; 565 566 static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw) 567 { 568 struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw); 569 struct regmap *regmap = mux->regmap; 570 unsigned int reg = mux->reg; 571 unsigned int val; 572 573 regmap_read(regmap, reg, &val); 574 val &= AM654_SERDES_CTRL_CLKSEL_MASK; 575 val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT; 576 577 return serdes_am654_mux_table[val][mux->clk_id]; 578 } 579 580 static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index) 581 { 582 struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw); 583 struct regmap *regmap = mux->regmap; 584 const char *name = clk_hw_get_name(hw); 585 unsigned int reg = mux->reg; 586 int clk_id = mux->clk_id; 587 int parents[SERDES_NUM_CLOCKS]; 588 const int *p; 589 u32 val; 590 int found, i; 591 int ret; 592 593 /* get existing setting */ 594 regmap_read(regmap, reg, &val); 595 val &= AM654_SERDES_CTRL_CLKSEL_MASK; 596 val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT; 597 598 for (i = 0; i < SERDES_NUM_CLOCKS; i++) 599 parents[i] = serdes_am654_mux_table[val][i]; 600 601 /* change parent of this clock. others left intact */ 602 parents[clk_id] = index; 603 604 /* Find the match */ 605 for (val = 0; val < SERDES_NUM_MUX_COMBINATIONS; val++) { 606 p = serdes_am654_mux_table[val]; 607 found = 1; 608 for (i = 0; i < SERDES_NUM_CLOCKS; i++) { 609 if (parents[i] != p[i]) { 610 found = 0; 611 break; 612 } 613 } 614 615 if (found) 616 break; 617 } 618 619 if (!found) { 620 /* 621 * This can never happen, unless we missed 622 * a valid combination in serdes_am654_mux_table. 623 */ 624 WARN(1, "Failed to find the parent of %s clock\n", name); 625 return -EINVAL; 626 } 627 628 val <<= AM654_SERDES_CTRL_CLKSEL_SHIFT; 629 ret = regmap_update_bits(regmap, reg, AM654_SERDES_CTRL_CLKSEL_MASK, 630 val); 631 632 return ret; 633 } 634 635 static const struct clk_ops serdes_am654_clk_mux_ops = { 636 .determine_rate = __clk_mux_determine_rate, 637 .set_parent = serdes_am654_clk_mux_set_parent, 638 .get_parent = serdes_am654_clk_mux_get_parent, 639 }; 640 641 static int serdes_am654_clk_register(struct serdes_am654 *am654_phy, 642 const char *clock_name, int clock_num) 643 { 644 struct device_node *node = am654_phy->of_node; 645 struct device *dev = am654_phy->dev; 646 struct serdes_am654_clk_mux *mux; 647 struct device_node *regmap_node; 648 const char **parent_names; 649 struct clk_init_data *init; 650 unsigned int num_parents; 651 struct regmap *regmap; 652 const __be32 *addr; 653 unsigned int reg; 654 struct clk *clk; 655 int ret = 0; 656 657 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 658 if (!mux) 659 return -ENOMEM; 660 661 init = &mux->clk_data; 662 663 regmap_node = of_parse_phandle(node, "ti,serdes-clk", 0); 664 if (!regmap_node) { 665 dev_err(dev, "Fail to get serdes-clk node\n"); 666 ret = -ENODEV; 667 goto out_put_node; 668 } 669 670 regmap = syscon_node_to_regmap(regmap_node->parent); 671 if (IS_ERR(regmap)) { 672 dev_err(dev, "Fail to get Syscon regmap\n"); 673 ret = PTR_ERR(regmap); 674 goto out_put_node; 675 } 676 677 num_parents = of_clk_get_parent_count(node); 678 if (num_parents < 2) { 679 dev_err(dev, "SERDES clock must have parents\n"); 680 ret = -EINVAL; 681 goto out_put_node; 682 } 683 684 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 685 GFP_KERNEL); 686 if (!parent_names) { 687 ret = -ENOMEM; 688 goto out_put_node; 689 } 690 691 of_clk_parent_fill(node, parent_names, num_parents); 692 693 addr = of_get_address(regmap_node, 0, NULL, NULL); 694 if (!addr) { 695 ret = -EINVAL; 696 goto out_put_node; 697 } 698 699 reg = be32_to_cpu(*addr); 700 701 init->ops = &serdes_am654_clk_mux_ops; 702 init->flags = CLK_SET_RATE_NO_REPARENT; 703 init->parent_names = parent_names; 704 init->num_parents = num_parents; 705 init->name = clock_name; 706 707 mux->regmap = regmap; 708 mux->reg = reg; 709 mux->clk_id = clock_num; 710 mux->hw.init = init; 711 712 clk = devm_clk_register(dev, &mux->hw); 713 if (IS_ERR(clk)) { 714 ret = PTR_ERR(clk); 715 goto out_put_node; 716 } 717 718 am654_phy->clks[clock_num] = clk; 719 720 out_put_node: 721 of_node_put(regmap_node); 722 return ret; 723 } 724 725 static const struct of_device_id serdes_am654_id_table[] = { 726 { 727 .compatible = "ti,phy-am654-serdes", 728 }, 729 {} 730 }; 731 MODULE_DEVICE_TABLE(of, serdes_am654_id_table); 732 733 static int serdes_am654_regfield_init(struct serdes_am654 *am654_phy) 734 { 735 struct regmap *regmap = am654_phy->regmap; 736 struct device *dev = am654_phy->dev; 737 int i; 738 739 for (i = 0; i < MAX_FIELDS; i++) { 740 am654_phy->fields[i] = devm_regmap_field_alloc(dev, 741 regmap, 742 serdes_am654_reg_fields[i]); 743 if (IS_ERR(am654_phy->fields[i])) { 744 dev_err(dev, "Unable to allocate regmap field %d\n", i); 745 return PTR_ERR(am654_phy->fields[i]); 746 } 747 } 748 749 return 0; 750 } 751 752 static int serdes_am654_probe(struct platform_device *pdev) 753 { 754 struct phy_provider *phy_provider; 755 struct device *dev = &pdev->dev; 756 struct device_node *node = dev->of_node; 757 struct clk_onecell_data *clk_data; 758 struct serdes_am654 *am654_phy; 759 struct mux_control *control; 760 const char *clock_name; 761 struct regmap *regmap; 762 void __iomem *base; 763 struct phy *phy; 764 int ret; 765 int i; 766 767 am654_phy = devm_kzalloc(dev, sizeof(*am654_phy), GFP_KERNEL); 768 if (!am654_phy) 769 return -ENOMEM; 770 771 base = devm_platform_ioremap_resource(pdev, 0); 772 if (IS_ERR(base)) 773 return PTR_ERR(base); 774 775 regmap = devm_regmap_init_mmio(dev, base, &serdes_am654_regmap_config); 776 if (IS_ERR(regmap)) { 777 dev_err(dev, "Failed to initialize regmap\n"); 778 return PTR_ERR(regmap); 779 } 780 781 control = devm_mux_control_get(dev, NULL); 782 if (IS_ERR(control)) 783 return PTR_ERR(control); 784 785 am654_phy->dev = dev; 786 am654_phy->of_node = node; 787 am654_phy->regmap = regmap; 788 am654_phy->control = control; 789 am654_phy->type = PHY_NONE; 790 791 ret = serdes_am654_regfield_init(am654_phy); 792 if (ret) { 793 dev_err(dev, "Failed to initialize regfields\n"); 794 return ret; 795 } 796 797 platform_set_drvdata(pdev, am654_phy); 798 799 for (i = 0; i < SERDES_NUM_CLOCKS; i++) { 800 ret = of_property_read_string_index(node, "clock-output-names", 801 i, &clock_name); 802 if (ret) { 803 dev_err(dev, "Failed to get clock name\n"); 804 return ret; 805 } 806 807 ret = serdes_am654_clk_register(am654_phy, clock_name, i); 808 if (ret) { 809 dev_err(dev, "Failed to initialize clock %s\n", 810 clock_name); 811 return ret; 812 } 813 } 814 815 clk_data = &am654_phy->clk_data; 816 clk_data->clks = am654_phy->clks; 817 clk_data->clk_num = SERDES_NUM_CLOCKS; 818 ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 819 if (ret) 820 return ret; 821 822 pm_runtime_enable(dev); 823 824 phy = devm_phy_create(dev, NULL, &ops); 825 if (IS_ERR(phy)) { 826 ret = PTR_ERR(phy); 827 goto clk_err; 828 } 829 830 phy_set_drvdata(phy, am654_phy); 831 phy_provider = devm_of_phy_provider_register(dev, serdes_am654_xlate); 832 if (IS_ERR(phy_provider)) { 833 ret = PTR_ERR(phy_provider); 834 goto clk_err; 835 } 836 837 return 0; 838 839 clk_err: 840 of_clk_del_provider(node); 841 pm_runtime_disable(dev); 842 return ret; 843 } 844 845 static void serdes_am654_remove(struct platform_device *pdev) 846 { 847 struct serdes_am654 *am654_phy = platform_get_drvdata(pdev); 848 struct device_node *node = am654_phy->of_node; 849 850 pm_runtime_disable(&pdev->dev); 851 of_clk_del_provider(node); 852 } 853 854 static struct platform_driver serdes_am654_driver = { 855 .probe = serdes_am654_probe, 856 .remove_new = serdes_am654_remove, 857 .driver = { 858 .name = "phy-am654", 859 .of_match_table = serdes_am654_id_table, 860 }, 861 }; 862 module_platform_driver(serdes_am654_driver); 863 864 MODULE_AUTHOR("Texas Instruments Inc."); 865 MODULE_DESCRIPTION("TI AM654x SERDES driver"); 866 MODULE_LICENSE("GPL v2"); 867