1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/phy/phy.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/platform_device.h> 13 #include <linux/clk.h> 14 #include <linux/slab.h> 15 16 #include <soc/tegra/fuse.h> 17 18 #include "xusb.h" 19 20 /* FUSE USB_CALIB registers */ 21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0) 22 #define HS_CURR_LEVEL_PAD_MASK 0x3f 23 #define HS_TERM_RANGE_ADJ_SHIFT 7 24 #define HS_TERM_RANGE_ADJ_MASK 0xf 25 #define HS_SQUELCH_SHIFT 29 26 #define HS_SQUELCH_MASK 0x7 27 28 #define RPD_CTRL_SHIFT 0 29 #define RPD_CTRL_MASK 0x1f 30 31 /* XUSB PADCTL registers */ 32 #define XUSB_PADCTL_USB2_PAD_MUX 0x4 33 #define USB2_PORT_SHIFT(x) ((x) * 2) 34 #define USB2_PORT_MASK 0x3 35 #define PORT_XUSB 1 36 #define HSIC_PORT_SHIFT(x) ((x) + 20) 37 #define HSIC_PORT_MASK 0x1 38 #define PORT_HSIC 0 39 40 #define XUSB_PADCTL_USB2_PORT_CAP 0x8 41 #define XUSB_PADCTL_SS_PORT_CAP 0xc 42 #define PORTX_CAP_SHIFT(x) ((x) * 4) 43 #define PORT_CAP_MASK 0x3 44 #define PORT_CAP_DISABLED 0x0 45 #define PORT_CAP_HOST 0x1 46 #define PORT_CAP_DEVICE 0x2 47 #define PORT_CAP_OTG 0x3 48 49 #define XUSB_PADCTL_ELPG_PROGRAM 0x20 50 #define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x) 51 #define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7) 52 #define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14) 53 #define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21) 54 #define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28) 55 #define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30) 56 #define ALL_WAKE_EVENTS \ 57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \ 58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \ 59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \ 60 USB2_HSIC_PORT_WAKEUP_EVENT(0)) 61 62 #define XUSB_PADCTL_ELPG_PROGRAM_1 0x24 63 #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3) 64 #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3) 65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3) 66 67 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40) 68 #define HS_CURR_LEVEL(x) ((x) & 0x3f) 69 #define TERM_SEL BIT(25) 70 #define USB2_OTG_PD BIT(26) 71 #define USB2_OTG_PD2 BIT(27) 72 #define USB2_OTG_PD2_OVRD_EN BIT(28) 73 #define USB2_OTG_PD_ZI BIT(29) 74 75 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40) 76 #define USB2_OTG_PD_DR BIT(2) 77 #define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3) 78 #define RPD_CTRL(x) (((x) & 0x1f) << 26) 79 80 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284 81 #define BIAS_PAD_PD BIT(11) 82 #define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0) 83 84 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288 85 #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12) 86 #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19) 87 #define USB2_PD_TRK BIT(26) 88 89 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) 90 #define HSIC_PD_TX_DATA0 BIT(1) 91 #define HSIC_PD_TX_STROBE BIT(3) 92 #define HSIC_PD_RX_DATA0 BIT(4) 93 #define HSIC_PD_RX_STROBE BIT(6) 94 #define HSIC_PD_ZI_DATA0 BIT(7) 95 #define HSIC_PD_ZI_STROBE BIT(9) 96 #define HSIC_RPD_DATA0 BIT(13) 97 #define HSIC_RPD_STROBE BIT(15) 98 #define HSIC_RPU_DATA0 BIT(16) 99 #define HSIC_RPU_STROBE BIT(18) 100 101 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340 102 #define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5) 103 #define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12) 104 #define HSIC_PD_TRK BIT(19) 105 106 #define USB2_VBUS_ID 0x360 107 #define VBUS_OVERRIDE BIT(14) 108 #define ID_OVERRIDE(x) (((x) & 0xf) << 18) 109 #define ID_OVERRIDE_FLOATING ID_OVERRIDE(8) 110 #define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0) 111 112 #define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \ 113 { \ 114 .name = _name, \ 115 .offset = _offset, \ 116 .shift = _shift, \ 117 .mask = _mask, \ 118 .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \ 119 .funcs = tegra186_##_type##_functions, \ 120 } 121 122 struct tegra_xusb_fuse_calibration { 123 u32 *hs_curr_level; 124 u32 hs_squelch; 125 u32 hs_term_range_adj; 126 u32 rpd_ctrl; 127 }; 128 129 struct tegra186_xusb_padctl { 130 struct tegra_xusb_padctl base; 131 132 struct tegra_xusb_fuse_calibration calib; 133 134 /* UTMI bias and tracking */ 135 struct clk *usb2_trk_clk; 136 unsigned int bias_pad_enable; 137 }; 138 139 static inline struct tegra186_xusb_padctl * 140 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl) 141 { 142 return container_of(padctl, struct tegra186_xusb_padctl, base); 143 } 144 145 /* USB 2.0 UTMI PHY support */ 146 static struct tegra_xusb_lane * 147 tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 148 unsigned int index) 149 { 150 struct tegra_xusb_usb2_lane *usb2; 151 int err; 152 153 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); 154 if (!usb2) 155 return ERR_PTR(-ENOMEM); 156 157 INIT_LIST_HEAD(&usb2->base.list); 158 usb2->base.soc = &pad->soc->lanes[index]; 159 usb2->base.index = index; 160 usb2->base.pad = pad; 161 usb2->base.np = np; 162 163 err = tegra_xusb_lane_parse_dt(&usb2->base, np); 164 if (err < 0) { 165 kfree(usb2); 166 return ERR_PTR(err); 167 } 168 169 return &usb2->base; 170 } 171 172 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) 173 { 174 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); 175 176 kfree(usb2); 177 } 178 179 static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = { 180 .probe = tegra186_usb2_lane_probe, 181 .remove = tegra186_usb2_lane_remove, 182 }; 183 184 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) 185 { 186 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 187 struct device *dev = padctl->dev; 188 u32 value; 189 int err; 190 191 mutex_lock(&padctl->lock); 192 193 if (priv->bias_pad_enable++ > 0) { 194 mutex_unlock(&padctl->lock); 195 return; 196 } 197 198 err = clk_prepare_enable(priv->usb2_trk_clk); 199 if (err < 0) 200 dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err); 201 202 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 203 value &= ~USB2_TRK_START_TIMER(~0); 204 value |= USB2_TRK_START_TIMER(0x1e); 205 value &= ~USB2_TRK_DONE_RESET_TIMER(~0); 206 value |= USB2_TRK_DONE_RESET_TIMER(0xa); 207 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 208 209 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 210 value &= ~BIAS_PAD_PD; 211 value &= ~HS_SQUELCH_LEVEL(~0); 212 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch); 213 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 214 215 udelay(1); 216 217 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 218 value &= ~USB2_PD_TRK; 219 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 220 221 mutex_unlock(&padctl->lock); 222 } 223 224 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) 225 { 226 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 227 u32 value; 228 229 mutex_lock(&padctl->lock); 230 231 if (WARN_ON(priv->bias_pad_enable == 0)) { 232 mutex_unlock(&padctl->lock); 233 return; 234 } 235 236 if (--priv->bias_pad_enable > 0) { 237 mutex_unlock(&padctl->lock); 238 return; 239 } 240 241 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 242 value |= USB2_PD_TRK; 243 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 244 245 clk_disable_unprepare(priv->usb2_trk_clk); 246 247 mutex_unlock(&padctl->lock); 248 } 249 250 static void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy) 251 { 252 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 253 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 254 struct tegra_xusb_usb2_port *port; 255 struct device *dev = padctl->dev; 256 unsigned int index = lane->index; 257 u32 value; 258 259 if (!phy) 260 return; 261 262 port = tegra_xusb_find_usb2_port(padctl, index); 263 if (!port) { 264 dev_err(dev, "no port found for USB2 lane %u\n", index); 265 return; 266 } 267 268 tegra186_utmi_bias_pad_power_on(padctl); 269 270 udelay(2); 271 272 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 273 value &= ~USB2_OTG_PD; 274 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 275 276 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 277 value &= ~USB2_OTG_PD_DR; 278 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 279 } 280 281 static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy) 282 { 283 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 284 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 285 unsigned int index = lane->index; 286 u32 value; 287 288 if (!phy) 289 return; 290 291 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 292 value |= USB2_OTG_PD; 293 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 294 295 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 296 value |= USB2_OTG_PD_DR; 297 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 298 299 udelay(2); 300 301 tegra186_utmi_bias_pad_power_off(padctl); 302 } 303 304 static int tegra186_utmi_phy_power_on(struct phy *phy) 305 { 306 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 307 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); 308 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 309 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 310 struct tegra_xusb_usb2_port *port; 311 unsigned int index = lane->index; 312 struct device *dev = padctl->dev; 313 u32 value; 314 315 port = tegra_xusb_find_usb2_port(padctl, index); 316 if (!port) { 317 dev_err(dev, "no port found for USB2 lane %u\n", index); 318 return -ENODEV; 319 } 320 321 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); 322 value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index)); 323 value |= (PORT_XUSB << USB2_PORT_SHIFT(index)); 324 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); 325 326 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); 327 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index)); 328 329 if (port->mode == USB_DR_MODE_UNKNOWN) 330 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index)); 331 else if (port->mode == USB_DR_MODE_PERIPHERAL) 332 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index)); 333 else if (port->mode == USB_DR_MODE_HOST) 334 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index)); 335 else if (port->mode == USB_DR_MODE_OTG) 336 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index)); 337 338 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); 339 340 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 341 value &= ~USB2_OTG_PD_ZI; 342 value |= TERM_SEL; 343 value &= ~HS_CURR_LEVEL(~0); 344 345 if (usb2->hs_curr_level_offset) { 346 int hs_current_level; 347 348 hs_current_level = (int)priv->calib.hs_curr_level[index] + 349 usb2->hs_curr_level_offset; 350 351 if (hs_current_level < 0) 352 hs_current_level = 0; 353 if (hs_current_level > 0x3f) 354 hs_current_level = 0x3f; 355 356 value |= HS_CURR_LEVEL(hs_current_level); 357 } else { 358 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]); 359 } 360 361 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 362 363 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 364 value &= ~TERM_RANGE_ADJ(~0); 365 value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj); 366 value &= ~RPD_CTRL(~0); 367 value |= RPD_CTRL(priv->calib.rpd_ctrl); 368 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 369 370 /* TODO: pad power saving */ 371 tegra_phy_xusb_utmi_pad_power_on(phy); 372 return 0; 373 } 374 375 static int tegra186_utmi_phy_power_off(struct phy *phy) 376 { 377 /* TODO: pad power saving */ 378 tegra_phy_xusb_utmi_pad_power_down(phy); 379 380 return 0; 381 } 382 383 static int tegra186_utmi_phy_init(struct phy *phy) 384 { 385 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 386 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 387 struct tegra_xusb_usb2_port *port; 388 unsigned int index = lane->index; 389 struct device *dev = padctl->dev; 390 int err; 391 392 port = tegra_xusb_find_usb2_port(padctl, index); 393 if (!port) { 394 dev_err(dev, "no port found for USB2 lane %u\n", index); 395 return -ENODEV; 396 } 397 398 if (port->supply && port->mode == USB_DR_MODE_HOST) { 399 err = regulator_enable(port->supply); 400 if (err) { 401 dev_err(dev, "failed to enable port %u VBUS: %d\n", 402 index, err); 403 return err; 404 } 405 } 406 407 return 0; 408 } 409 410 static int tegra186_utmi_phy_exit(struct phy *phy) 411 { 412 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 413 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 414 struct tegra_xusb_usb2_port *port; 415 unsigned int index = lane->index; 416 struct device *dev = padctl->dev; 417 int err; 418 419 port = tegra_xusb_find_usb2_port(padctl, index); 420 if (!port) { 421 dev_err(dev, "no port found for USB2 lane %u\n", index); 422 return -ENODEV; 423 } 424 425 if (port->supply && port->mode == USB_DR_MODE_HOST) { 426 err = regulator_disable(port->supply); 427 if (err) { 428 dev_err(dev, "failed to disable port %u VBUS: %d\n", 429 index, err); 430 return err; 431 } 432 } 433 434 return 0; 435 } 436 437 static const struct phy_ops utmi_phy_ops = { 438 .init = tegra186_utmi_phy_init, 439 .exit = tegra186_utmi_phy_exit, 440 .power_on = tegra186_utmi_phy_power_on, 441 .power_off = tegra186_utmi_phy_power_off, 442 .owner = THIS_MODULE, 443 }; 444 445 static struct tegra_xusb_pad * 446 tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl, 447 const struct tegra_xusb_pad_soc *soc, 448 struct device_node *np) 449 { 450 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 451 struct tegra_xusb_usb2_pad *usb2; 452 struct tegra_xusb_pad *pad; 453 int err; 454 455 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); 456 if (!usb2) 457 return ERR_PTR(-ENOMEM); 458 459 pad = &usb2->base; 460 pad->ops = &tegra186_usb2_lane_ops; 461 pad->soc = soc; 462 463 err = tegra_xusb_pad_init(pad, padctl, np); 464 if (err < 0) { 465 kfree(usb2); 466 goto out; 467 } 468 469 priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk"); 470 if (IS_ERR(priv->usb2_trk_clk)) { 471 err = PTR_ERR(priv->usb2_trk_clk); 472 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err); 473 goto unregister; 474 } 475 476 err = tegra_xusb_pad_register(pad, &utmi_phy_ops); 477 if (err < 0) 478 goto unregister; 479 480 dev_set_drvdata(&pad->dev, pad); 481 482 return pad; 483 484 unregister: 485 device_unregister(&pad->dev); 486 out: 487 return ERR_PTR(err); 488 } 489 490 static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad) 491 { 492 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad); 493 494 kfree(usb2); 495 } 496 497 static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = { 498 .probe = tegra186_usb2_pad_probe, 499 .remove = tegra186_usb2_pad_remove, 500 }; 501 502 static const char * const tegra186_usb2_functions[] = { 503 "xusb", 504 }; 505 506 static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { 507 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2), 508 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2), 509 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2), 510 }; 511 512 static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { 513 .name = "usb2", 514 .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes), 515 .lanes = tegra186_usb2_lanes, 516 .ops = &tegra186_usb2_pad_ops, 517 }; 518 519 static int tegra186_usb2_port_enable(struct tegra_xusb_port *port) 520 { 521 return 0; 522 } 523 524 static void tegra186_usb2_port_disable(struct tegra_xusb_port *port) 525 { 526 } 527 528 static struct tegra_xusb_lane * 529 tegra186_usb2_port_map(struct tegra_xusb_port *port) 530 { 531 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); 532 } 533 534 static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = { 535 .enable = tegra186_usb2_port_enable, 536 .disable = tegra186_usb2_port_disable, 537 .map = tegra186_usb2_port_map, 538 }; 539 540 /* SuperSpeed PHY support */ 541 static struct tegra_xusb_lane * 542 tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 543 unsigned int index) 544 { 545 struct tegra_xusb_usb3_lane *usb3; 546 int err; 547 548 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL); 549 if (!usb3) 550 return ERR_PTR(-ENOMEM); 551 552 INIT_LIST_HEAD(&usb3->base.list); 553 usb3->base.soc = &pad->soc->lanes[index]; 554 usb3->base.index = index; 555 usb3->base.pad = pad; 556 usb3->base.np = np; 557 558 err = tegra_xusb_lane_parse_dt(&usb3->base, np); 559 if (err < 0) { 560 kfree(usb3); 561 return ERR_PTR(err); 562 } 563 564 return &usb3->base; 565 } 566 567 static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane) 568 { 569 struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane); 570 571 kfree(usb3); 572 } 573 574 static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = { 575 .probe = tegra186_usb3_lane_probe, 576 .remove = tegra186_usb3_lane_remove, 577 }; 578 static int tegra186_usb3_port_enable(struct tegra_xusb_port *port) 579 { 580 return 0; 581 } 582 583 static void tegra186_usb3_port_disable(struct tegra_xusb_port *port) 584 { 585 } 586 587 static struct tegra_xusb_lane * 588 tegra186_usb3_port_map(struct tegra_xusb_port *port) 589 { 590 return tegra_xusb_find_lane(port->padctl, "usb3", port->index); 591 } 592 593 static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = { 594 .enable = tegra186_usb3_port_enable, 595 .disable = tegra186_usb3_port_disable, 596 .map = tegra186_usb3_port_map, 597 }; 598 599 static int tegra186_usb3_phy_power_on(struct phy *phy) 600 { 601 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 602 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 603 struct tegra_xusb_usb3_port *port; 604 struct tegra_xusb_usb2_port *usb2; 605 unsigned int index = lane->index; 606 struct device *dev = padctl->dev; 607 u32 value; 608 609 port = tegra_xusb_find_usb3_port(padctl, index); 610 if (!port) { 611 dev_err(dev, "no port found for USB3 lane %u\n", index); 612 return -ENODEV; 613 } 614 615 usb2 = tegra_xusb_find_usb2_port(padctl, port->port); 616 if (!usb2) { 617 dev_err(dev, "no companion port found for USB3 lane %u\n", 618 index); 619 return -ENODEV; 620 } 621 622 mutex_lock(&padctl->lock); 623 624 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP); 625 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index)); 626 627 if (usb2->mode == USB_DR_MODE_UNKNOWN) 628 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index)); 629 else if (usb2->mode == USB_DR_MODE_PERIPHERAL) 630 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index)); 631 else if (usb2->mode == USB_DR_MODE_HOST) 632 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index)); 633 else if (usb2->mode == USB_DR_MODE_OTG) 634 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index)); 635 636 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP); 637 638 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 639 value &= ~SSPX_ELPG_VCORE_DOWN(index); 640 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 641 642 usleep_range(100, 200); 643 644 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 645 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index); 646 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 647 648 usleep_range(100, 200); 649 650 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 651 value &= ~SSPX_ELPG_CLAMP_EN(index); 652 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 653 654 mutex_unlock(&padctl->lock); 655 656 return 0; 657 } 658 659 static int tegra186_usb3_phy_power_off(struct phy *phy) 660 { 661 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 662 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 663 struct tegra_xusb_usb3_port *port; 664 unsigned int index = lane->index; 665 struct device *dev = padctl->dev; 666 u32 value; 667 668 port = tegra_xusb_find_usb3_port(padctl, index); 669 if (!port) { 670 dev_err(dev, "no port found for USB3 lane %u\n", index); 671 return -ENODEV; 672 } 673 674 mutex_lock(&padctl->lock); 675 676 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 677 value |= SSPX_ELPG_CLAMP_EN_EARLY(index); 678 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 679 680 usleep_range(100, 200); 681 682 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 683 value |= SSPX_ELPG_CLAMP_EN(index); 684 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 685 686 usleep_range(250, 350); 687 688 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 689 value |= SSPX_ELPG_VCORE_DOWN(index); 690 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 691 692 mutex_unlock(&padctl->lock); 693 694 return 0; 695 } 696 697 static int tegra186_usb3_phy_init(struct phy *phy) 698 { 699 return 0; 700 } 701 702 static int tegra186_usb3_phy_exit(struct phy *phy) 703 { 704 return 0; 705 } 706 707 static const struct phy_ops usb3_phy_ops = { 708 .init = tegra186_usb3_phy_init, 709 .exit = tegra186_usb3_phy_exit, 710 .power_on = tegra186_usb3_phy_power_on, 711 .power_off = tegra186_usb3_phy_power_off, 712 .owner = THIS_MODULE, 713 }; 714 715 static struct tegra_xusb_pad * 716 tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl, 717 const struct tegra_xusb_pad_soc *soc, 718 struct device_node *np) 719 { 720 struct tegra_xusb_usb3_pad *usb3; 721 struct tegra_xusb_pad *pad; 722 int err; 723 724 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL); 725 if (!usb3) 726 return ERR_PTR(-ENOMEM); 727 728 pad = &usb3->base; 729 pad->ops = &tegra186_usb3_lane_ops; 730 pad->soc = soc; 731 732 err = tegra_xusb_pad_init(pad, padctl, np); 733 if (err < 0) { 734 kfree(usb3); 735 goto out; 736 } 737 738 err = tegra_xusb_pad_register(pad, &usb3_phy_ops); 739 if (err < 0) 740 goto unregister; 741 742 dev_set_drvdata(&pad->dev, pad); 743 744 return pad; 745 746 unregister: 747 device_unregister(&pad->dev); 748 out: 749 return ERR_PTR(err); 750 } 751 752 static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad) 753 { 754 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad); 755 756 kfree(usb2); 757 } 758 759 static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = { 760 .probe = tegra186_usb3_pad_probe, 761 .remove = tegra186_usb3_pad_remove, 762 }; 763 764 static const char * const tegra186_usb3_functions[] = { 765 "xusb", 766 }; 767 768 static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { 769 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3), 770 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3), 771 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3), 772 }; 773 774 static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { 775 .name = "usb3", 776 .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes), 777 .lanes = tegra186_usb3_lanes, 778 .ops = &tegra186_usb3_pad_ops, 779 }; 780 781 static const struct tegra_xusb_pad_soc * const tegra186_pads[] = { 782 &tegra186_usb2_pad, 783 &tegra186_usb3_pad, 784 #if 0 /* TODO implement */ 785 &tegra186_hsic_pad, 786 #endif 787 }; 788 789 static int 790 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl) 791 { 792 struct device *dev = padctl->base.dev; 793 unsigned int i, count; 794 u32 value, *level; 795 int err; 796 797 count = padctl->base.soc->ports.usb2.count; 798 799 level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL); 800 if (!level) 801 return -ENOMEM; 802 803 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value); 804 if (err) { 805 dev_err(dev, "failed to read calibration fuse: %d\n", err); 806 return err; 807 } 808 809 dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value); 810 811 for (i = 0; i < count; i++) 812 level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) & 813 HS_CURR_LEVEL_PAD_MASK; 814 815 padctl->calib.hs_curr_level = level; 816 817 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) & 818 HS_SQUELCH_MASK; 819 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) & 820 HS_TERM_RANGE_ADJ_MASK; 821 822 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value); 823 if (err) { 824 dev_err(dev, "failed to read calibration fuse: %d\n", err); 825 return err; 826 } 827 828 dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value); 829 830 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK; 831 832 return 0; 833 } 834 835 static struct tegra_xusb_padctl * 836 tegra186_xusb_padctl_probe(struct device *dev, 837 const struct tegra_xusb_padctl_soc *soc) 838 { 839 struct tegra186_xusb_padctl *priv; 840 int err; 841 842 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 843 if (!priv) 844 return ERR_PTR(-ENOMEM); 845 846 priv->base.dev = dev; 847 priv->base.soc = soc; 848 849 err = tegra186_xusb_read_fuse_calibration(priv); 850 if (err < 0) 851 return ERR_PTR(err); 852 853 return &priv->base; 854 } 855 856 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl) 857 { 858 } 859 860 static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = { 861 .probe = tegra186_xusb_padctl_probe, 862 .remove = tegra186_xusb_padctl_remove, 863 }; 864 865 static const char * const tegra186_xusb_padctl_supply_names[] = { 866 "avdd-pll-erefeut", 867 "avdd-usb", 868 "vclamp-usb", 869 "vddio-hsic", 870 }; 871 872 const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { 873 .num_pads = ARRAY_SIZE(tegra186_pads), 874 .pads = tegra186_pads, 875 .ports = { 876 .usb2 = { 877 .ops = &tegra186_usb2_port_ops, 878 .count = 3, 879 }, 880 #if 0 /* TODO implement */ 881 .hsic = { 882 .ops = &tegra186_hsic_port_ops, 883 .count = 1, 884 }, 885 #endif 886 .usb3 = { 887 .ops = &tegra186_usb3_port_ops, 888 .count = 3, 889 }, 890 }, 891 .ops = &tegra186_xusb_padctl_ops, 892 .supply_names = tegra186_xusb_padctl_supply_names, 893 .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names), 894 }; 895 EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); 896 897 MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>"); 898 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver"); 899 MODULE_LICENSE("GPL v2"); 900