1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/phy/phy.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/platform_device.h> 13 #include <linux/clk.h> 14 #include <linux/slab.h> 15 16 #include <soc/tegra/fuse.h> 17 18 #include "xusb.h" 19 20 /* FUSE USB_CALIB registers */ 21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0) 22 #define HS_CURR_LEVEL_PAD_MASK 0x3f 23 #define HS_TERM_RANGE_ADJ_SHIFT 7 24 #define HS_TERM_RANGE_ADJ_MASK 0xf 25 #define HS_SQUELCH_SHIFT 29 26 #define HS_SQUELCH_MASK 0x7 27 28 #define RPD_CTRL_SHIFT 0 29 #define RPD_CTRL_MASK 0x1f 30 31 /* XUSB PADCTL registers */ 32 #define XUSB_PADCTL_USB2_PAD_MUX 0x4 33 #define USB2_PORT_SHIFT(x) ((x) * 2) 34 #define USB2_PORT_MASK 0x3 35 #define PORT_XUSB 1 36 #define HSIC_PORT_SHIFT(x) ((x) + 20) 37 #define HSIC_PORT_MASK 0x1 38 #define PORT_HSIC 0 39 40 #define XUSB_PADCTL_USB2_PORT_CAP 0x8 41 #define XUSB_PADCTL_SS_PORT_CAP 0xc 42 #define PORTX_CAP_SHIFT(x) ((x) * 4) 43 #define PORT_CAP_MASK 0x3 44 #define PORT_CAP_DISABLED 0x0 45 #define PORT_CAP_HOST 0x1 46 #define PORT_CAP_DEVICE 0x2 47 #define PORT_CAP_OTG 0x3 48 49 #define XUSB_PADCTL_ELPG_PROGRAM 0x20 50 #define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x) 51 #define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7) 52 #define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14) 53 #define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21) 54 #define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28) 55 #define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30) 56 #define ALL_WAKE_EVENTS \ 57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \ 58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \ 59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \ 60 USB2_HSIC_PORT_WAKEUP_EVENT(0)) 61 62 #define XUSB_PADCTL_ELPG_PROGRAM_1 0x24 63 #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3) 64 #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3) 65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3) 66 #define XUSB_PADCTL_SS_PORT_CFG 0x2c 67 #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4) 68 #define PORTX_SPEED_SUPPORT_MASK (0x3) 69 #define PORT_SPEED_SUPPORT_GEN1 (0x0) 70 71 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40) 72 #define HS_CURR_LEVEL(x) ((x) & 0x3f) 73 #define TERM_SEL BIT(25) 74 #define USB2_OTG_PD BIT(26) 75 #define USB2_OTG_PD2 BIT(27) 76 #define USB2_OTG_PD2_OVRD_EN BIT(28) 77 #define USB2_OTG_PD_ZI BIT(29) 78 79 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40) 80 #define USB2_OTG_PD_DR BIT(2) 81 #define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3) 82 #define RPD_CTRL(x) (((x) & 0x1f) << 26) 83 84 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284 85 #define BIAS_PAD_PD BIT(11) 86 #define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0) 87 88 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288 89 #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12) 90 #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19) 91 #define USB2_PD_TRK BIT(26) 92 #define USB2_TRK_COMPLETED BIT(31) 93 94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL2 0x28c 95 #define USB2_TRK_HW_MODE BIT(0) 96 #define CYA_TRK_CODE_UPDATE_ON_IDLE BIT(31) 97 98 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) 99 #define HSIC_PD_TX_DATA0 BIT(1) 100 #define HSIC_PD_TX_STROBE BIT(3) 101 #define HSIC_PD_RX_DATA0 BIT(4) 102 #define HSIC_PD_RX_STROBE BIT(6) 103 #define HSIC_PD_ZI_DATA0 BIT(7) 104 #define HSIC_PD_ZI_STROBE BIT(9) 105 #define HSIC_RPD_DATA0 BIT(13) 106 #define HSIC_RPD_STROBE BIT(15) 107 #define HSIC_RPU_DATA0 BIT(16) 108 #define HSIC_RPU_STROBE BIT(18) 109 110 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340 111 #define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5) 112 #define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12) 113 #define HSIC_PD_TRK BIT(19) 114 115 #define USB2_VBUS_ID 0x360 116 #define VBUS_OVERRIDE BIT(14) 117 #define ID_OVERRIDE(x) (((x) & 0xf) << 18) 118 #define ID_OVERRIDE_FLOATING ID_OVERRIDE(8) 119 #define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0) 120 121 /* XUSB AO registers */ 122 #define XUSB_AO_USB_DEBOUNCE_DEL (0x4) 123 #define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4) 124 #define UTMIP_LINE_DEB_CNT(x) ((x) & 0xf) 125 126 #define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4) 127 #define CLR_WALK_PTR BIT(0) 128 #define CAP_CFG BIT(1) 129 #define CLR_WAKE_ALARM BIT(3) 130 131 #define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4) 132 #define HSIC_CLR_WALK_PTR BIT(0) 133 #define HSIC_CLR_WAKE_ALARM BIT(3) 134 #define HSIC_CAP_CFG BIT(4) 135 136 #define XUSB_AO_UTMIP_SAVED_STATE(x) (0x70 + (x) * 4) 137 #define SPEED(x) ((x) & 0x3) 138 #define UTMI_HS SPEED(0) 139 #define UTMI_FS SPEED(1) 140 #define UTMI_LS SPEED(2) 141 #define UTMI_RST SPEED(3) 142 143 #define XUSB_AO_UHSIC_SAVED_STATE(x) (0x90 + (x) * 4) 144 #define MODE(x) ((x) & 0x1) 145 #define MODE_HS MODE(0) 146 #define MODE_RST MODE(1) 147 148 #define XUSB_AO_UTMIP_SLEEPWALK_STATUS(x) (0xa0 + (x) * 4) 149 150 #define XUSB_AO_UTMIP_SLEEPWALK_CFG(x) (0xd0 + (x) * 4) 151 #define XUSB_AO_UHSIC_SLEEPWALK_CFG(x) (0xf0 + (x) * 4) 152 #define FAKE_USBOP_VAL BIT(0) 153 #define FAKE_USBON_VAL BIT(1) 154 #define FAKE_USBOP_EN BIT(2) 155 #define FAKE_USBON_EN BIT(3) 156 #define FAKE_STROBE_VAL BIT(0) 157 #define FAKE_DATA_VAL BIT(1) 158 #define FAKE_STROBE_EN BIT(2) 159 #define FAKE_DATA_EN BIT(3) 160 #define WAKE_WALK_EN BIT(14) 161 #define MASTER_ENABLE BIT(15) 162 #define LINEVAL_WALK_EN BIT(16) 163 #define WAKE_VAL(x) (((x) & 0xf) << 17) 164 #define WAKE_VAL_NONE WAKE_VAL(12) 165 #define WAKE_VAL_ANY WAKE_VAL(15) 166 #define WAKE_VAL_DS10 WAKE_VAL(2) 167 #define LINE_WAKEUP_EN BIT(21) 168 #define MASTER_CFG_SEL BIT(22) 169 170 #define XUSB_AO_UTMIP_SLEEPWALK(x) (0x100 + (x) * 4) 171 /* phase A */ 172 #define USBOP_RPD_A BIT(0) 173 #define USBON_RPD_A BIT(1) 174 #define AP_A BIT(4) 175 #define AN_A BIT(5) 176 #define HIGHZ_A BIT(6) 177 #define MASTER_ENABLE_A BIT(7) 178 /* phase B */ 179 #define USBOP_RPD_B BIT(8) 180 #define USBON_RPD_B BIT(9) 181 #define AP_B BIT(12) 182 #define AN_B BIT(13) 183 #define HIGHZ_B BIT(14) 184 #define MASTER_ENABLE_B BIT(15) 185 /* phase C */ 186 #define USBOP_RPD_C BIT(16) 187 #define USBON_RPD_C BIT(17) 188 #define AP_C BIT(20) 189 #define AN_C BIT(21) 190 #define HIGHZ_C BIT(22) 191 #define MASTER_ENABLE_C BIT(23) 192 /* phase D */ 193 #define USBOP_RPD_D BIT(24) 194 #define USBON_RPD_D BIT(25) 195 #define AP_D BIT(28) 196 #define AN_D BIT(29) 197 #define HIGHZ_D BIT(30) 198 #define MASTER_ENABLE_D BIT(31) 199 #define MASTER_ENABLE_B_C_D \ 200 (MASTER_ENABLE_B | MASTER_ENABLE_C | MASTER_ENABLE_D) 201 202 #define XUSB_AO_UHSIC_SLEEPWALK(x) (0x120 + (x) * 4) 203 /* phase A */ 204 #define RPD_STROBE_A BIT(0) 205 #define RPD_DATA0_A BIT(1) 206 #define RPU_STROBE_A BIT(2) 207 #define RPU_DATA0_A BIT(3) 208 /* phase B */ 209 #define RPD_STROBE_B BIT(8) 210 #define RPD_DATA0_B BIT(9) 211 #define RPU_STROBE_B BIT(10) 212 #define RPU_DATA0_B BIT(11) 213 /* phase C */ 214 #define RPD_STROBE_C BIT(16) 215 #define RPD_DATA0_C BIT(17) 216 #define RPU_STROBE_C BIT(18) 217 #define RPU_DATA0_C BIT(19) 218 /* phase D */ 219 #define RPD_STROBE_D BIT(24) 220 #define RPD_DATA0_D BIT(25) 221 #define RPU_STROBE_D BIT(26) 222 #define RPU_DATA0_D BIT(27) 223 224 #define XUSB_AO_UTMIP_PAD_CFG(x) (0x130 + (x) * 4) 225 #define FSLS_USE_XUSB_AO BIT(3) 226 #define TRK_CTRL_USE_XUSB_AO BIT(4) 227 #define RPD_CTRL_USE_XUSB_AO BIT(5) 228 #define RPU_USE_XUSB_AO BIT(6) 229 #define VREG_USE_XUSB_AO BIT(7) 230 #define USBOP_VAL_PD BIT(8) 231 #define USBON_VAL_PD BIT(9) 232 #define E_DPD_OVRD_EN BIT(10) 233 #define E_DPD_OVRD_VAL BIT(11) 234 235 #define XUSB_AO_UHSIC_PAD_CFG(x) (0x150 + (x) * 4) 236 #define STROBE_VAL_PD BIT(0) 237 #define DATA0_VAL_PD BIT(1) 238 #define USE_XUSB_AO BIT(4) 239 240 #define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \ 241 { \ 242 .name = _name, \ 243 .offset = _offset, \ 244 .shift = _shift, \ 245 .mask = _mask, \ 246 .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \ 247 .funcs = tegra186_##_type##_functions, \ 248 } 249 250 struct tegra_xusb_fuse_calibration { 251 u32 *hs_curr_level; 252 u32 hs_squelch; 253 u32 hs_term_range_adj; 254 u32 rpd_ctrl; 255 }; 256 257 struct tegra186_xusb_padctl_context { 258 u32 vbus_id; 259 u32 usb2_pad_mux; 260 u32 usb2_port_cap; 261 u32 ss_port_cap; 262 }; 263 264 struct tegra186_xusb_padctl { 265 struct tegra_xusb_padctl base; 266 void __iomem *ao_regs; 267 268 struct tegra_xusb_fuse_calibration calib; 269 270 /* UTMI bias and tracking */ 271 struct clk *usb2_trk_clk; 272 unsigned int bias_pad_enable; 273 274 /* padctl context */ 275 struct tegra186_xusb_padctl_context context; 276 }; 277 278 static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset) 279 { 280 writel(value, priv->ao_regs + offset); 281 } 282 283 static inline u32 ao_readl(struct tegra186_xusb_padctl *priv, unsigned int offset) 284 { 285 return readl(priv->ao_regs + offset); 286 } 287 288 static inline struct tegra186_xusb_padctl * 289 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl) 290 { 291 return container_of(padctl, struct tegra186_xusb_padctl, base); 292 } 293 294 /* USB 2.0 UTMI PHY support */ 295 static struct tegra_xusb_lane * 296 tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 297 unsigned int index) 298 { 299 struct tegra_xusb_usb2_lane *usb2; 300 int err; 301 302 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); 303 if (!usb2) 304 return ERR_PTR(-ENOMEM); 305 306 INIT_LIST_HEAD(&usb2->base.list); 307 usb2->base.soc = &pad->soc->lanes[index]; 308 usb2->base.index = index; 309 usb2->base.pad = pad; 310 usb2->base.np = np; 311 312 err = tegra_xusb_lane_parse_dt(&usb2->base, np); 313 if (err < 0) { 314 kfree(usb2); 315 return ERR_PTR(err); 316 } 317 318 return &usb2->base; 319 } 320 321 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) 322 { 323 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); 324 325 kfree(usb2); 326 } 327 328 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, 329 enum usb_device_speed speed) 330 { 331 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 332 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 333 unsigned int index = lane->index; 334 u32 value; 335 336 mutex_lock(&padctl->lock); 337 338 /* ensure sleepwalk logic is disabled */ 339 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 340 value &= ~MASTER_ENABLE; 341 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 342 343 /* ensure sleepwalk logics are in low power mode */ 344 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 345 value |= MASTER_CFG_SEL; 346 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 347 348 /* set debounce time */ 349 value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL); 350 value &= ~UTMIP_LINE_DEB_CNT(~0); 351 value |= UTMIP_LINE_DEB_CNT(1); 352 ao_writel(priv, value, XUSB_AO_USB_DEBOUNCE_DEL); 353 354 /* ensure fake events of sleepwalk logic are desiabled */ 355 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 356 value &= ~(FAKE_USBOP_VAL | FAKE_USBON_VAL | 357 FAKE_USBOP_EN | FAKE_USBON_EN); 358 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 359 360 /* ensure wake events of sleepwalk logic are not latched */ 361 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 362 value &= ~LINE_WAKEUP_EN; 363 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 364 365 /* disable wake event triggers of sleepwalk logic */ 366 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 367 value &= ~WAKE_VAL(~0); 368 value |= WAKE_VAL_NONE; 369 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 370 371 /* power down the line state detectors of the pad */ 372 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); 373 value |= (USBOP_VAL_PD | USBON_VAL_PD); 374 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index)); 375 376 /* save state per speed */ 377 value = ao_readl(priv, XUSB_AO_UTMIP_SAVED_STATE(index)); 378 value &= ~SPEED(~0); 379 380 switch (speed) { 381 case USB_SPEED_HIGH: 382 value |= UTMI_HS; 383 break; 384 385 case USB_SPEED_FULL: 386 value |= UTMI_FS; 387 break; 388 389 case USB_SPEED_LOW: 390 value |= UTMI_LS; 391 break; 392 393 default: 394 value |= UTMI_RST; 395 break; 396 } 397 398 ao_writel(priv, value, XUSB_AO_UTMIP_SAVED_STATE(index)); 399 400 /* enable the trigger of the sleepwalk logic */ 401 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 402 value |= LINEVAL_WALK_EN; 403 value &= ~WAKE_WALK_EN; 404 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 405 406 /* reset the walk pointer and clear the alarm of the sleepwalk logic, 407 * as well as capture the configuration of the USB2.0 pad 408 */ 409 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index)); 410 value |= (CLR_WALK_PTR | CLR_WAKE_ALARM | CAP_CFG); 411 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index)); 412 413 /* setup the pull-ups and pull-downs of the signals during the four 414 * stages of sleepwalk. 415 * if device is connected, program sleepwalk logic to maintain a J and 416 * keep driving K upon seeing remote wake. 417 */ 418 value = USBOP_RPD_A | USBOP_RPD_B | USBOP_RPD_C | USBOP_RPD_D; 419 value |= USBON_RPD_A | USBON_RPD_B | USBON_RPD_C | USBON_RPD_D; 420 421 switch (speed) { 422 case USB_SPEED_HIGH: 423 case USB_SPEED_FULL: 424 /* J state: D+/D- = high/low, K state: D+/D- = low/high */ 425 value |= HIGHZ_A; 426 value |= AP_A; 427 value |= AN_B | AN_C | AN_D; 428 if (padctl->soc->supports_lp_cfg_en) 429 value |= MASTER_ENABLE_B_C_D; 430 break; 431 432 case USB_SPEED_LOW: 433 /* J state: D+/D- = low/high, K state: D+/D- = high/low */ 434 value |= HIGHZ_A; 435 value |= AN_A; 436 value |= AP_B | AP_C | AP_D; 437 if (padctl->soc->supports_lp_cfg_en) 438 value |= MASTER_ENABLE_B_C_D; 439 break; 440 441 default: 442 value |= HIGHZ_A | HIGHZ_B | HIGHZ_C | HIGHZ_D; 443 break; 444 } 445 446 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index)); 447 448 /* power up the line state detectors of the pad */ 449 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); 450 value &= ~(USBOP_VAL_PD | USBON_VAL_PD); 451 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index)); 452 453 usleep_range(150, 200); 454 455 /* switch the electric control of the USB2.0 pad to XUSB_AO */ 456 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); 457 value |= FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO | 458 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO; 459 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index)); 460 461 /* set the wake signaling trigger events */ 462 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 463 value &= ~WAKE_VAL(~0); 464 value |= WAKE_VAL_ANY; 465 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 466 467 /* enable the wake detection */ 468 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 469 value |= MASTER_ENABLE | LINE_WAKEUP_EN; 470 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 471 472 mutex_unlock(&padctl->lock); 473 474 return 0; 475 } 476 477 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane) 478 { 479 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 480 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 481 unsigned int index = lane->index; 482 u32 value; 483 484 mutex_lock(&padctl->lock); 485 486 /* disable the wake detection */ 487 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 488 value &= ~(MASTER_ENABLE | LINE_WAKEUP_EN); 489 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 490 491 /* switch the electric control of the USB2.0 pad to XUSB vcore logic */ 492 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); 493 value &= ~(FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO | 494 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO); 495 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index)); 496 497 /* disable wake event triggers of sleepwalk logic */ 498 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 499 value &= ~WAKE_VAL(~0); 500 value |= WAKE_VAL_NONE; 501 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); 502 503 if (padctl->soc->supports_lp_cfg_en) { 504 /* disable the four stages of sleepwalk */ 505 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK(index)); 506 value &= ~(MASTER_ENABLE_A | MASTER_ENABLE_B_C_D); 507 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index)); 508 } 509 510 /* power down the line state detectors of the port */ 511 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); 512 value |= USBOP_VAL_PD | USBON_VAL_PD; 513 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index)); 514 515 /* clear alarm of the sleepwalk logic */ 516 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index)); 517 value |= CLR_WAKE_ALARM; 518 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index)); 519 520 mutex_unlock(&padctl->lock); 521 522 return 0; 523 } 524 525 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane) 526 { 527 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 528 unsigned int index = lane->index; 529 u32 value; 530 531 mutex_lock(&padctl->lock); 532 533 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 534 value &= ~ALL_WAKE_EVENTS; 535 value |= USB2_PORT_WAKEUP_EVENT(index); 536 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 537 538 usleep_range(10, 20); 539 540 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 541 value &= ~ALL_WAKE_EVENTS; 542 value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index); 543 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 544 545 mutex_unlock(&padctl->lock); 546 547 return 0; 548 } 549 550 static int tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane *lane) 551 { 552 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 553 unsigned int index = lane->index; 554 u32 value; 555 556 mutex_lock(&padctl->lock); 557 558 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 559 value &= ~ALL_WAKE_EVENTS; 560 value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index); 561 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 562 563 usleep_range(10, 20); 564 565 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 566 value &= ~ALL_WAKE_EVENTS; 567 value |= USB2_PORT_WAKEUP_EVENT(index); 568 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 569 570 mutex_unlock(&padctl->lock); 571 572 return 0; 573 } 574 575 static bool tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane *lane) 576 { 577 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 578 unsigned int index = lane->index; 579 u32 value; 580 581 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 582 if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) && 583 (value & USB2_PORT_WAKEUP_EVENT(index))) 584 return true; 585 586 return false; 587 } 588 589 static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = { 590 .probe = tegra186_usb2_lane_probe, 591 .remove = tegra186_usb2_lane_remove, 592 .enable_phy_sleepwalk = tegra186_utmi_enable_phy_sleepwalk, 593 .disable_phy_sleepwalk = tegra186_utmi_disable_phy_sleepwalk, 594 .enable_phy_wake = tegra186_utmi_enable_phy_wake, 595 .disable_phy_wake = tegra186_utmi_disable_phy_wake, 596 .remote_wake_detected = tegra186_utmi_phy_remote_wake_detected, 597 }; 598 599 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) 600 { 601 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 602 struct device *dev = padctl->dev; 603 u32 value; 604 int err; 605 606 mutex_lock(&padctl->lock); 607 608 if (priv->bias_pad_enable++ > 0) { 609 mutex_unlock(&padctl->lock); 610 return; 611 } 612 613 err = clk_prepare_enable(priv->usb2_trk_clk); 614 if (err < 0) 615 dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err); 616 617 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 618 value &= ~USB2_TRK_START_TIMER(~0); 619 value |= USB2_TRK_START_TIMER(0x1e); 620 value &= ~USB2_TRK_DONE_RESET_TIMER(~0); 621 value |= USB2_TRK_DONE_RESET_TIMER(0xa); 622 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 623 624 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 625 value &= ~BIAS_PAD_PD; 626 value &= ~HS_SQUELCH_LEVEL(~0); 627 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch); 628 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 629 630 udelay(1); 631 632 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 633 value &= ~USB2_PD_TRK; 634 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 635 636 if (padctl->soc->poll_trk_completed) { 637 err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, 638 USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 100); 639 if (err) { 640 /* The failure with polling on trk complete will not 641 * cause the failure of powering on the bias pad. 642 */ 643 dev_warn(dev, "failed to poll USB2 trk completed: %d\n", err); 644 } 645 646 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 647 value |= USB2_TRK_COMPLETED; 648 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 649 } else { 650 udelay(100); 651 } 652 653 if (padctl->soc->trk_hw_mode) { 654 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); 655 value |= USB2_TRK_HW_MODE; 656 value &= ~CYA_TRK_CODE_UPDATE_ON_IDLE; 657 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); 658 } else { 659 clk_disable_unprepare(priv->usb2_trk_clk); 660 } 661 662 mutex_unlock(&padctl->lock); 663 } 664 665 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) 666 { 667 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 668 u32 value; 669 670 mutex_lock(&padctl->lock); 671 672 if (WARN_ON(priv->bias_pad_enable == 0)) { 673 mutex_unlock(&padctl->lock); 674 return; 675 } 676 677 if (--priv->bias_pad_enable > 0) { 678 mutex_unlock(&padctl->lock); 679 return; 680 } 681 682 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 683 value |= USB2_PD_TRK; 684 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 685 686 if (padctl->soc->trk_hw_mode) { 687 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); 688 value &= ~USB2_TRK_HW_MODE; 689 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); 690 clk_disable_unprepare(priv->usb2_trk_clk); 691 } 692 693 mutex_unlock(&padctl->lock); 694 } 695 696 static void tegra186_utmi_pad_power_on(struct phy *phy) 697 { 698 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 699 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 700 struct tegra_xusb_usb2_port *port; 701 struct device *dev = padctl->dev; 702 unsigned int index = lane->index; 703 u32 value; 704 705 if (!phy) 706 return; 707 708 port = tegra_xusb_find_usb2_port(padctl, index); 709 if (!port) { 710 dev_err(dev, "no port found for USB2 lane %u\n", index); 711 return; 712 } 713 714 dev_dbg(dev, "power on UTMI pad %u\n", index); 715 716 tegra186_utmi_bias_pad_power_on(padctl); 717 718 udelay(2); 719 720 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 721 value &= ~USB2_OTG_PD; 722 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 723 724 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 725 value &= ~USB2_OTG_PD_DR; 726 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 727 } 728 729 static void tegra186_utmi_pad_power_down(struct phy *phy) 730 { 731 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 732 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 733 unsigned int index = lane->index; 734 u32 value; 735 736 if (!phy) 737 return; 738 739 dev_dbg(padctl->dev, "power down UTMI pad %u\n", index); 740 741 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 742 value |= USB2_OTG_PD; 743 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 744 745 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 746 value |= USB2_OTG_PD_DR; 747 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 748 749 udelay(2); 750 751 tegra186_utmi_bias_pad_power_off(padctl); 752 } 753 754 static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl, 755 bool status) 756 { 757 u32 value; 758 759 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear"); 760 761 value = padctl_readl(padctl, USB2_VBUS_ID); 762 763 if (status) { 764 value |= VBUS_OVERRIDE; 765 value &= ~ID_OVERRIDE(~0); 766 value |= ID_OVERRIDE_FLOATING; 767 } else { 768 value &= ~VBUS_OVERRIDE; 769 } 770 771 padctl_writel(padctl, value, USB2_VBUS_ID); 772 773 return 0; 774 } 775 776 static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl, 777 bool status) 778 { 779 u32 value; 780 781 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear"); 782 783 value = padctl_readl(padctl, USB2_VBUS_ID); 784 785 if (status) { 786 if (value & VBUS_OVERRIDE) { 787 value &= ~VBUS_OVERRIDE; 788 padctl_writel(padctl, value, USB2_VBUS_ID); 789 usleep_range(1000, 2000); 790 791 value = padctl_readl(padctl, USB2_VBUS_ID); 792 } 793 794 value &= ~ID_OVERRIDE(~0); 795 value |= ID_OVERRIDE_GROUNDED; 796 } else { 797 value &= ~ID_OVERRIDE(~0); 798 value |= ID_OVERRIDE_FLOATING; 799 } 800 801 padctl_writel(padctl, value, USB2_VBUS_ID); 802 803 return 0; 804 } 805 806 static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode, 807 int submode) 808 { 809 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 810 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 811 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl, 812 lane->index); 813 int err = 0; 814 815 mutex_lock(&padctl->lock); 816 817 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode); 818 819 if (mode == PHY_MODE_USB_OTG) { 820 if (submode == USB_ROLE_HOST) { 821 tegra186_xusb_padctl_id_override(padctl, true); 822 823 err = regulator_enable(port->supply); 824 } else if (submode == USB_ROLE_DEVICE) { 825 tegra186_xusb_padctl_vbus_override(padctl, true); 826 } else if (submode == USB_ROLE_NONE) { 827 /* 828 * When port is peripheral only or role transitions to 829 * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not 830 * enabled. 831 */ 832 if (regulator_is_enabled(port->supply)) 833 regulator_disable(port->supply); 834 835 tegra186_xusb_padctl_id_override(padctl, false); 836 tegra186_xusb_padctl_vbus_override(padctl, false); 837 } 838 } 839 840 mutex_unlock(&padctl->lock); 841 842 return err; 843 } 844 845 static int tegra186_utmi_phy_power_on(struct phy *phy) 846 { 847 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 848 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); 849 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 850 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 851 struct tegra_xusb_usb2_port *port; 852 unsigned int index = lane->index; 853 struct device *dev = padctl->dev; 854 u32 value; 855 856 port = tegra_xusb_find_usb2_port(padctl, index); 857 if (!port) { 858 dev_err(dev, "no port found for USB2 lane %u\n", index); 859 return -ENODEV; 860 } 861 862 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); 863 value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index)); 864 value |= (PORT_XUSB << USB2_PORT_SHIFT(index)); 865 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); 866 867 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); 868 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index)); 869 870 if (port->mode == USB_DR_MODE_UNKNOWN) 871 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index)); 872 else if (port->mode == USB_DR_MODE_PERIPHERAL) 873 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index)); 874 else if (port->mode == USB_DR_MODE_HOST) 875 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index)); 876 else if (port->mode == USB_DR_MODE_OTG) 877 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index)); 878 879 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); 880 881 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 882 value &= ~USB2_OTG_PD_ZI; 883 value |= TERM_SEL; 884 value &= ~HS_CURR_LEVEL(~0); 885 886 if (usb2->hs_curr_level_offset) { 887 int hs_current_level; 888 889 hs_current_level = (int)priv->calib.hs_curr_level[index] + 890 usb2->hs_curr_level_offset; 891 892 if (hs_current_level < 0) 893 hs_current_level = 0; 894 if (hs_current_level > 0x3f) 895 hs_current_level = 0x3f; 896 897 value |= HS_CURR_LEVEL(hs_current_level); 898 } else { 899 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]); 900 } 901 902 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 903 904 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 905 value &= ~TERM_RANGE_ADJ(~0); 906 value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj); 907 value &= ~RPD_CTRL(~0); 908 value |= RPD_CTRL(priv->calib.rpd_ctrl); 909 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 910 911 tegra186_utmi_pad_power_on(phy); 912 913 return 0; 914 } 915 916 static int tegra186_utmi_phy_power_off(struct phy *phy) 917 { 918 tegra186_utmi_pad_power_down(phy); 919 920 return 0; 921 } 922 923 static int tegra186_utmi_phy_init(struct phy *phy) 924 { 925 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 926 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 927 struct tegra_xusb_usb2_port *port; 928 unsigned int index = lane->index; 929 struct device *dev = padctl->dev; 930 int err; 931 u32 reg; 932 933 port = tegra_xusb_find_usb2_port(padctl, index); 934 if (!port) { 935 dev_err(dev, "no port found for USB2 lane %u\n", index); 936 return -ENODEV; 937 } 938 939 if (port->mode == USB_DR_MODE_OTG || 940 port->mode == USB_DR_MODE_PERIPHERAL) { 941 /* reset VBUS&ID OVERRIDE */ 942 reg = padctl_readl(padctl, USB2_VBUS_ID); 943 reg &= ~VBUS_OVERRIDE; 944 reg &= ~ID_OVERRIDE(~0); 945 reg |= ID_OVERRIDE_FLOATING; 946 padctl_writel(padctl, reg, USB2_VBUS_ID); 947 } 948 949 if (port->supply && port->mode == USB_DR_MODE_HOST) { 950 err = regulator_enable(port->supply); 951 if (err) { 952 dev_err(dev, "failed to enable port %u VBUS: %d\n", 953 index, err); 954 return err; 955 } 956 } 957 958 return 0; 959 } 960 961 static int tegra186_utmi_phy_exit(struct phy *phy) 962 { 963 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 964 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 965 struct tegra_xusb_usb2_port *port; 966 unsigned int index = lane->index; 967 struct device *dev = padctl->dev; 968 int err; 969 970 port = tegra_xusb_find_usb2_port(padctl, index); 971 if (!port) { 972 dev_err(dev, "no port found for USB2 lane %u\n", index); 973 return -ENODEV; 974 } 975 976 if (port->supply && port->mode == USB_DR_MODE_HOST) { 977 err = regulator_disable(port->supply); 978 if (err) { 979 dev_err(dev, "failed to disable port %u VBUS: %d\n", 980 index, err); 981 return err; 982 } 983 } 984 985 return 0; 986 } 987 988 static const struct phy_ops utmi_phy_ops = { 989 .init = tegra186_utmi_phy_init, 990 .exit = tegra186_utmi_phy_exit, 991 .power_on = tegra186_utmi_phy_power_on, 992 .power_off = tegra186_utmi_phy_power_off, 993 .set_mode = tegra186_utmi_phy_set_mode, 994 .owner = THIS_MODULE, 995 }; 996 997 static struct tegra_xusb_pad * 998 tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl, 999 const struct tegra_xusb_pad_soc *soc, 1000 struct device_node *np) 1001 { 1002 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 1003 struct tegra_xusb_usb2_pad *usb2; 1004 struct tegra_xusb_pad *pad; 1005 int err; 1006 1007 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); 1008 if (!usb2) 1009 return ERR_PTR(-ENOMEM); 1010 1011 pad = &usb2->base; 1012 pad->ops = &tegra186_usb2_lane_ops; 1013 pad->soc = soc; 1014 1015 err = tegra_xusb_pad_init(pad, padctl, np); 1016 if (err < 0) { 1017 kfree(usb2); 1018 goto out; 1019 } 1020 1021 priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk"); 1022 if (IS_ERR(priv->usb2_trk_clk)) { 1023 err = PTR_ERR(priv->usb2_trk_clk); 1024 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err); 1025 goto unregister; 1026 } 1027 1028 err = tegra_xusb_pad_register(pad, &utmi_phy_ops); 1029 if (err < 0) 1030 goto unregister; 1031 1032 dev_set_drvdata(&pad->dev, pad); 1033 1034 return pad; 1035 1036 unregister: 1037 device_unregister(&pad->dev); 1038 out: 1039 return ERR_PTR(err); 1040 } 1041 1042 static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad) 1043 { 1044 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad); 1045 1046 kfree(usb2); 1047 } 1048 1049 static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = { 1050 .probe = tegra186_usb2_pad_probe, 1051 .remove = tegra186_usb2_pad_remove, 1052 }; 1053 1054 static const char * const tegra186_usb2_functions[] = { 1055 "xusb", 1056 }; 1057 1058 static int tegra186_usb2_port_enable(struct tegra_xusb_port *port) 1059 { 1060 return 0; 1061 } 1062 1063 static void tegra186_usb2_port_disable(struct tegra_xusb_port *port) 1064 { 1065 } 1066 1067 static struct tegra_xusb_lane * 1068 tegra186_usb2_port_map(struct tegra_xusb_port *port) 1069 { 1070 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); 1071 } 1072 1073 static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = { 1074 .release = tegra_xusb_usb2_port_release, 1075 .remove = tegra_xusb_usb2_port_remove, 1076 .enable = tegra186_usb2_port_enable, 1077 .disable = tegra186_usb2_port_disable, 1078 .map = tegra186_usb2_port_map, 1079 }; 1080 1081 /* SuperSpeed PHY support */ 1082 static struct tegra_xusb_lane * 1083 tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 1084 unsigned int index) 1085 { 1086 struct tegra_xusb_usb3_lane *usb3; 1087 int err; 1088 1089 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL); 1090 if (!usb3) 1091 return ERR_PTR(-ENOMEM); 1092 1093 INIT_LIST_HEAD(&usb3->base.list); 1094 usb3->base.soc = &pad->soc->lanes[index]; 1095 usb3->base.index = index; 1096 usb3->base.pad = pad; 1097 usb3->base.np = np; 1098 1099 err = tegra_xusb_lane_parse_dt(&usb3->base, np); 1100 if (err < 0) { 1101 kfree(usb3); 1102 return ERR_PTR(err); 1103 } 1104 1105 return &usb3->base; 1106 } 1107 1108 static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane) 1109 { 1110 struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane); 1111 1112 kfree(usb3); 1113 } 1114 1115 static int tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, 1116 enum usb_device_speed speed) 1117 { 1118 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1119 unsigned int index = lane->index; 1120 u32 value; 1121 1122 mutex_lock(&padctl->lock); 1123 1124 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 1125 value |= SSPX_ELPG_CLAMP_EN_EARLY(index); 1126 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 1127 1128 usleep_range(100, 200); 1129 1130 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 1131 value |= SSPX_ELPG_CLAMP_EN(index); 1132 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 1133 1134 usleep_range(250, 350); 1135 1136 mutex_unlock(&padctl->lock); 1137 1138 return 0; 1139 } 1140 1141 static int tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane *lane) 1142 { 1143 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1144 unsigned int index = lane->index; 1145 u32 value; 1146 1147 mutex_lock(&padctl->lock); 1148 1149 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 1150 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index); 1151 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 1152 1153 usleep_range(100, 200); 1154 1155 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 1156 value &= ~SSPX_ELPG_CLAMP_EN(index); 1157 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 1158 1159 mutex_unlock(&padctl->lock); 1160 1161 return 0; 1162 } 1163 1164 static int tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane *lane) 1165 { 1166 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1167 unsigned int index = lane->index; 1168 u32 value; 1169 1170 mutex_lock(&padctl->lock); 1171 1172 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 1173 value &= ~ALL_WAKE_EVENTS; 1174 value |= SS_PORT_WAKEUP_EVENT(index); 1175 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 1176 1177 usleep_range(10, 20); 1178 1179 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 1180 value &= ~ALL_WAKE_EVENTS; 1181 value |= SS_PORT_WAKE_INTERRUPT_ENABLE(index); 1182 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 1183 1184 mutex_unlock(&padctl->lock); 1185 1186 return 0; 1187 } 1188 1189 static int tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane *lane) 1190 { 1191 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1192 unsigned int index = lane->index; 1193 u32 value; 1194 1195 mutex_lock(&padctl->lock); 1196 1197 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 1198 value &= ~ALL_WAKE_EVENTS; 1199 value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index); 1200 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 1201 1202 usleep_range(10, 20); 1203 1204 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 1205 value &= ~ALL_WAKE_EVENTS; 1206 value |= SS_PORT_WAKEUP_EVENT(index); 1207 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); 1208 1209 mutex_unlock(&padctl->lock); 1210 1211 return 0; 1212 } 1213 1214 static bool tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane *lane) 1215 { 1216 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1217 unsigned int index = lane->index; 1218 u32 value; 1219 1220 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); 1221 if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index))) 1222 return true; 1223 1224 return false; 1225 } 1226 1227 static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = { 1228 .probe = tegra186_usb3_lane_probe, 1229 .remove = tegra186_usb3_lane_remove, 1230 .enable_phy_sleepwalk = tegra186_usb3_enable_phy_sleepwalk, 1231 .disable_phy_sleepwalk = tegra186_usb3_disable_phy_sleepwalk, 1232 .enable_phy_wake = tegra186_usb3_enable_phy_wake, 1233 .disable_phy_wake = tegra186_usb3_disable_phy_wake, 1234 .remote_wake_detected = tegra186_usb3_phy_remote_wake_detected, 1235 }; 1236 1237 static int tegra186_usb3_port_enable(struct tegra_xusb_port *port) 1238 { 1239 return 0; 1240 } 1241 1242 static void tegra186_usb3_port_disable(struct tegra_xusb_port *port) 1243 { 1244 } 1245 1246 static struct tegra_xusb_lane * 1247 tegra186_usb3_port_map(struct tegra_xusb_port *port) 1248 { 1249 return tegra_xusb_find_lane(port->padctl, "usb3", port->index); 1250 } 1251 1252 static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = { 1253 .release = tegra_xusb_usb3_port_release, 1254 .enable = tegra186_usb3_port_enable, 1255 .disable = tegra186_usb3_port_disable, 1256 .map = tegra186_usb3_port_map, 1257 }; 1258 1259 static int tegra186_usb3_phy_power_on(struct phy *phy) 1260 { 1261 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1262 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1263 struct tegra_xusb_usb3_port *port; 1264 struct tegra_xusb_usb2_port *usb2; 1265 unsigned int index = lane->index; 1266 struct device *dev = padctl->dev; 1267 u32 value; 1268 1269 port = tegra_xusb_find_usb3_port(padctl, index); 1270 if (!port) { 1271 dev_err(dev, "no port found for USB3 lane %u\n", index); 1272 return -ENODEV; 1273 } 1274 1275 usb2 = tegra_xusb_find_usb2_port(padctl, port->port); 1276 if (!usb2) { 1277 dev_err(dev, "no companion port found for USB3 lane %u\n", 1278 index); 1279 return -ENODEV; 1280 } 1281 1282 mutex_lock(&padctl->lock); 1283 1284 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP); 1285 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index)); 1286 1287 if (usb2->mode == USB_DR_MODE_UNKNOWN) 1288 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index)); 1289 else if (usb2->mode == USB_DR_MODE_PERIPHERAL) 1290 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index)); 1291 else if (usb2->mode == USB_DR_MODE_HOST) 1292 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index)); 1293 else if (usb2->mode == USB_DR_MODE_OTG) 1294 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index)); 1295 1296 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP); 1297 1298 if (padctl->soc->supports_gen2 && port->disable_gen2) { 1299 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG); 1300 value &= ~(PORTX_SPEED_SUPPORT_MASK << 1301 PORTX_SPEED_SUPPORT_SHIFT(index)); 1302 value |= (PORT_SPEED_SUPPORT_GEN1 << 1303 PORTX_SPEED_SUPPORT_SHIFT(index)); 1304 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG); 1305 } 1306 1307 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 1308 value &= ~SSPX_ELPG_VCORE_DOWN(index); 1309 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 1310 1311 usleep_range(100, 200); 1312 1313 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 1314 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index); 1315 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 1316 1317 usleep_range(100, 200); 1318 1319 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 1320 value &= ~SSPX_ELPG_CLAMP_EN(index); 1321 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 1322 1323 mutex_unlock(&padctl->lock); 1324 1325 return 0; 1326 } 1327 1328 static int tegra186_usb3_phy_power_off(struct phy *phy) 1329 { 1330 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1331 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1332 struct tegra_xusb_usb3_port *port; 1333 unsigned int index = lane->index; 1334 struct device *dev = padctl->dev; 1335 u32 value; 1336 1337 port = tegra_xusb_find_usb3_port(padctl, index); 1338 if (!port) { 1339 dev_err(dev, "no port found for USB3 lane %u\n", index); 1340 return -ENODEV; 1341 } 1342 1343 mutex_lock(&padctl->lock); 1344 1345 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 1346 value |= SSPX_ELPG_CLAMP_EN_EARLY(index); 1347 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 1348 1349 usleep_range(100, 200); 1350 1351 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 1352 value |= SSPX_ELPG_CLAMP_EN(index); 1353 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 1354 1355 usleep_range(250, 350); 1356 1357 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); 1358 value |= SSPX_ELPG_VCORE_DOWN(index); 1359 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); 1360 1361 mutex_unlock(&padctl->lock); 1362 1363 return 0; 1364 } 1365 1366 static int tegra186_usb3_phy_init(struct phy *phy) 1367 { 1368 return 0; 1369 } 1370 1371 static int tegra186_usb3_phy_exit(struct phy *phy) 1372 { 1373 return 0; 1374 } 1375 1376 static const struct phy_ops usb3_phy_ops = { 1377 .init = tegra186_usb3_phy_init, 1378 .exit = tegra186_usb3_phy_exit, 1379 .power_on = tegra186_usb3_phy_power_on, 1380 .power_off = tegra186_usb3_phy_power_off, 1381 .owner = THIS_MODULE, 1382 }; 1383 1384 static struct tegra_xusb_pad * 1385 tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl, 1386 const struct tegra_xusb_pad_soc *soc, 1387 struct device_node *np) 1388 { 1389 struct tegra_xusb_usb3_pad *usb3; 1390 struct tegra_xusb_pad *pad; 1391 int err; 1392 1393 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL); 1394 if (!usb3) 1395 return ERR_PTR(-ENOMEM); 1396 1397 pad = &usb3->base; 1398 pad->ops = &tegra186_usb3_lane_ops; 1399 pad->soc = soc; 1400 1401 err = tegra_xusb_pad_init(pad, padctl, np); 1402 if (err < 0) { 1403 kfree(usb3); 1404 goto out; 1405 } 1406 1407 err = tegra_xusb_pad_register(pad, &usb3_phy_ops); 1408 if (err < 0) 1409 goto unregister; 1410 1411 dev_set_drvdata(&pad->dev, pad); 1412 1413 return pad; 1414 1415 unregister: 1416 device_unregister(&pad->dev); 1417 out: 1418 return ERR_PTR(err); 1419 } 1420 1421 static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad) 1422 { 1423 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad); 1424 1425 kfree(usb2); 1426 } 1427 1428 static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = { 1429 .probe = tegra186_usb3_pad_probe, 1430 .remove = tegra186_usb3_pad_remove, 1431 }; 1432 1433 static const char * const tegra186_usb3_functions[] = { 1434 "xusb", 1435 }; 1436 1437 static int 1438 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl) 1439 { 1440 struct device *dev = padctl->base.dev; 1441 unsigned int i, count; 1442 u32 value, *level; 1443 int err; 1444 1445 count = padctl->base.soc->ports.usb2.count; 1446 1447 level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL); 1448 if (!level) 1449 return -ENOMEM; 1450 1451 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value); 1452 if (err) 1453 return dev_err_probe(dev, err, 1454 "failed to read calibration fuse\n"); 1455 1456 dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value); 1457 1458 for (i = 0; i < count; i++) 1459 level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) & 1460 HS_CURR_LEVEL_PAD_MASK; 1461 1462 padctl->calib.hs_curr_level = level; 1463 1464 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) & 1465 HS_SQUELCH_MASK; 1466 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) & 1467 HS_TERM_RANGE_ADJ_MASK; 1468 1469 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value); 1470 if (err) { 1471 dev_err(dev, "failed to read calibration fuse: %d\n", err); 1472 return err; 1473 } 1474 1475 dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value); 1476 1477 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK; 1478 1479 return 0; 1480 } 1481 1482 static struct tegra_xusb_padctl * 1483 tegra186_xusb_padctl_probe(struct device *dev, 1484 const struct tegra_xusb_padctl_soc *soc) 1485 { 1486 struct platform_device *pdev = to_platform_device(dev); 1487 struct tegra186_xusb_padctl *priv; 1488 struct resource *res; 1489 int err; 1490 1491 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1492 if (!priv) 1493 return ERR_PTR(-ENOMEM); 1494 1495 priv->base.dev = dev; 1496 priv->base.soc = soc; 1497 1498 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao"); 1499 priv->ao_regs = devm_ioremap_resource(dev, res); 1500 if (IS_ERR(priv->ao_regs)) 1501 return ERR_CAST(priv->ao_regs); 1502 1503 err = tegra186_xusb_read_fuse_calibration(priv); 1504 if (err < 0) 1505 return ERR_PTR(err); 1506 1507 return &priv->base; 1508 } 1509 1510 static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl) 1511 { 1512 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 1513 1514 priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID); 1515 priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); 1516 priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); 1517 priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP); 1518 } 1519 1520 static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl) 1521 { 1522 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); 1523 1524 padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX); 1525 padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP); 1526 padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP); 1527 padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID); 1528 } 1529 1530 static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl) 1531 { 1532 tegra186_xusb_padctl_save(padctl); 1533 1534 return 0; 1535 } 1536 1537 static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl) 1538 { 1539 tegra186_xusb_padctl_restore(padctl); 1540 1541 return 0; 1542 } 1543 1544 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl) 1545 { 1546 } 1547 1548 static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = { 1549 .probe = tegra186_xusb_padctl_probe, 1550 .remove = tegra186_xusb_padctl_remove, 1551 .suspend_noirq = tegra186_xusb_padctl_suspend_noirq, 1552 .resume_noirq = tegra186_xusb_padctl_resume_noirq, 1553 .vbus_override = tegra186_xusb_padctl_vbus_override, 1554 .utmi_pad_power_on = tegra186_utmi_pad_power_on, 1555 .utmi_pad_power_down = tegra186_utmi_pad_power_down, 1556 }; 1557 1558 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) 1559 static const char * const tegra186_xusb_padctl_supply_names[] = { 1560 "avdd-pll-erefeut", 1561 "avdd-usb", 1562 "vclamp-usb", 1563 "vddio-hsic", 1564 }; 1565 1566 static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { 1567 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2), 1568 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2), 1569 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2), 1570 }; 1571 1572 static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { 1573 .name = "usb2", 1574 .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes), 1575 .lanes = tegra186_usb2_lanes, 1576 .ops = &tegra186_usb2_pad_ops, 1577 }; 1578 1579 static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { 1580 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3), 1581 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3), 1582 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3), 1583 }; 1584 1585 static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { 1586 .name = "usb3", 1587 .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes), 1588 .lanes = tegra186_usb3_lanes, 1589 .ops = &tegra186_usb3_pad_ops, 1590 }; 1591 1592 static const struct tegra_xusb_pad_soc * const tegra186_pads[] = { 1593 &tegra186_usb2_pad, 1594 &tegra186_usb3_pad, 1595 #if 0 /* TODO implement */ 1596 &tegra186_hsic_pad, 1597 #endif 1598 }; 1599 1600 const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { 1601 .num_pads = ARRAY_SIZE(tegra186_pads), 1602 .pads = tegra186_pads, 1603 .ports = { 1604 .usb2 = { 1605 .ops = &tegra186_usb2_port_ops, 1606 .count = 3, 1607 }, 1608 #if 0 /* TODO implement */ 1609 .hsic = { 1610 .ops = &tegra186_hsic_port_ops, 1611 .count = 1, 1612 }, 1613 #endif 1614 .usb3 = { 1615 .ops = &tegra186_usb3_port_ops, 1616 .count = 3, 1617 }, 1618 }, 1619 .ops = &tegra186_xusb_padctl_ops, 1620 .supply_names = tegra186_xusb_padctl_supply_names, 1621 .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names), 1622 }; 1623 EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); 1624 #endif 1625 1626 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ 1627 IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) 1628 static const char * const tegra194_xusb_padctl_supply_names[] = { 1629 "avdd-usb", 1630 "vclamp-usb", 1631 }; 1632 1633 static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = { 1634 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2), 1635 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2), 1636 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2), 1637 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2), 1638 }; 1639 1640 static const struct tegra_xusb_pad_soc tegra194_usb2_pad = { 1641 .name = "usb2", 1642 .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes), 1643 .lanes = tegra194_usb2_lanes, 1644 .ops = &tegra186_usb2_pad_ops, 1645 }; 1646 1647 static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = { 1648 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3), 1649 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3), 1650 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3), 1651 TEGRA186_LANE("usb3-3", 0, 0, 0, usb3), 1652 }; 1653 1654 static const struct tegra_xusb_pad_soc tegra194_usb3_pad = { 1655 .name = "usb3", 1656 .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes), 1657 .lanes = tegra194_usb3_lanes, 1658 .ops = &tegra186_usb3_pad_ops, 1659 }; 1660 1661 static const struct tegra_xusb_pad_soc * const tegra194_pads[] = { 1662 &tegra194_usb2_pad, 1663 &tegra194_usb3_pad, 1664 }; 1665 1666 const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = { 1667 .num_pads = ARRAY_SIZE(tegra194_pads), 1668 .pads = tegra194_pads, 1669 .ports = { 1670 .usb2 = { 1671 .ops = &tegra186_usb2_port_ops, 1672 .count = 4, 1673 }, 1674 .usb3 = { 1675 .ops = &tegra186_usb3_port_ops, 1676 .count = 4, 1677 }, 1678 }, 1679 .ops = &tegra186_xusb_padctl_ops, 1680 .supply_names = tegra194_xusb_padctl_supply_names, 1681 .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), 1682 .supports_gen2 = true, 1683 .poll_trk_completed = true, 1684 }; 1685 EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc); 1686 1687 const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = { 1688 .num_pads = ARRAY_SIZE(tegra194_pads), 1689 .pads = tegra194_pads, 1690 .ports = { 1691 .usb2 = { 1692 .ops = &tegra186_usb2_port_ops, 1693 .count = 4, 1694 }, 1695 .usb3 = { 1696 .ops = &tegra186_usb3_port_ops, 1697 .count = 4, 1698 }, 1699 }, 1700 .ops = &tegra186_xusb_padctl_ops, 1701 .supply_names = tegra194_xusb_padctl_supply_names, 1702 .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), 1703 .supports_gen2 = true, 1704 .poll_trk_completed = true, 1705 .trk_hw_mode = true, 1706 .supports_lp_cfg_en = true, 1707 }; 1708 EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc); 1709 #endif 1710 1711 MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>"); 1712 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver"); 1713 MODULE_LICENSE("GPL v2"); 1714