1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STMicroelectronics COMBOPHY STM32MP25 Controller driver. 4 * 5 * Copyright (C) 2024 STMicroelectronics 6 * Author: Christian Bruel <christian.bruel@foss.st.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/platform_device.h> 13 #include <linux/phy/phy.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 #include <dt-bindings/phy/phy.h> 18 19 #define SYSCFG_COMBOPHY_CR1 0x4c00 20 #define SYSCFG_COMBOPHY_CR2 0x4c04 21 #define SYSCFG_COMBOPHY_CR4 0x4c0c 22 #define SYSCFG_COMBOPHY_CR5 0x4c10 23 #define SYSCFG_COMBOPHY_SR 0x4c14 24 #define SYSCFG_PCIEPRGCR 0x6080 25 26 /* SYSCFG PCIEPRGCR */ 27 #define STM32MP25_PCIEPRGCR_EN BIT(0) 28 #define STM32MP25_PCIEPRG_IMPCTRL_OHM GENMASK(3, 1) 29 #define STM32MP25_PCIEPRG_IMPCTRL_VSWING GENMASK(5, 4) 30 31 /* SYSCFG SYSCFG_COMBOPHY_SR */ 32 #define STM32MP25_PIPE0_PHYSTATUS BIT(1) 33 34 /* SYSCFG CR1 */ 35 #define SYSCFG_COMBOPHY_CR1_REFUSEPAD BIT(0) 36 #define SYSCFG_COMBOPHY_CR1_MPLLMULT GENMASK(7, 1) 37 #define SYSCFG_COMBOPHY_CR1_REFCLKSEL GENMASK(16, 8) 38 #define SYSCFG_COMBOPHY_CR1_REFCLKDIV2 BIT(17) 39 #define SYSCFG_COMBOPHY_CR1_REFSSPEN BIT(18) 40 #define SYSCFG_COMBOPHY_CR1_SSCEN BIT(19) 41 42 /* SYSCFG CR4 */ 43 #define SYSCFG_COMBOPHY_CR4_RX0_EQ GENMASK(2, 0) 44 45 #define MPLLMULT_19_2 (0x02u << 1) 46 #define MPLLMULT_20 (0x7du << 1) 47 #define MPLLMULT_24 (0x68u << 1) 48 #define MPLLMULT_25 (0x64u << 1) 49 #define MPLLMULT_26 (0x60u << 1) 50 #define MPLLMULT_38_4 (0x41u << 1) 51 #define MPLLMULT_48 (0x6cu << 1) 52 #define MPLLMULT_50 (0x32u << 1) 53 #define MPLLMULT_52 (0x30u << 1) 54 #define MPLLMULT_100 (0x19u << 1) 55 56 #define REFCLKSEL_0 0 57 #define REFCLKSEL_1 (0x108u << 8) 58 59 #define REFCLDIV_0 0 60 61 /* SYSCFG CR2 */ 62 #define SYSCFG_COMBOPHY_CR2_MODESEL GENMASK(1, 0) 63 #define SYSCFG_COMBOPHY_CR2_ISO_DIS BIT(15) 64 65 #define COMBOPHY_MODESEL_PCIE 0 66 #define COMBOPHY_MODESEL_USB 3 67 68 /* SYSCFG CR5 */ 69 #define SYSCFG_COMBOPHY_CR5_COMMON_CLOCKS BIT(12) 70 71 #define COMBOPHY_SUP_ANA_MPLL_LOOP_CTL 0xc0 72 #define COMBOPHY_PROP_CNTRL GENMASK(7, 4) 73 74 /* Required apb/ker clocks first, optional pad last. */ 75 static const char * const combophy_clks[] = {"apb", "ker", "pad"}; 76 #define APB_CLK 0 77 #define KER_CLK 1 78 #define PAD_CLK 2 79 80 struct stm32_combophy { 81 struct phy *phy; 82 struct regmap *regmap; 83 struct device *dev; 84 void __iomem *base; 85 struct reset_control *phy_reset; 86 struct clk_bulk_data clks[ARRAY_SIZE(combophy_clks)]; 87 int num_clks; 88 bool have_pad_clk; 89 unsigned int type; 90 bool is_init; 91 int irq_wakeup; 92 }; 93 94 struct clk_impedance { 95 u32 microohm; 96 u32 vswing[4]; 97 }; 98 99 /* 100 * lookup table to hold the settings needed for a ref clock frequency 101 * impedance, the offset is used to set the IMP_CTL and DE_EMP bit of the 102 * PRG_IMP_CTRL register. Use ordered discrete values in the table 103 */ 104 static const struct clk_impedance imp_lookup[] = { 105 { 6090000, { 442000, 564000, 684000, 802000 } }, 106 { 5662000, { 528000, 621000, 712000, 803000 } }, 107 { 5292000, { 491000, 596000, 700000, 802000 } }, 108 { 4968000, { 558000, 640000, 722000, 803000 } }, 109 { 4684000, { 468000, 581000, 692000, 802000 } }, 110 { 4429000, { 554000, 613000, 717000, 803000 } }, 111 { 4204000, { 511000, 609000, 706000, 802000 } }, 112 { 3999000, { 571000, 648000, 726000, 803000 } } 113 }; 114 #define DEFAULT_IMP_INDEX 3 /* Default impedance is 50 Ohm */ 115 116 static int stm32_impedance_tune(struct stm32_combophy *combophy) 117 { 118 u8 imp_size = ARRAY_SIZE(imp_lookup); 119 u8 vswing_size = ARRAY_SIZE(imp_lookup[0].vswing); 120 u8 imp_of, vswing_of; 121 u32 max_imp = imp_lookup[0].microohm; 122 u32 min_imp = imp_lookup[imp_size - 1].microohm; 123 u32 max_vswing; 124 u32 min_vswing = imp_lookup[0].vswing[0]; 125 u32 val; 126 127 if (!of_property_read_u32(combophy->dev->of_node, "st,output-micro-ohms", &val)) { 128 if (val < min_imp || val > max_imp) { 129 dev_err(combophy->dev, "Invalid value %u for output ohm\n", val); 130 return -EINVAL; 131 } 132 133 for (imp_of = 0; imp_of < ARRAY_SIZE(imp_lookup); imp_of++) 134 if (imp_lookup[imp_of].microohm <= val) 135 break; 136 137 if (WARN_ON(imp_of == ARRAY_SIZE(imp_lookup))) 138 return -EINVAL; 139 140 dev_dbg(combophy->dev, "Set %u micro-ohms output impedance\n", 141 imp_lookup[imp_of].microohm); 142 143 regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, 144 STM32MP25_PCIEPRG_IMPCTRL_OHM, 145 FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_OHM, imp_of)); 146 } else 147 imp_of = DEFAULT_IMP_INDEX; 148 149 if (!of_property_read_u32(combophy->dev->of_node, "st,output-vswing-microvolt", &val)) { 150 max_vswing = imp_lookup[imp_of].vswing[vswing_size - 1]; 151 152 if (val < min_vswing || val > max_vswing) { 153 dev_err(combophy->dev, "Invalid value %u for output vswing\n", val); 154 return -EINVAL; 155 } 156 157 for (vswing_of = 0; vswing_of < ARRAY_SIZE(imp_lookup[imp_of].vswing); vswing_of++) 158 if (imp_lookup[imp_of].vswing[vswing_of] >= val) 159 break; 160 161 if (WARN_ON(vswing_of == ARRAY_SIZE(imp_lookup[imp_of].vswing))) 162 return -EINVAL; 163 164 dev_dbg(combophy->dev, "Set %u microvolt swing\n", 165 imp_lookup[imp_of].vswing[vswing_of]); 166 167 regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, 168 STM32MP25_PCIEPRG_IMPCTRL_VSWING, 169 FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_VSWING, vswing_of)); 170 } 171 172 return 0; 173 } 174 175 static int stm32_combophy_pll_init(struct stm32_combophy *combophy) 176 { 177 int ret; 178 u32 refclksel, pllmult, propcntrl, val; 179 u32 clk_rate; 180 struct clk *clk; 181 u32 cr1_val = 0, cr1_mask = 0; 182 183 if (combophy->have_pad_clk) 184 clk = combophy->clks[PAD_CLK].clk; 185 else 186 clk = combophy->clks[KER_CLK].clk; 187 188 clk_rate = clk_get_rate(clk); 189 190 dev_dbg(combophy->dev, "%s pll init rate %d\n", 191 combophy->have_pad_clk ? "External" : "Ker", clk_rate); 192 193 if (combophy->type != PHY_TYPE_PCIE) { 194 cr1_mask |= SYSCFG_COMBOPHY_CR1_REFSSPEN; 195 cr1_val |= SYSCFG_COMBOPHY_CR1_REFSSPEN; 196 } 197 198 if (of_property_present(combophy->dev->of_node, "st,ssc-on")) { 199 dev_dbg(combophy->dev, "Enabling clock with SSC\n"); 200 cr1_mask |= SYSCFG_COMBOPHY_CR1_SSCEN; 201 cr1_val |= SYSCFG_COMBOPHY_CR1_SSCEN; 202 } 203 204 switch (clk_rate) { 205 case 100000000: 206 pllmult = MPLLMULT_100; 207 refclksel = REFCLKSEL_0; 208 propcntrl = 0x8u << 4; 209 break; 210 case 19200000: 211 pllmult = MPLLMULT_19_2; 212 refclksel = REFCLKSEL_1; 213 propcntrl = 0x8u << 4; 214 break; 215 case 25000000: 216 pllmult = MPLLMULT_25; 217 refclksel = REFCLKSEL_0; 218 propcntrl = 0xeu << 4; 219 break; 220 case 24000000: 221 pllmult = MPLLMULT_24; 222 refclksel = REFCLKSEL_1; 223 propcntrl = 0xeu << 4; 224 break; 225 case 20000000: 226 pllmult = MPLLMULT_20; 227 refclksel = REFCLKSEL_0; 228 propcntrl = 0xeu << 4; 229 break; 230 default: 231 dev_err(combophy->dev, "Invalid rate 0x%x\n", clk_rate); 232 return -EINVAL; 233 } 234 235 cr1_mask |= SYSCFG_COMBOPHY_CR1_REFCLKDIV2; 236 cr1_val |= REFCLDIV_0; 237 238 cr1_mask |= SYSCFG_COMBOPHY_CR1_REFCLKSEL; 239 cr1_val |= refclksel; 240 241 cr1_mask |= SYSCFG_COMBOPHY_CR1_MPLLMULT; 242 cr1_val |= pllmult; 243 244 /* 245 * vddcombophy is interconnected with vddcore. Isolation bit should be unset 246 * before using the ComboPHY. 247 */ 248 regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2, 249 SYSCFG_COMBOPHY_CR2_ISO_DIS, SYSCFG_COMBOPHY_CR2_ISO_DIS); 250 251 reset_control_assert(combophy->phy_reset); 252 253 if (combophy->type == PHY_TYPE_PCIE) { 254 ret = stm32_impedance_tune(combophy); 255 if (ret) 256 goto out_iso; 257 258 cr1_mask |= SYSCFG_COMBOPHY_CR1_REFUSEPAD; 259 cr1_val |= combophy->have_pad_clk ? SYSCFG_COMBOPHY_CR1_REFUSEPAD : 0; 260 } 261 262 if (!of_property_read_u32(combophy->dev->of_node, "st,rx-equalizer", &val)) { 263 dev_dbg(combophy->dev, "Set RX equalizer %u\n", val); 264 if (val > SYSCFG_COMBOPHY_CR4_RX0_EQ) { 265 dev_err(combophy->dev, "Invalid value %u for rx0 equalizer\n", val); 266 ret = -EINVAL; 267 goto out_iso; 268 } 269 270 regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR4, 271 SYSCFG_COMBOPHY_CR4_RX0_EQ, val); 272 } 273 274 regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR1, cr1_mask, cr1_val); 275 276 /* 277 * Force elasticity buffer to be tuned for the reference clock as 278 * the separated clock model is not supported 279 */ 280 regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR5, 281 SYSCFG_COMBOPHY_CR5_COMMON_CLOCKS, SYSCFG_COMBOPHY_CR5_COMMON_CLOCKS); 282 283 reset_control_deassert(combophy->phy_reset); 284 285 ret = regmap_read_poll_timeout(combophy->regmap, SYSCFG_COMBOPHY_SR, val, 286 !(val & STM32MP25_PIPE0_PHYSTATUS), 287 10, 1000); 288 if (ret) { 289 dev_err(combophy->dev, "timeout, cannot lock PLL\n"); 290 if (combophy->type == PHY_TYPE_PCIE && !combophy->have_pad_clk) 291 regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, 292 STM32MP25_PCIEPRGCR_EN, 0); 293 294 if (combophy->type != PHY_TYPE_PCIE) 295 regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR1, 296 SYSCFG_COMBOPHY_CR1_REFSSPEN, 0); 297 298 goto out; 299 } 300 301 302 if (combophy->type == PHY_TYPE_PCIE) { 303 if (!combophy->have_pad_clk) 304 regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, 305 STM32MP25_PCIEPRGCR_EN, STM32MP25_PCIEPRGCR_EN); 306 307 val = readl_relaxed(combophy->base + COMBOPHY_SUP_ANA_MPLL_LOOP_CTL); 308 val &= ~COMBOPHY_PROP_CNTRL; 309 val |= propcntrl; 310 writel_relaxed(val, combophy->base + COMBOPHY_SUP_ANA_MPLL_LOOP_CTL); 311 } 312 313 return 0; 314 315 out_iso: 316 reset_control_deassert(combophy->phy_reset); 317 318 out: 319 regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2, 320 SYSCFG_COMBOPHY_CR2_ISO_DIS, 0); 321 322 return ret; 323 } 324 325 static struct phy *stm32_combophy_xlate(struct device *dev, 326 const struct of_phandle_args *args) 327 { 328 struct stm32_combophy *combophy = dev_get_drvdata(dev); 329 unsigned int type; 330 331 if (args->args_count != 1) { 332 dev_err(dev, "invalid number of cells in 'phy' property\n"); 333 return ERR_PTR(-EINVAL); 334 } 335 336 type = args->args[0]; 337 if (type != PHY_TYPE_USB3 && type != PHY_TYPE_PCIE) { 338 dev_err(dev, "unsupported device type: %d\n", type); 339 return ERR_PTR(-EINVAL); 340 } 341 342 if (combophy->have_pad_clk && type != PHY_TYPE_PCIE) { 343 dev_err(dev, "Invalid use of clk_pad for USB3 mode\n"); 344 return ERR_PTR(-EINVAL); 345 } 346 347 combophy->type = type; 348 349 return combophy->phy; 350 } 351 352 static int stm32_combophy_set_mode(struct stm32_combophy *combophy) 353 { 354 int type = combophy->type; 355 u32 val; 356 357 switch (type) { 358 case PHY_TYPE_PCIE: 359 dev_dbg(combophy->dev, "setting PCIe ComboPHY\n"); 360 val = COMBOPHY_MODESEL_PCIE; 361 break; 362 case PHY_TYPE_USB3: 363 dev_dbg(combophy->dev, "setting USB3 ComboPHY\n"); 364 val = COMBOPHY_MODESEL_USB; 365 break; 366 default: 367 dev_err(combophy->dev, "Invalid PHY mode %d\n", type); 368 return -EINVAL; 369 } 370 371 return regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2, 372 SYSCFG_COMBOPHY_CR2_MODESEL, val); 373 } 374 375 static int stm32_combophy_suspend_noirq(struct device *dev) 376 { 377 struct stm32_combophy *combophy = dev_get_drvdata(dev); 378 379 /* 380 * Clocks should be turned off since it is not needed for 381 * wakeup capability. In case usb-remote wakeup is not enabled, 382 * combo-phy is already turned off by HCD driver using exit callback 383 */ 384 if (combophy->is_init) { 385 clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks); 386 387 /* since wakeup is enabled for ctrl */ 388 enable_irq_wake(combophy->irq_wakeup); 389 } 390 391 return 0; 392 } 393 394 static int stm32_combophy_resume_noirq(struct device *dev) 395 { 396 struct stm32_combophy *combophy = dev_get_drvdata(dev); 397 int ret; 398 399 /* 400 * If clocks was turned off by suspend call for wakeup then needs 401 * to be turned back ON in resume. In case usb-remote wakeup is not 402 * enabled, clocks already turned ON by HCD driver using init callback 403 */ 404 if (combophy->is_init) { 405 /* since wakeup was enabled for ctrl */ 406 disable_irq_wake(combophy->irq_wakeup); 407 408 ret = clk_bulk_prepare_enable(combophy->num_clks, combophy->clks); 409 if (ret) { 410 dev_err(dev, "can't enable clocks (%d)\n", ret); 411 return ret; 412 } 413 } 414 415 return 0; 416 } 417 418 static int stm32_combophy_exit(struct phy *phy) 419 { 420 struct stm32_combophy *combophy = phy_get_drvdata(phy); 421 struct device *dev = combophy->dev; 422 423 combophy->is_init = false; 424 425 if (combophy->type == PHY_TYPE_PCIE && !combophy->have_pad_clk) 426 regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, 427 STM32MP25_PCIEPRGCR_EN, 0); 428 429 if (combophy->type != PHY_TYPE_PCIE) 430 regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR1, 431 SYSCFG_COMBOPHY_CR1_REFSSPEN, 0); 432 433 regmap_update_bits(combophy->regmap, SYSCFG_COMBOPHY_CR2, 434 SYSCFG_COMBOPHY_CR2_ISO_DIS, 0); 435 436 clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks); 437 438 pm_runtime_put_noidle(dev); 439 440 return 0; 441 } 442 443 static int stm32_combophy_init(struct phy *phy) 444 { 445 struct stm32_combophy *combophy = phy_get_drvdata(phy); 446 struct device *dev = combophy->dev; 447 int ret; 448 449 pm_runtime_get_noresume(dev); 450 451 ret = clk_bulk_prepare_enable(combophy->num_clks, combophy->clks); 452 if (ret) { 453 dev_err(dev, "can't enable clocks (%d)\n", ret); 454 pm_runtime_put_noidle(dev); 455 return ret; 456 } 457 458 ret = stm32_combophy_set_mode(combophy); 459 if (ret) { 460 dev_err(dev, "combophy mode not set\n"); 461 clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks); 462 pm_runtime_put_noidle(dev); 463 return ret; 464 } 465 466 ret = stm32_combophy_pll_init(combophy); 467 if (ret) { 468 clk_bulk_disable_unprepare(combophy->num_clks, combophy->clks); 469 pm_runtime_put_noidle(dev); 470 return ret; 471 } 472 473 pm_runtime_disable(dev); 474 pm_runtime_set_active(dev); 475 pm_runtime_enable(dev); 476 477 combophy->is_init = true; 478 479 return ret; 480 } 481 482 static const struct phy_ops stm32_combophy_phy_data = { 483 .init = stm32_combophy_init, 484 .exit = stm32_combophy_exit, 485 .owner = THIS_MODULE 486 }; 487 488 static irqreturn_t stm32_combophy_irq_wakeup_handler(int irq, void *dev_id) 489 { 490 return IRQ_HANDLED; 491 } 492 493 static int stm32_combophy_get_clocks(struct stm32_combophy *combophy) 494 { 495 int i, ret; 496 497 for (i = 0; i < ARRAY_SIZE(combophy_clks); i++) 498 combophy->clks[i].id = combophy_clks[i]; 499 500 combophy->num_clks = ARRAY_SIZE(combophy_clks) - 1; 501 502 ret = devm_clk_bulk_get(combophy->dev, combophy->num_clks, combophy->clks); 503 if (ret) 504 return ret; 505 506 ret = devm_clk_bulk_get_optional(combophy->dev, 1, combophy->clks + combophy->num_clks); 507 if (ret) 508 return ret; 509 510 if (combophy->clks[combophy->num_clks].clk != NULL) { 511 combophy->have_pad_clk = true; 512 combophy->num_clks++; 513 } 514 515 return 0; 516 } 517 518 static int stm32_combophy_probe(struct platform_device *pdev) 519 { 520 struct stm32_combophy *combophy; 521 struct device *dev = &pdev->dev; 522 struct phy_provider *phy_provider; 523 int ret, irq; 524 525 combophy = devm_kzalloc(dev, sizeof(*combophy), GFP_KERNEL); 526 if (!combophy) 527 return -ENOMEM; 528 529 combophy->dev = dev; 530 531 dev_set_drvdata(dev, combophy); 532 533 combophy->base = devm_platform_ioremap_resource(pdev, 0); 534 if (IS_ERR(combophy->base)) 535 return PTR_ERR(combophy->base); 536 537 ret = stm32_combophy_get_clocks(combophy); 538 if (ret) 539 return ret; 540 541 combophy->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); 542 if (IS_ERR(combophy->phy_reset)) 543 return dev_err_probe(dev, PTR_ERR(combophy->phy_reset), 544 "Failed to get PHY reset\n"); 545 546 combophy->regmap = syscon_regmap_lookup_by_compatible("st,stm32mp25-syscfg"); 547 if (IS_ERR(combophy->regmap)) 548 return dev_err_probe(dev, PTR_ERR(combophy->regmap), 549 "No syscfg specified\n"); 550 551 combophy->phy = devm_phy_create(dev, NULL, &stm32_combophy_phy_data); 552 if (IS_ERR(combophy->phy)) 553 return dev_err_probe(dev, PTR_ERR(combophy->phy), 554 "failed to create PCIe/USB3 ComboPHY\n"); 555 556 if (device_property_read_bool(dev, "wakeup-source")) { 557 irq = platform_get_irq(pdev, 0); 558 if (irq < 0) 559 return dev_err_probe(dev, irq, "failed to get IRQ\n"); 560 combophy->irq_wakeup = irq; 561 562 ret = devm_request_threaded_irq(dev, combophy->irq_wakeup, NULL, 563 stm32_combophy_irq_wakeup_handler, IRQF_ONESHOT, 564 NULL, NULL); 565 if (ret) 566 return dev_err_probe(dev, ret, "unable to request wake IRQ %d\n", 567 combophy->irq_wakeup); 568 } 569 570 ret = devm_pm_runtime_enable(dev); 571 if (ret) 572 return dev_err_probe(dev, ret, "Failed to enable pm runtime\n"); 573 574 phy_set_drvdata(combophy->phy, combophy); 575 576 phy_provider = devm_of_phy_provider_register(dev, stm32_combophy_xlate); 577 578 return PTR_ERR_OR_ZERO(phy_provider); 579 } 580 581 static const struct dev_pm_ops stm32_combophy_pm_ops = { 582 NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_combophy_suspend_noirq, 583 stm32_combophy_resume_noirq) 584 }; 585 586 static const struct of_device_id stm32_combophy_of_match[] = { 587 { .compatible = "st,stm32mp25-combophy", }, 588 { }, 589 }; 590 MODULE_DEVICE_TABLE(of, stm32_combophy_of_match); 591 592 static struct platform_driver stm32_combophy_driver = { 593 .probe = stm32_combophy_probe, 594 .driver = { 595 .name = "stm32-combophy", 596 .of_match_table = stm32_combophy_of_match, 597 .pm = pm_sleep_ptr(&stm32_combophy_pm_ops) 598 } 599 }; 600 601 module_platform_driver(stm32_combophy_driver); 602 603 MODULE_AUTHOR("Christian Bruel <christian.bruel@foss.st.com>"); 604 MODULE_DESCRIPTION("STM32MP25 Combophy USB3/PCIe controller driver"); 605 MODULE_LICENSE("GPL"); 606