1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ST SPEAr1310-miphy driver 4 * 5 * Copyright (C) 2014 ST Microelectronics 6 * Pratyush Anand <pratyush.anand@gmail.com> 7 * Mohit Kumar <mohit.kumar.dhaka@gmail.com> 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/kernel.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 21 /* SPEAr1310 Registers */ 22 #define SPEAR1310_PCIE_SATA_CFG 0x3A4 23 #define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31) 24 #define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30) 25 #define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29) 26 #define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31) 27 #define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30) 28 #define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29) 29 #define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27) 30 #define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26) 31 #define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25) 32 #define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24) 33 #define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23) 34 #define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22) 35 #define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21) 36 #define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20) 37 #define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19) 38 #define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18) 39 #define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17) 40 #define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16) 41 #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11) 42 #define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10) 43 #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9) 44 #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8) 45 #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7) 46 #define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6) 47 #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5) 48 #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4) 49 #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3) 50 #define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2) 51 #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1) 52 #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0) 53 54 #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29))) 55 #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \ 56 BIT((x + 29))) 57 #define SPEAR1310_PCIE_CFG_VAL(x) \ 58 (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \ 59 SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \ 60 SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \ 61 SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \ 62 SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT) 63 #define SPEAR1310_SATA_CFG_VAL(x) \ 64 (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \ 65 SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \ 66 SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \ 67 SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \ 68 SPEAR1310_SATA##x##_CFG_TX_CLK_EN) 69 70 #define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8 71 #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31) 72 #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28) 73 #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16) 74 #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15) 75 #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12) 76 #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0) 77 #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF) 78 #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16) 79 #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \ 80 (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \ 81 SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \ 82 SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \ 83 SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \ 84 SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \ 85 SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60)) 86 #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ 87 (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120)) 88 #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \ 89 (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \ 90 SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \ 91 SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \ 92 SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25)) 93 94 #define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC 95 96 enum spear1310_miphy_mode { 97 SATA, 98 PCIE, 99 }; 100 101 struct spear1310_miphy_priv { 102 /* instance id of this phy */ 103 u32 id; 104 /* phy mode: 0 for SATA 1 for PCIe */ 105 enum spear1310_miphy_mode mode; 106 /* regmap for any soc specific misc registers */ 107 struct regmap *misc; 108 /* phy struct pointer */ 109 struct phy *phy; 110 }; 111 112 static int spear1310_miphy_pcie_init(struct spear1310_miphy_priv *priv) 113 { 114 u32 val; 115 116 regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1, 117 SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 118 SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE); 119 120 switch (priv->id) { 121 case 0: 122 val = SPEAR1310_PCIE_CFG_VAL(0); 123 break; 124 case 1: 125 val = SPEAR1310_PCIE_CFG_VAL(1); 126 break; 127 case 2: 128 val = SPEAR1310_PCIE_CFG_VAL(2); 129 break; 130 default: 131 return -EINVAL; 132 } 133 134 regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG, 135 SPEAR1310_PCIE_CFG_MASK(priv->id), val); 136 137 return 0; 138 } 139 140 static int spear1310_miphy_pcie_exit(struct spear1310_miphy_priv *priv) 141 { 142 regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG, 143 SPEAR1310_PCIE_CFG_MASK(priv->id), 0); 144 145 regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1, 146 SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0); 147 148 return 0; 149 } 150 151 static int spear1310_miphy_init(struct phy *phy) 152 { 153 struct spear1310_miphy_priv *priv = phy_get_drvdata(phy); 154 int ret = 0; 155 156 if (priv->mode == PCIE) 157 ret = spear1310_miphy_pcie_init(priv); 158 159 return ret; 160 } 161 162 static int spear1310_miphy_exit(struct phy *phy) 163 { 164 struct spear1310_miphy_priv *priv = phy_get_drvdata(phy); 165 int ret = 0; 166 167 if (priv->mode == PCIE) 168 ret = spear1310_miphy_pcie_exit(priv); 169 170 return ret; 171 } 172 173 static const struct of_device_id spear1310_miphy_of_match[] = { 174 { .compatible = "st,spear1310-miphy" }, 175 { }, 176 }; 177 MODULE_DEVICE_TABLE(of, spear1310_miphy_of_match); 178 179 static const struct phy_ops spear1310_miphy_ops = { 180 .init = spear1310_miphy_init, 181 .exit = spear1310_miphy_exit, 182 .owner = THIS_MODULE, 183 }; 184 185 static struct phy *spear1310_miphy_xlate(struct device *dev, 186 struct of_phandle_args *args) 187 { 188 struct spear1310_miphy_priv *priv = dev_get_drvdata(dev); 189 190 if (args->args_count < 1) { 191 dev_err(dev, "DT did not pass correct no of args\n"); 192 return ERR_PTR(-ENODEV); 193 } 194 195 priv->mode = args->args[0]; 196 197 if (priv->mode != SATA && priv->mode != PCIE) { 198 dev_err(dev, "DT did not pass correct phy mode\n"); 199 return ERR_PTR(-ENODEV); 200 } 201 202 return priv->phy; 203 } 204 205 static int spear1310_miphy_probe(struct platform_device *pdev) 206 { 207 struct device *dev = &pdev->dev; 208 struct spear1310_miphy_priv *priv; 209 struct phy_provider *phy_provider; 210 211 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 212 if (!priv) 213 return -ENOMEM; 214 215 priv->misc = 216 syscon_regmap_lookup_by_phandle(dev->of_node, "misc"); 217 if (IS_ERR(priv->misc)) { 218 dev_err(dev, "failed to find misc regmap\n"); 219 return PTR_ERR(priv->misc); 220 } 221 222 if (of_property_read_u32(dev->of_node, "phy-id", &priv->id)) { 223 dev_err(dev, "failed to find phy id\n"); 224 return -EINVAL; 225 } 226 227 priv->phy = devm_phy_create(dev, NULL, &spear1310_miphy_ops); 228 if (IS_ERR(priv->phy)) { 229 dev_err(dev, "failed to create SATA PCIe PHY\n"); 230 return PTR_ERR(priv->phy); 231 } 232 233 dev_set_drvdata(dev, priv); 234 phy_set_drvdata(priv->phy, priv); 235 236 phy_provider = 237 devm_of_phy_provider_register(dev, spear1310_miphy_xlate); 238 if (IS_ERR(phy_provider)) { 239 dev_err(dev, "failed to register phy provider\n"); 240 return PTR_ERR(phy_provider); 241 } 242 243 return 0; 244 } 245 246 static struct platform_driver spear1310_miphy_driver = { 247 .probe = spear1310_miphy_probe, 248 .driver = { 249 .name = "spear1310-miphy", 250 .of_match_table = spear1310_miphy_of_match, 251 }, 252 }; 253 254 module_platform_driver(spear1310_miphy_driver); 255 256 MODULE_DESCRIPTION("ST SPEAR1310-MIPHY driver"); 257 MODULE_AUTHOR("Pratyush Anand <pratyush.anand@gmail.com>"); 258 MODULE_LICENSE("GPL v2"); 259