1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bitfield.h> 4 #include <linux/cleanup.h> 5 #include <linux/io.h> 6 #include <linux/iopoll.h> 7 #include <linux/module.h> 8 #include <linux/regmap.h> 9 #include <linux/usb.h> 10 11 #include <dt-bindings/phy/phy.h> 12 13 #include "phy-k3-common.h" 14 15 /* PHY Registers */ 16 #define PHY_VERSION 0x0 17 18 #define PHY_RESET_CFG 0x04 19 20 #define PHY_RESET_RXBUF_RST BIT(0) 21 #define PHY_RESET_SOFT_RST_PCS BIT(1) 22 #define PHY_RESET_SOFT_RST_AHB BIT(2) 23 #define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) 24 25 #define PHY_CLK_CFG 0x08 26 27 #define PHY_CLK_PLL_READY BIT(0) 28 #define PHY_CLK_TXCLK_INV BIT(2) 29 #define PHY_CLK_RXCLK_EN BIT(3) 30 #define PHY_CLK_TXCLK_EN BIT(4) 31 #define PHY_CLK_PCLK_EN BIT(5) 32 #define PHY_CLK_PIPE_PCLK_EN BIT(6) 33 #define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) 34 #define PHY_CLK_REFCLK_24M 2 35 #define PHY_CLK_SW_INIT_DONE BIT(11) 36 #define PHY_CLK_PU_SSC_OUT BIT(23) 37 38 #define PHY_MODE_CFG 0x0C 39 40 #define PHY_MODE_PCIE_INT_EN BIT(0) 41 #define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) 42 #define PHY_MODE_LFPS_TPERIOD_USB 3 43 44 #define PHY_PU_SEL 0x40 45 46 #define PHY_PU_CFG_STATUS BIT(9) 47 #define PHY_PU_OVRD_STATUS BIT(10) 48 49 #define PHY_PU_CK_REG 0x54 50 51 #define PHY_PU_REFCLK_100 BIT(25) 52 53 #define PHY_PLL_REG1 0x58 54 55 #define PHY_PLL_FREF_SEL GENMASK(15, 13) 56 #define PHY_PLL_FREF_24M 0x1 57 #define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) 58 #define PHY_PLL_SSC_5000PPM 0xa 59 #define PHY_PLL_SSC_MODE GENMASK(29, 28) 60 #define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 61 #define PHY_PLL_SSC_MODE_UP_SPREAD 1 62 #define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 63 #define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 64 65 #define PHY_PLL_REG2 0x5c 66 67 #define PHY_PLL_SEL_REF100 BIT(21) 68 69 /* PHY RX Register Definitions */ 70 #define PHY_RX_REG_A 0x60 71 72 #define PHY_RX_REG0_MASK GENMASK(7, 0) 73 #define PHY_RX_REG1_MASK GENMASK(15, 8) 74 #define PHY_RX_REG2_MASK GENMASK(23, 16) 75 #define PHY_RX_REG3_MASK GENMASK(31, 24) 76 77 #define PHY_RX_REG0_RLOAD BIT(4) 78 #define PHY_RX_REG1_RTERM GENMASK(11, 8) 79 #define PHY_RX_REG1_RC_CALI GENMASK(15, 12) 80 #define PHY_RX_REG2_CSEL GENMASK(19, 16) 81 #define PHY_RX_REG2_FORCE_CSEL BIT(20) 82 #define PHY_RX_REG2_PSEL GENMASK(23, 21) 83 #define PHY_RX_REG3_I_LOAD GENMASK(26, 24) 84 #define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) 85 #define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) 86 #define PHY_RX_REG3_RDEG1 GENMASK(31, 30) 87 88 #define PHY_RX_REG_B 0x64 89 90 #define PHY_RX_REG4_MASK GENMASK(7, 0) 91 #define PHY_RX_REG5_MASK GENMASK(15, 8) 92 #define PHY_RX_REG6_MASK GENMASK(23, 16) 93 94 #define PHY_RX_REGB_MASK GENMASK(23, 0) 95 96 #define PHY_RX_REG4_RDEG2 GENMASK(2, 1) 97 #define PHY_RX_REG4_ENVOS BIT(4) 98 #define PHY_RX_REG4_RTERM_SEL BIT(5) 99 #define PHY_RX_REG4_MANUAL_CFG BIT(7) 100 #define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) 101 #define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) 102 #define PHY_RX_REG6_H1_REG GENMASK(19, 16) 103 #define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) 104 #define PHY_RX_REG6_BYPASS_ADPT BIT(22) 105 106 #define PHY_ADPT_CFG0 0x140 107 #define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) 108 #define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) 109 110 #define PHY_RXEQ_TIME 0xb4 111 #define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) 112 #define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) 113 #define PHY_RXEQ_TIME_AMP_SOC_650M 0 114 #define PHY_RXEQ_TIME_AMP_SOC_800M 1 115 #define PHY_RXEQ_TIME_AMP_SOC_870M 2 116 #define PHY_RXEQ_TIME_AMP_SOC_900M 3 117 #define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) 118 119 #define PCIE_PU_ADDR_CLK_CFG 0x0008 120 #define PHY_CLK_PLL_READY BIT(0) 121 #define PCIE_INITAL_TIMER GENMASK(6, 3) 122 #define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) 123 #define CFG_SW_PHY_INIT_DONE BIT(11) 124 125 /* Lane RX/TX configuration (per‑lane, at lane_base) */ 126 #define PCIE_RX_REG1 0x050 127 #define PCIE_RX_REFCLK_MODE GENMASK(1, 0) 128 #define PCIE_RX_REFCLK_MODE_DRIVER 1 129 #define PCIE_RX_SEL_TRI_CODE BIT(2) 130 #define PCIE_RX_LEGACY GENMASK(15, 8) 131 #define PCIE_RX_LEGACY_DEFAULT 0x65 132 133 #define PCIE_TX_REG1 0x064 134 135 #define PCIE_PLL_TIMEOUT 500000 136 #define PCIE_POLL_DELAY 500 137 138 static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) 139 { 140 struct phy *phy = lg->phy; 141 u32 val, tmp; 142 int ret; 143 144 /* Do not wait CDR lock before sampling data */ 145 val = readl(base + PHY_RESET_CFG); 146 val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); 147 writel(val, base + PHY_RESET_CFG); 148 149 /* Power down 100MHz refclk buffer */ 150 val = readl(base + PHY_PU_CK_REG); 151 val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); 152 writel(val, base + PHY_PU_CK_REG); 153 154 /* Program PLL REG1 configure the SSC */ 155 val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | 156 FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | 157 FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); 158 writel(val, base + PHY_PLL_REG1); 159 160 /* Un-select 100MHz PLL reference */ 161 val = readl(base + PHY_PLL_REG2); 162 val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); 163 writel(val, base + PHY_PLL_REG2); 164 165 /* USB LFPS period configuration */ 166 val = readl(base + PHY_MODE_CFG); 167 val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); 168 writel(val, base + PHY_MODE_CFG); 169 170 /* Force AFE adaptation reset */ 171 val = readl(base + PHY_ADPT_CFG0); 172 val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; 173 writel(val, base + PHY_ADPT_CFG0); 174 175 /* Override driver amplitude value to 900m */ 176 val = readl(base + PHY_RXEQ_TIME); 177 val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; 178 val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); 179 writel(val, base + PHY_RXEQ_TIME); 180 181 /* Configure RX parameters */ 182 val = PHY_RX_REG0_RLOAD | 183 FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | 184 FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | 185 FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | 186 PHY_RX_REG2_FORCE_CSEL | 187 FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | 188 FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | 189 PHY_RX_REG3_SEL_CBOOST_CODE | 190 FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | 191 FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); 192 writel(val, base + PHY_RX_REG_A); 193 194 val = readl(base + PHY_RX_REG_B); 195 tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | 196 PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | 197 FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | 198 FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | 199 FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | 200 FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); 201 val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); 202 writel(val, base + PHY_RX_REG_B); 203 204 /* 205 * Inform PHY that all PLL-related configuration is done. 206 * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. 207 */ 208 val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | 209 FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | 210 PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | 211 PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; 212 writel(val, base + PHY_CLK_CFG); 213 214 ret = readl_poll_timeout(base + PHY_CLK_CFG, val, 215 (val & PHY_CLK_PLL_READY), 216 PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); 217 if (ret) { 218 dev_err(&phy->dev, "PHY PLL polling timeout\n"); 219 return ret; 220 } 221 222 return 0; 223 } 224 225 static int k3_usb3phy_init(struct phy *phy) 226 { 227 struct k3_lane_group *lg = phy_get_drvdata(phy); 228 int ret, i; 229 230 for (i = 0; i < lg->data->lanes; i++) { 231 ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); 232 if (ret < 0) 233 return ret; 234 } 235 236 return 0; 237 } 238 239 const struct phy_ops k3_usb3_phy_ops = { 240 .init = k3_usb3phy_init, 241 .owner = THIS_MODULE, 242 }; 243 EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); 244 245 static int k3_pcie_phy_init(struct phy *phy) 246 { 247 struct k3_lane_group *lg = phy_get_drvdata(phy); 248 void __iomem *phy_base = lg->base + lg->data->offsets[0]; 249 u32 val; 250 int ret; 251 int i; 252 253 val = readl(phy_base + PHY_PLL_REG1); 254 val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); 255 writel(val, phy_base + PHY_PLL_REG1); 256 257 val = readl(phy_base + PHY_PLL_REG2); 258 val = u32_replace_bits(val, 0, BIT(21)); 259 writel(val, phy_base + PHY_PLL_REG2); 260 261 for (i = 0; i < lg->data->lanes; i++) { 262 void __iomem *lane_base = lg->base + lg->data->offsets[i]; 263 264 val = readl(lane_base + PCIE_RX_REG1); 265 val = u32_replace_bits(val, 0, 0x3); 266 writel(val, lane_base + PCIE_RX_REG1); 267 } 268 269 val = readl(phy_base + PHY_PLL_REG2); 270 val |= BIT(20); 271 writel(val, phy_base + PHY_PLL_REG2); 272 273 /* The write is needed as clock requires renegotiation */ 274 val = FIELD_PREP(PCIE_RX_REFCLK_MODE, PCIE_RX_REFCLK_MODE_DRIVER) | 275 PCIE_RX_SEL_TRI_CODE | 276 FIELD_PREP(PCIE_RX_LEGACY, PCIE_RX_LEGACY_DEFAULT); 277 writel(val, phy_base + PCIE_RX_REG1); 278 279 /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ 280 val = readl(phy_base + PHY_PLL_REG1); 281 val = u32_replace_bits(val, 0, GENMASK(27, 24)); 282 writel(val, phy_base + PHY_PLL_REG1); 283 284 for (i = 0; i < lg->data->lanes; i++) { 285 void __iomem *lane_base = lg->base + lg->data->offsets[i]; 286 287 /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ 288 val = readl(lane_base + PHY_PU_SEL); 289 val = u32_replace_bits(val, 1, BIT(13)); 290 writel(val, lane_base + PHY_PU_SEL); 291 292 /* disable en_sample_data_after_cdr_locked */ 293 val = readl(lane_base + PHY_RESET_CFG); 294 val = u32_replace_bits(val, 0, BIT(6)); 295 writel(val, lane_base + PHY_RESET_CFG); 296 297 /* Dynamic Lock */ 298 val = readl(lane_base + PHY_MODE_CFG); 299 val = u32_replace_bits(val, 1, BIT(2)); 300 writel(val, lane_base + PHY_MODE_CFG); 301 302 val = FIELD_PREP(PHY_RX_REG0_MASK, 0x10) | 303 FIELD_PREP(PHY_RX_REG1_MASK, 0x78) | 304 FIELD_PREP(PHY_RX_REG2_MASK, 0x98) | 305 FIELD_PREP(PHY_RX_REG3_MASK, 0xdf); 306 writel(val, lane_base + PHY_RX_REG_A); 307 308 val = readl(lane_base + PHY_RX_REG_B); 309 val &= ~PHY_RX_REGB_MASK; 310 val |= FIELD_PREP(PHY_RX_REG4_MASK, 0xb4) | 311 FIELD_PREP(PHY_RX_REG5_MASK, 0x88) | 312 FIELD_PREP(PHY_RX_REG6_MASK, 0x28); 313 writel(val, lane_base + PHY_RX_REG_B); 314 315 /* Set init done */ 316 val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); 317 val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); 318 writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); 319 } 320 321 ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, 322 (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, 323 PCIE_PLL_TIMEOUT); 324 if (ret) { 325 dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); 326 return ret; 327 } 328 329 return 0; 330 } 331 332 const struct phy_ops k3_pcie_phy_ops = { 333 .init = k3_pcie_phy_init, 334 .owner = THIS_MODULE, 335 }; 336 EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); 337 338 /* PHY rcal init requires APB_SPARE regmap access */ 339 340 #define APB_SPARE_PU_CAL 0x178 341 #define PU_CAL BIT(17) 342 343 #define APB_SPARE_RCAL_HSIO 0x17c 344 #define APB_SPARE_PU_CAL_DONE BIT(8) 345 #define RCAL_OVRD_PTRIM GENMASK(23, 20) 346 #define RCAL_OVRD_NTRIM GENMASK(27, 24) 347 #define RCAL_OVRD_PTRIM_EN BIT(28) 348 #define RCAL_OVRD_NTRIM_EN BIT(29) 349 #define RCAL_OVRD_STABLE_VAL BIT(30) 350 #define RCAL_OVRD_STABLE_EN BIT(31) 351 352 #define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) 353 #define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) 354 355 #define PU_CAL_TIMEOUT 2000000 356 357 static DEFINE_MUTEX(calibrate_lock); 358 359 int k3_phy_calibrate(struct regmap *apb_spare) 360 { 361 unsigned int val = 0; 362 int ret; 363 364 guard(mutex)(&calibrate_lock); 365 366 regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); 367 if (val & APB_SPARE_PU_CAL_DONE) 368 return 0; 369 370 regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, 371 PU_CAL); 372 373 ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, 374 val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, 375 PU_CAL_TIMEOUT); 376 377 if (ret) 378 regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, 379 RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | 380 RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, 381 RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | 382 FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | 383 FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | 384 RCAL_OVRD_STABLE_EN); 385 386 return 0; 387 } 388 EXPORT_SYMBOL_GPL(k3_phy_calibrate); 389 390 MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); 391 MODULE_LICENSE("GPL"); 392