1c6d9b132SKunihiko Hayashi // SPDX-License-Identifier: GPL-2.0 2c6d9b132SKunihiko Hayashi /* 3c6d9b132SKunihiko Hayashi * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller 4c6d9b132SKunihiko Hayashi * Copyright 2018, Socionext Inc. 5c6d9b132SKunihiko Hayashi * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 6c6d9b132SKunihiko Hayashi */ 7c6d9b132SKunihiko Hayashi 8c6d9b132SKunihiko Hayashi #include <linux/bitops.h> 9c6d9b132SKunihiko Hayashi #include <linux/bitfield.h> 10c6d9b132SKunihiko Hayashi #include <linux/clk.h> 11c6d9b132SKunihiko Hayashi #include <linux/iopoll.h> 12c6d9b132SKunihiko Hayashi #include <linux/mfd/syscon.h> 13c6d9b132SKunihiko Hayashi #include <linux/module.h> 14*7559e757SRob Herring #include <linux/of.h> 15c6d9b132SKunihiko Hayashi #include <linux/phy/phy.h> 16c6d9b132SKunihiko Hayashi #include <linux/platform_device.h> 17c6d9b132SKunihiko Hayashi #include <linux/regmap.h> 18c6d9b132SKunihiko Hayashi #include <linux/reset.h> 19c6d9b132SKunihiko Hayashi #include <linux/resource.h> 20c6d9b132SKunihiko Hayashi 21c6d9b132SKunihiko Hayashi /* PHY */ 2204de8fa2SKunihiko Hayashi #define PCL_PHY_CLKCTRL 0x0000 2304de8fa2SKunihiko Hayashi #define PORT_SEL_MASK GENMASK(11, 9) 2404de8fa2SKunihiko Hayashi #define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1) 2504de8fa2SKunihiko Hayashi 26c6d9b132SKunihiko Hayashi #define PCL_PHY_TEST_I 0x2000 27c6d9b132SKunihiko Hayashi #define TESTI_DAT_MASK GENMASK(13, 6) 28c6d9b132SKunihiko Hayashi #define TESTI_ADR_MASK GENMASK(5, 1) 29c6d9b132SKunihiko Hayashi #define TESTI_WR_EN BIT(0) 307f1abed4SKunihiko Hayashi #define TESTIO_PHY_SHIFT 16 31c6d9b132SKunihiko Hayashi 324a90bbb4SKunihiko Hayashi #define PCL_PHY_TEST_O 0x2004 334a90bbb4SKunihiko Hayashi #define TESTO_DAT_MASK GENMASK(7, 0) 344a90bbb4SKunihiko Hayashi 35c6d9b132SKunihiko Hayashi #define PCL_PHY_RESET 0x200c 36c6d9b132SKunihiko Hayashi #define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */ 37c6d9b132SKunihiko Hayashi #define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */ 38c6d9b132SKunihiko Hayashi 39c6d9b132SKunihiko Hayashi /* SG */ 40c6d9b132SKunihiko Hayashi #define SG_USBPCIESEL 0x590 41c6d9b132SKunihiko Hayashi #define SG_USBPCIESEL_PCIE BIT(0) 42c6d9b132SKunihiko Hayashi 431c1597c8SKunihiko Hayashi /* SC */ 441c1597c8SKunihiko Hayashi #define SC_US3SRCSEL 0x2244 451c1597c8SKunihiko Hayashi #define SC_US3SRCSEL_2LANE GENMASK(9, 8) 461c1597c8SKunihiko Hayashi 47c6d9b132SKunihiko Hayashi #define PCL_PHY_R00 0 48c6d9b132SKunihiko Hayashi #define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */ 49c6d9b132SKunihiko Hayashi #define PCL_PHY_R06 6 50c6d9b132SKunihiko Hayashi #define RX_EQ_ADJ GENMASK(5, 0) /* EQ adjustment value */ 51c6d9b132SKunihiko Hayashi #define RX_EQ_ADJ_VAL 0 52c6d9b132SKunihiko Hayashi #define PCL_PHY_R26 26 53c6d9b132SKunihiko Hayashi #define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */ 54c6d9b132SKunihiko Hayashi #define VCO_CTRL_INIT_VAL 5 5525bba42fSKunihiko Hayashi #define PCL_PHY_R28 28 5625bba42fSKunihiko Hayashi #define VCOPLL_CLMP GENMASK(3, 2) /* Tx VCOPLL clamp mode */ 5725bba42fSKunihiko Hayashi #define VCOPLL_CLMP_VAL 0 58c6d9b132SKunihiko Hayashi 59c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv { 60c6d9b132SKunihiko Hayashi void __iomem *base; 61c6d9b132SKunihiko Hayashi struct device *dev; 6204de8fa2SKunihiko Hayashi struct clk *clk, *clk_gio; 6304de8fa2SKunihiko Hayashi struct reset_control *rst, *rst_gio; 64c6d9b132SKunihiko Hayashi const struct uniphier_pciephy_soc_data *data; 65c6d9b132SKunihiko Hayashi }; 66c6d9b132SKunihiko Hayashi 67c6d9b132SKunihiko Hayashi struct uniphier_pciephy_soc_data { 6804de8fa2SKunihiko Hayashi bool is_legacy; 697f1abed4SKunihiko Hayashi bool is_dual_phy; 706861781aSKunihiko Hayashi void (*set_phymode)(struct regmap *regmap); 71c6d9b132SKunihiko Hayashi }; 72c6d9b132SKunihiko Hayashi 73c6d9b132SKunihiko Hayashi static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv, 747f1abed4SKunihiko Hayashi int id, u32 data) 75c6d9b132SKunihiko Hayashi { 767f1abed4SKunihiko Hayashi if (id) 777f1abed4SKunihiko Hayashi data <<= TESTIO_PHY_SHIFT; 787f1abed4SKunihiko Hayashi 79c6d9b132SKunihiko Hayashi /* need to read TESTO twice after accessing TESTI */ 80c6d9b132SKunihiko Hayashi writel(data, priv->base + PCL_PHY_TEST_I); 81c6d9b132SKunihiko Hayashi readl(priv->base + PCL_PHY_TEST_O); 82c6d9b132SKunihiko Hayashi readl(priv->base + PCL_PHY_TEST_O); 83c6d9b132SKunihiko Hayashi } 84c6d9b132SKunihiko Hayashi 857f1abed4SKunihiko Hayashi static u32 uniphier_pciephy_testio_read(struct uniphier_pciephy_priv *priv, int id) 867f1abed4SKunihiko Hayashi { 877f1abed4SKunihiko Hayashi u32 val = readl(priv->base + PCL_PHY_TEST_O); 887f1abed4SKunihiko Hayashi 897f1abed4SKunihiko Hayashi if (id) 907f1abed4SKunihiko Hayashi val >>= TESTIO_PHY_SHIFT; 917f1abed4SKunihiko Hayashi 927f1abed4SKunihiko Hayashi return val & TESTO_DAT_MASK; 937f1abed4SKunihiko Hayashi } 947f1abed4SKunihiko Hayashi 95c6d9b132SKunihiko Hayashi static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv, 967f1abed4SKunihiko Hayashi int id, u32 reg, u32 mask, u32 param) 97c6d9b132SKunihiko Hayashi { 98c6d9b132SKunihiko Hayashi u32 val; 99c6d9b132SKunihiko Hayashi 100c6d9b132SKunihiko Hayashi /* read previous data */ 101c6d9b132SKunihiko Hayashi val = FIELD_PREP(TESTI_DAT_MASK, 1); 102c6d9b132SKunihiko Hayashi val |= FIELD_PREP(TESTI_ADR_MASK, reg); 1037f1abed4SKunihiko Hayashi uniphier_pciephy_testio_write(priv, id, val); 1047f1abed4SKunihiko Hayashi val = uniphier_pciephy_testio_read(priv, id); 105c6d9b132SKunihiko Hayashi 106c6d9b132SKunihiko Hayashi /* update value */ 1074a90bbb4SKunihiko Hayashi val &= ~mask; 1084a90bbb4SKunihiko Hayashi val |= mask & param; 1094a90bbb4SKunihiko Hayashi val = FIELD_PREP(TESTI_DAT_MASK, val); 110c6d9b132SKunihiko Hayashi val |= FIELD_PREP(TESTI_ADR_MASK, reg); 1117f1abed4SKunihiko Hayashi uniphier_pciephy_testio_write(priv, id, val); 1127f1abed4SKunihiko Hayashi uniphier_pciephy_testio_write(priv, id, val | TESTI_WR_EN); 1137f1abed4SKunihiko Hayashi uniphier_pciephy_testio_write(priv, id, val); 114c6d9b132SKunihiko Hayashi 115c6d9b132SKunihiko Hayashi /* read current data as dummy */ 116c6d9b132SKunihiko Hayashi val = FIELD_PREP(TESTI_DAT_MASK, 1); 117c6d9b132SKunihiko Hayashi val |= FIELD_PREP(TESTI_ADR_MASK, reg); 1187f1abed4SKunihiko Hayashi uniphier_pciephy_testio_write(priv, id, val); 1197f1abed4SKunihiko Hayashi uniphier_pciephy_testio_read(priv, id); 120c6d9b132SKunihiko Hayashi } 121c6d9b132SKunihiko Hayashi 122c6d9b132SKunihiko Hayashi static void uniphier_pciephy_assert(struct uniphier_pciephy_priv *priv) 123c6d9b132SKunihiko Hayashi { 124c6d9b132SKunihiko Hayashi u32 val; 125c6d9b132SKunihiko Hayashi 126c6d9b132SKunihiko Hayashi val = readl(priv->base + PCL_PHY_RESET); 127c6d9b132SKunihiko Hayashi val &= ~PCL_PHY_RESET_N; 128c6d9b132SKunihiko Hayashi val |= PCL_PHY_RESET_N_MNMODE; 129c6d9b132SKunihiko Hayashi writel(val, priv->base + PCL_PHY_RESET); 130c6d9b132SKunihiko Hayashi } 131c6d9b132SKunihiko Hayashi 132c6d9b132SKunihiko Hayashi static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv) 133c6d9b132SKunihiko Hayashi { 134c6d9b132SKunihiko Hayashi u32 val; 135c6d9b132SKunihiko Hayashi 136c6d9b132SKunihiko Hayashi val = readl(priv->base + PCL_PHY_RESET); 137c6d9b132SKunihiko Hayashi val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N; 138c6d9b132SKunihiko Hayashi writel(val, priv->base + PCL_PHY_RESET); 139c6d9b132SKunihiko Hayashi } 140c6d9b132SKunihiko Hayashi 141c6d9b132SKunihiko Hayashi static int uniphier_pciephy_init(struct phy *phy) 142c6d9b132SKunihiko Hayashi { 143c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); 14404de8fa2SKunihiko Hayashi u32 val; 1457f1abed4SKunihiko Hayashi int ret, id; 146c6d9b132SKunihiko Hayashi 147c6d9b132SKunihiko Hayashi ret = clk_prepare_enable(priv->clk); 148c6d9b132SKunihiko Hayashi if (ret) 149c6d9b132SKunihiko Hayashi return ret; 150c6d9b132SKunihiko Hayashi 15104de8fa2SKunihiko Hayashi ret = clk_prepare_enable(priv->clk_gio); 152c6d9b132SKunihiko Hayashi if (ret) 153c6d9b132SKunihiko Hayashi goto out_clk_disable; 154c6d9b132SKunihiko Hayashi 15504de8fa2SKunihiko Hayashi ret = reset_control_deassert(priv->rst); 15604de8fa2SKunihiko Hayashi if (ret) 15704de8fa2SKunihiko Hayashi goto out_clk_gio_disable; 15804de8fa2SKunihiko Hayashi 15904de8fa2SKunihiko Hayashi ret = reset_control_deassert(priv->rst_gio); 16004de8fa2SKunihiko Hayashi if (ret) 16104de8fa2SKunihiko Hayashi goto out_rst_assert; 16204de8fa2SKunihiko Hayashi 16304de8fa2SKunihiko Hayashi /* support only 1 port */ 16404de8fa2SKunihiko Hayashi val = readl(priv->base + PCL_PHY_CLKCTRL); 16504de8fa2SKunihiko Hayashi val &= ~PORT_SEL_MASK; 16604de8fa2SKunihiko Hayashi val |= PORT_SEL_1; 16704de8fa2SKunihiko Hayashi writel(val, priv->base + PCL_PHY_CLKCTRL); 16804de8fa2SKunihiko Hayashi 16904de8fa2SKunihiko Hayashi /* legacy controller doesn't have phy_reset and parameters */ 17004de8fa2SKunihiko Hayashi if (priv->data->is_legacy) 17104de8fa2SKunihiko Hayashi return 0; 17204de8fa2SKunihiko Hayashi 1737f1abed4SKunihiko Hayashi for (id = 0; id < (priv->data->is_dual_phy ? 2 : 1); id++) { 1747f1abed4SKunihiko Hayashi uniphier_pciephy_set_param(priv, id, PCL_PHY_R00, 175c6d9b132SKunihiko Hayashi RX_EQ_ADJ_EN, RX_EQ_ADJ_EN); 1767f1abed4SKunihiko Hayashi uniphier_pciephy_set_param(priv, id, PCL_PHY_R06, RX_EQ_ADJ, 177c6d9b132SKunihiko Hayashi FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL)); 1787f1abed4SKunihiko Hayashi uniphier_pciephy_set_param(priv, id, PCL_PHY_R26, VCO_CTRL, 179c6d9b132SKunihiko Hayashi FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL)); 1807f1abed4SKunihiko Hayashi uniphier_pciephy_set_param(priv, id, PCL_PHY_R28, VCOPLL_CLMP, 18125bba42fSKunihiko Hayashi FIELD_PREP(VCOPLL_CLMP, VCOPLL_CLMP_VAL)); 1827f1abed4SKunihiko Hayashi } 183c6d9b132SKunihiko Hayashi usleep_range(1, 10); 184c6d9b132SKunihiko Hayashi 185c6d9b132SKunihiko Hayashi uniphier_pciephy_deassert(priv); 186c6d9b132SKunihiko Hayashi usleep_range(1, 10); 187c6d9b132SKunihiko Hayashi 188c6d9b132SKunihiko Hayashi return 0; 189c6d9b132SKunihiko Hayashi 19004de8fa2SKunihiko Hayashi out_rst_assert: 19104de8fa2SKunihiko Hayashi reset_control_assert(priv->rst); 19204de8fa2SKunihiko Hayashi out_clk_gio_disable: 19304de8fa2SKunihiko Hayashi clk_disable_unprepare(priv->clk_gio); 194c6d9b132SKunihiko Hayashi out_clk_disable: 195c6d9b132SKunihiko Hayashi clk_disable_unprepare(priv->clk); 196c6d9b132SKunihiko Hayashi 197c6d9b132SKunihiko Hayashi return ret; 198c6d9b132SKunihiko Hayashi } 199c6d9b132SKunihiko Hayashi 200c6d9b132SKunihiko Hayashi static int uniphier_pciephy_exit(struct phy *phy) 201c6d9b132SKunihiko Hayashi { 202c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); 203c6d9b132SKunihiko Hayashi 20404de8fa2SKunihiko Hayashi if (!priv->data->is_legacy) 205c6d9b132SKunihiko Hayashi uniphier_pciephy_assert(priv); 20604de8fa2SKunihiko Hayashi reset_control_assert(priv->rst_gio); 207c6d9b132SKunihiko Hayashi reset_control_assert(priv->rst); 20804de8fa2SKunihiko Hayashi clk_disable_unprepare(priv->clk_gio); 209c6d9b132SKunihiko Hayashi clk_disable_unprepare(priv->clk); 210c6d9b132SKunihiko Hayashi 211c6d9b132SKunihiko Hayashi return 0; 212c6d9b132SKunihiko Hayashi } 213c6d9b132SKunihiko Hayashi 214c6d9b132SKunihiko Hayashi static const struct phy_ops uniphier_pciephy_ops = { 215c6d9b132SKunihiko Hayashi .init = uniphier_pciephy_init, 216c6d9b132SKunihiko Hayashi .exit = uniphier_pciephy_exit, 217c6d9b132SKunihiko Hayashi .owner = THIS_MODULE, 218c6d9b132SKunihiko Hayashi }; 219c6d9b132SKunihiko Hayashi 220c6d9b132SKunihiko Hayashi static int uniphier_pciephy_probe(struct platform_device *pdev) 221c6d9b132SKunihiko Hayashi { 222c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv *priv; 223c6d9b132SKunihiko Hayashi struct phy_provider *phy_provider; 224c6d9b132SKunihiko Hayashi struct device *dev = &pdev->dev; 225c6d9b132SKunihiko Hayashi struct regmap *regmap; 226c6d9b132SKunihiko Hayashi struct phy *phy; 227c6d9b132SKunihiko Hayashi 228c6d9b132SKunihiko Hayashi priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 229c6d9b132SKunihiko Hayashi if (!priv) 230c6d9b132SKunihiko Hayashi return -ENOMEM; 231c6d9b132SKunihiko Hayashi 232c6d9b132SKunihiko Hayashi priv->data = of_device_get_match_data(dev); 233c6d9b132SKunihiko Hayashi if (WARN_ON(!priv->data)) 234c6d9b132SKunihiko Hayashi return -EINVAL; 235c6d9b132SKunihiko Hayashi 236c6d9b132SKunihiko Hayashi priv->dev = dev; 237c6d9b132SKunihiko Hayashi 23840d76346SKunihiko Hayashi priv->base = devm_platform_ioremap_resource(pdev, 0); 239c6d9b132SKunihiko Hayashi if (IS_ERR(priv->base)) 240c6d9b132SKunihiko Hayashi return PTR_ERR(priv->base); 241c6d9b132SKunihiko Hayashi 24204de8fa2SKunihiko Hayashi if (priv->data->is_legacy) { 24304de8fa2SKunihiko Hayashi priv->clk_gio = devm_clk_get(dev, "gio"); 24404de8fa2SKunihiko Hayashi if (IS_ERR(priv->clk_gio)) 24504de8fa2SKunihiko Hayashi return PTR_ERR(priv->clk_gio); 24604de8fa2SKunihiko Hayashi 24704de8fa2SKunihiko Hayashi priv->rst_gio = 24804de8fa2SKunihiko Hayashi devm_reset_control_get_shared(dev, "gio"); 24904de8fa2SKunihiko Hayashi if (IS_ERR(priv->rst_gio)) 25004de8fa2SKunihiko Hayashi return PTR_ERR(priv->rst_gio); 25104de8fa2SKunihiko Hayashi 25204de8fa2SKunihiko Hayashi priv->clk = devm_clk_get(dev, "link"); 25304de8fa2SKunihiko Hayashi if (IS_ERR(priv->clk)) 25404de8fa2SKunihiko Hayashi return PTR_ERR(priv->clk); 25504de8fa2SKunihiko Hayashi 25604de8fa2SKunihiko Hayashi priv->rst = devm_reset_control_get_shared(dev, "link"); 25704de8fa2SKunihiko Hayashi if (IS_ERR(priv->rst)) 25804de8fa2SKunihiko Hayashi return PTR_ERR(priv->rst); 25904de8fa2SKunihiko Hayashi } else { 260c6d9b132SKunihiko Hayashi priv->clk = devm_clk_get(dev, NULL); 261c6d9b132SKunihiko Hayashi if (IS_ERR(priv->clk)) 262c6d9b132SKunihiko Hayashi return PTR_ERR(priv->clk); 263c6d9b132SKunihiko Hayashi 264c6d9b132SKunihiko Hayashi priv->rst = devm_reset_control_get_shared(dev, NULL); 265c6d9b132SKunihiko Hayashi if (IS_ERR(priv->rst)) 266c6d9b132SKunihiko Hayashi return PTR_ERR(priv->rst); 26704de8fa2SKunihiko Hayashi } 268c6d9b132SKunihiko Hayashi 269c6d9b132SKunihiko Hayashi phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops); 270c6d9b132SKunihiko Hayashi if (IS_ERR(phy)) 271c6d9b132SKunihiko Hayashi return PTR_ERR(phy); 272c6d9b132SKunihiko Hayashi 273c6d9b132SKunihiko Hayashi regmap = syscon_regmap_lookup_by_phandle(dev->of_node, 274c6d9b132SKunihiko Hayashi "socionext,syscon"); 2756861781aSKunihiko Hayashi if (!IS_ERR(regmap) && priv->data->set_phymode) 2766861781aSKunihiko Hayashi priv->data->set_phymode(regmap); 277c6d9b132SKunihiko Hayashi 278c6d9b132SKunihiko Hayashi phy_set_drvdata(phy, priv); 279c6d9b132SKunihiko Hayashi phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 280c6d9b132SKunihiko Hayashi 281c6d9b132SKunihiko Hayashi return PTR_ERR_OR_ZERO(phy_provider); 282c6d9b132SKunihiko Hayashi } 283c6d9b132SKunihiko Hayashi 2846861781aSKunihiko Hayashi static void uniphier_pciephy_ld20_setmode(struct regmap *regmap) 2856861781aSKunihiko Hayashi { 2866861781aSKunihiko Hayashi regmap_update_bits(regmap, SG_USBPCIESEL, 2876861781aSKunihiko Hayashi SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE); 2886861781aSKunihiko Hayashi } 2896861781aSKunihiko Hayashi 2901c1597c8SKunihiko Hayashi static void uniphier_pciephy_nx1_setmode(struct regmap *regmap) 2911c1597c8SKunihiko Hayashi { 2921c1597c8SKunihiko Hayashi regmap_update_bits(regmap, SC_US3SRCSEL, 2931c1597c8SKunihiko Hayashi SC_US3SRCSEL_2LANE, SC_US3SRCSEL_2LANE); 2941c1597c8SKunihiko Hayashi } 2951c1597c8SKunihiko Hayashi 29604de8fa2SKunihiko Hayashi static const struct uniphier_pciephy_soc_data uniphier_pro5_data = { 29704de8fa2SKunihiko Hayashi .is_legacy = true, 29804de8fa2SKunihiko Hayashi }; 29904de8fa2SKunihiko Hayashi 300c6d9b132SKunihiko Hayashi static const struct uniphier_pciephy_soc_data uniphier_ld20_data = { 30104de8fa2SKunihiko Hayashi .is_legacy = false, 3027f1abed4SKunihiko Hayashi .is_dual_phy = false, 3036861781aSKunihiko Hayashi .set_phymode = uniphier_pciephy_ld20_setmode, 304c6d9b132SKunihiko Hayashi }; 305c6d9b132SKunihiko Hayashi 306c6d9b132SKunihiko Hayashi static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = { 30704de8fa2SKunihiko Hayashi .is_legacy = false, 3087f1abed4SKunihiko Hayashi .is_dual_phy = false, 309c6d9b132SKunihiko Hayashi }; 310c6d9b132SKunihiko Hayashi 3111c1597c8SKunihiko Hayashi static const struct uniphier_pciephy_soc_data uniphier_nx1_data = { 3121c1597c8SKunihiko Hayashi .is_legacy = false, 3137f1abed4SKunihiko Hayashi .is_dual_phy = true, 3141c1597c8SKunihiko Hayashi .set_phymode = uniphier_pciephy_nx1_setmode, 3151c1597c8SKunihiko Hayashi }; 3161c1597c8SKunihiko Hayashi 317c6d9b132SKunihiko Hayashi static const struct of_device_id uniphier_pciephy_match[] = { 318c6d9b132SKunihiko Hayashi { 31904de8fa2SKunihiko Hayashi .compatible = "socionext,uniphier-pro5-pcie-phy", 32004de8fa2SKunihiko Hayashi .data = &uniphier_pro5_data, 32104de8fa2SKunihiko Hayashi }, 32204de8fa2SKunihiko Hayashi { 323c6d9b132SKunihiko Hayashi .compatible = "socionext,uniphier-ld20-pcie-phy", 324c6d9b132SKunihiko Hayashi .data = &uniphier_ld20_data, 325c6d9b132SKunihiko Hayashi }, 326c6d9b132SKunihiko Hayashi { 327c6d9b132SKunihiko Hayashi .compatible = "socionext,uniphier-pxs3-pcie-phy", 328c6d9b132SKunihiko Hayashi .data = &uniphier_pxs3_data, 329c6d9b132SKunihiko Hayashi }, 3301c1597c8SKunihiko Hayashi { 3311c1597c8SKunihiko Hayashi .compatible = "socionext,uniphier-nx1-pcie-phy", 3321c1597c8SKunihiko Hayashi .data = &uniphier_nx1_data, 3331c1597c8SKunihiko Hayashi }, 334c6d9b132SKunihiko Hayashi { /* sentinel */ }, 335c6d9b132SKunihiko Hayashi }; 336c6d9b132SKunihiko Hayashi MODULE_DEVICE_TABLE(of, uniphier_pciephy_match); 337c6d9b132SKunihiko Hayashi 338c6d9b132SKunihiko Hayashi static struct platform_driver uniphier_pciephy_driver = { 339c6d9b132SKunihiko Hayashi .probe = uniphier_pciephy_probe, 340c6d9b132SKunihiko Hayashi .driver = { 341c6d9b132SKunihiko Hayashi .name = "uniphier-pcie-phy", 342c6d9b132SKunihiko Hayashi .of_match_table = uniphier_pciephy_match, 343c6d9b132SKunihiko Hayashi }, 344c6d9b132SKunihiko Hayashi }; 345c6d9b132SKunihiko Hayashi module_platform_driver(uniphier_pciephy_driver); 346c6d9b132SKunihiko Hayashi 347c6d9b132SKunihiko Hayashi MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); 348c6d9b132SKunihiko Hayashi MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller"); 349c6d9b132SKunihiko Hayashi MODULE_LICENSE("GPL v2"); 350