1c6d9b132SKunihiko Hayashi // SPDX-License-Identifier: GPL-2.0 2c6d9b132SKunihiko Hayashi /* 3c6d9b132SKunihiko Hayashi * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller 4c6d9b132SKunihiko Hayashi * Copyright 2018, Socionext Inc. 5c6d9b132SKunihiko Hayashi * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 6c6d9b132SKunihiko Hayashi */ 7c6d9b132SKunihiko Hayashi 8c6d9b132SKunihiko Hayashi #include <linux/bitops.h> 9c6d9b132SKunihiko Hayashi #include <linux/bitfield.h> 10c6d9b132SKunihiko Hayashi #include <linux/clk.h> 11c6d9b132SKunihiko Hayashi #include <linux/iopoll.h> 12c6d9b132SKunihiko Hayashi #include <linux/mfd/syscon.h> 13c6d9b132SKunihiko Hayashi #include <linux/module.h> 14c6d9b132SKunihiko Hayashi #include <linux/of_device.h> 15c6d9b132SKunihiko Hayashi #include <linux/phy/phy.h> 16c6d9b132SKunihiko Hayashi #include <linux/platform_device.h> 17c6d9b132SKunihiko Hayashi #include <linux/regmap.h> 18c6d9b132SKunihiko Hayashi #include <linux/reset.h> 19c6d9b132SKunihiko Hayashi #include <linux/resource.h> 20c6d9b132SKunihiko Hayashi 21c6d9b132SKunihiko Hayashi /* PHY */ 2204de8fa2SKunihiko Hayashi #define PCL_PHY_CLKCTRL 0x0000 2304de8fa2SKunihiko Hayashi #define PORT_SEL_MASK GENMASK(11, 9) 2404de8fa2SKunihiko Hayashi #define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1) 2504de8fa2SKunihiko Hayashi 26c6d9b132SKunihiko Hayashi #define PCL_PHY_TEST_I 0x2000 27c6d9b132SKunihiko Hayashi #define TESTI_DAT_MASK GENMASK(13, 6) 28c6d9b132SKunihiko Hayashi #define TESTI_ADR_MASK GENMASK(5, 1) 29c6d9b132SKunihiko Hayashi #define TESTI_WR_EN BIT(0) 30c6d9b132SKunihiko Hayashi 31*4a90bbb4SKunihiko Hayashi #define PCL_PHY_TEST_O 0x2004 32*4a90bbb4SKunihiko Hayashi #define TESTO_DAT_MASK GENMASK(7, 0) 33*4a90bbb4SKunihiko Hayashi 34c6d9b132SKunihiko Hayashi #define PCL_PHY_RESET 0x200c 35c6d9b132SKunihiko Hayashi #define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */ 36c6d9b132SKunihiko Hayashi #define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */ 37c6d9b132SKunihiko Hayashi 38c6d9b132SKunihiko Hayashi /* SG */ 39c6d9b132SKunihiko Hayashi #define SG_USBPCIESEL 0x590 40c6d9b132SKunihiko Hayashi #define SG_USBPCIESEL_PCIE BIT(0) 41c6d9b132SKunihiko Hayashi 42c6d9b132SKunihiko Hayashi #define PCL_PHY_R00 0 43c6d9b132SKunihiko Hayashi #define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */ 44c6d9b132SKunihiko Hayashi #define PCL_PHY_R06 6 45c6d9b132SKunihiko Hayashi #define RX_EQ_ADJ GENMASK(5, 0) /* EQ adjustment value */ 46c6d9b132SKunihiko Hayashi #define RX_EQ_ADJ_VAL 0 47c6d9b132SKunihiko Hayashi #define PCL_PHY_R26 26 48c6d9b132SKunihiko Hayashi #define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */ 49c6d9b132SKunihiko Hayashi #define VCO_CTRL_INIT_VAL 5 50c6d9b132SKunihiko Hayashi 51c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv { 52c6d9b132SKunihiko Hayashi void __iomem *base; 53c6d9b132SKunihiko Hayashi struct device *dev; 5404de8fa2SKunihiko Hayashi struct clk *clk, *clk_gio; 5504de8fa2SKunihiko Hayashi struct reset_control *rst, *rst_gio; 56c6d9b132SKunihiko Hayashi const struct uniphier_pciephy_soc_data *data; 57c6d9b132SKunihiko Hayashi }; 58c6d9b132SKunihiko Hayashi 59c6d9b132SKunihiko Hayashi struct uniphier_pciephy_soc_data { 6004de8fa2SKunihiko Hayashi bool is_legacy; 616861781aSKunihiko Hayashi void (*set_phymode)(struct regmap *regmap); 62c6d9b132SKunihiko Hayashi }; 63c6d9b132SKunihiko Hayashi 64c6d9b132SKunihiko Hayashi static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv, 65c6d9b132SKunihiko Hayashi u32 data) 66c6d9b132SKunihiko Hayashi { 67c6d9b132SKunihiko Hayashi /* need to read TESTO twice after accessing TESTI */ 68c6d9b132SKunihiko Hayashi writel(data, priv->base + PCL_PHY_TEST_I); 69c6d9b132SKunihiko Hayashi readl(priv->base + PCL_PHY_TEST_O); 70c6d9b132SKunihiko Hayashi readl(priv->base + PCL_PHY_TEST_O); 71c6d9b132SKunihiko Hayashi } 72c6d9b132SKunihiko Hayashi 73c6d9b132SKunihiko Hayashi static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv, 74c6d9b132SKunihiko Hayashi u32 reg, u32 mask, u32 param) 75c6d9b132SKunihiko Hayashi { 76c6d9b132SKunihiko Hayashi u32 val; 77c6d9b132SKunihiko Hayashi 78c6d9b132SKunihiko Hayashi /* read previous data */ 79c6d9b132SKunihiko Hayashi val = FIELD_PREP(TESTI_DAT_MASK, 1); 80c6d9b132SKunihiko Hayashi val |= FIELD_PREP(TESTI_ADR_MASK, reg); 81c6d9b132SKunihiko Hayashi uniphier_pciephy_testio_write(priv, val); 82*4a90bbb4SKunihiko Hayashi val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK; 83c6d9b132SKunihiko Hayashi 84c6d9b132SKunihiko Hayashi /* update value */ 85*4a90bbb4SKunihiko Hayashi val &= ~mask; 86*4a90bbb4SKunihiko Hayashi val |= mask & param; 87*4a90bbb4SKunihiko Hayashi val = FIELD_PREP(TESTI_DAT_MASK, val); 88c6d9b132SKunihiko Hayashi val |= FIELD_PREP(TESTI_ADR_MASK, reg); 89c6d9b132SKunihiko Hayashi uniphier_pciephy_testio_write(priv, val); 90c6d9b132SKunihiko Hayashi uniphier_pciephy_testio_write(priv, val | TESTI_WR_EN); 91c6d9b132SKunihiko Hayashi uniphier_pciephy_testio_write(priv, val); 92c6d9b132SKunihiko Hayashi 93c6d9b132SKunihiko Hayashi /* read current data as dummy */ 94c6d9b132SKunihiko Hayashi val = FIELD_PREP(TESTI_DAT_MASK, 1); 95c6d9b132SKunihiko Hayashi val |= FIELD_PREP(TESTI_ADR_MASK, reg); 96c6d9b132SKunihiko Hayashi uniphier_pciephy_testio_write(priv, val); 97c6d9b132SKunihiko Hayashi readl(priv->base + PCL_PHY_TEST_O); 98c6d9b132SKunihiko Hayashi } 99c6d9b132SKunihiko Hayashi 100c6d9b132SKunihiko Hayashi static void uniphier_pciephy_assert(struct uniphier_pciephy_priv *priv) 101c6d9b132SKunihiko Hayashi { 102c6d9b132SKunihiko Hayashi u32 val; 103c6d9b132SKunihiko Hayashi 104c6d9b132SKunihiko Hayashi val = readl(priv->base + PCL_PHY_RESET); 105c6d9b132SKunihiko Hayashi val &= ~PCL_PHY_RESET_N; 106c6d9b132SKunihiko Hayashi val |= PCL_PHY_RESET_N_MNMODE; 107c6d9b132SKunihiko Hayashi writel(val, priv->base + PCL_PHY_RESET); 108c6d9b132SKunihiko Hayashi } 109c6d9b132SKunihiko Hayashi 110c6d9b132SKunihiko Hayashi static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv) 111c6d9b132SKunihiko Hayashi { 112c6d9b132SKunihiko Hayashi u32 val; 113c6d9b132SKunihiko Hayashi 114c6d9b132SKunihiko Hayashi val = readl(priv->base + PCL_PHY_RESET); 115c6d9b132SKunihiko Hayashi val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N; 116c6d9b132SKunihiko Hayashi writel(val, priv->base + PCL_PHY_RESET); 117c6d9b132SKunihiko Hayashi } 118c6d9b132SKunihiko Hayashi 119c6d9b132SKunihiko Hayashi static int uniphier_pciephy_init(struct phy *phy) 120c6d9b132SKunihiko Hayashi { 121c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); 12204de8fa2SKunihiko Hayashi u32 val; 123c6d9b132SKunihiko Hayashi int ret; 124c6d9b132SKunihiko Hayashi 125c6d9b132SKunihiko Hayashi ret = clk_prepare_enable(priv->clk); 126c6d9b132SKunihiko Hayashi if (ret) 127c6d9b132SKunihiko Hayashi return ret; 128c6d9b132SKunihiko Hayashi 12904de8fa2SKunihiko Hayashi ret = clk_prepare_enable(priv->clk_gio); 130c6d9b132SKunihiko Hayashi if (ret) 131c6d9b132SKunihiko Hayashi goto out_clk_disable; 132c6d9b132SKunihiko Hayashi 13304de8fa2SKunihiko Hayashi ret = reset_control_deassert(priv->rst); 13404de8fa2SKunihiko Hayashi if (ret) 13504de8fa2SKunihiko Hayashi goto out_clk_gio_disable; 13604de8fa2SKunihiko Hayashi 13704de8fa2SKunihiko Hayashi ret = reset_control_deassert(priv->rst_gio); 13804de8fa2SKunihiko Hayashi if (ret) 13904de8fa2SKunihiko Hayashi goto out_rst_assert; 14004de8fa2SKunihiko Hayashi 14104de8fa2SKunihiko Hayashi /* support only 1 port */ 14204de8fa2SKunihiko Hayashi val = readl(priv->base + PCL_PHY_CLKCTRL); 14304de8fa2SKunihiko Hayashi val &= ~PORT_SEL_MASK; 14404de8fa2SKunihiko Hayashi val |= PORT_SEL_1; 14504de8fa2SKunihiko Hayashi writel(val, priv->base + PCL_PHY_CLKCTRL); 14604de8fa2SKunihiko Hayashi 14704de8fa2SKunihiko Hayashi /* legacy controller doesn't have phy_reset and parameters */ 14804de8fa2SKunihiko Hayashi if (priv->data->is_legacy) 14904de8fa2SKunihiko Hayashi return 0; 15004de8fa2SKunihiko Hayashi 151c6d9b132SKunihiko Hayashi uniphier_pciephy_set_param(priv, PCL_PHY_R00, 152c6d9b132SKunihiko Hayashi RX_EQ_ADJ_EN, RX_EQ_ADJ_EN); 153c6d9b132SKunihiko Hayashi uniphier_pciephy_set_param(priv, PCL_PHY_R06, RX_EQ_ADJ, 154c6d9b132SKunihiko Hayashi FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL)); 155c6d9b132SKunihiko Hayashi uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL, 156c6d9b132SKunihiko Hayashi FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL)); 157c6d9b132SKunihiko Hayashi usleep_range(1, 10); 158c6d9b132SKunihiko Hayashi 159c6d9b132SKunihiko Hayashi uniphier_pciephy_deassert(priv); 160c6d9b132SKunihiko Hayashi usleep_range(1, 10); 161c6d9b132SKunihiko Hayashi 162c6d9b132SKunihiko Hayashi return 0; 163c6d9b132SKunihiko Hayashi 16404de8fa2SKunihiko Hayashi out_rst_assert: 16504de8fa2SKunihiko Hayashi reset_control_assert(priv->rst); 16604de8fa2SKunihiko Hayashi out_clk_gio_disable: 16704de8fa2SKunihiko Hayashi clk_disable_unprepare(priv->clk_gio); 168c6d9b132SKunihiko Hayashi out_clk_disable: 169c6d9b132SKunihiko Hayashi clk_disable_unprepare(priv->clk); 170c6d9b132SKunihiko Hayashi 171c6d9b132SKunihiko Hayashi return ret; 172c6d9b132SKunihiko Hayashi } 173c6d9b132SKunihiko Hayashi 174c6d9b132SKunihiko Hayashi static int uniphier_pciephy_exit(struct phy *phy) 175c6d9b132SKunihiko Hayashi { 176c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); 177c6d9b132SKunihiko Hayashi 17804de8fa2SKunihiko Hayashi if (!priv->data->is_legacy) 179c6d9b132SKunihiko Hayashi uniphier_pciephy_assert(priv); 18004de8fa2SKunihiko Hayashi reset_control_assert(priv->rst_gio); 181c6d9b132SKunihiko Hayashi reset_control_assert(priv->rst); 18204de8fa2SKunihiko Hayashi clk_disable_unprepare(priv->clk_gio); 183c6d9b132SKunihiko Hayashi clk_disable_unprepare(priv->clk); 184c6d9b132SKunihiko Hayashi 185c6d9b132SKunihiko Hayashi return 0; 186c6d9b132SKunihiko Hayashi } 187c6d9b132SKunihiko Hayashi 188c6d9b132SKunihiko Hayashi static const struct phy_ops uniphier_pciephy_ops = { 189c6d9b132SKunihiko Hayashi .init = uniphier_pciephy_init, 190c6d9b132SKunihiko Hayashi .exit = uniphier_pciephy_exit, 191c6d9b132SKunihiko Hayashi .owner = THIS_MODULE, 192c6d9b132SKunihiko Hayashi }; 193c6d9b132SKunihiko Hayashi 194c6d9b132SKunihiko Hayashi static int uniphier_pciephy_probe(struct platform_device *pdev) 195c6d9b132SKunihiko Hayashi { 196c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv *priv; 197c6d9b132SKunihiko Hayashi struct phy_provider *phy_provider; 198c6d9b132SKunihiko Hayashi struct device *dev = &pdev->dev; 199c6d9b132SKunihiko Hayashi struct regmap *regmap; 200c6d9b132SKunihiko Hayashi struct phy *phy; 201c6d9b132SKunihiko Hayashi 202c6d9b132SKunihiko Hayashi priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 203c6d9b132SKunihiko Hayashi if (!priv) 204c6d9b132SKunihiko Hayashi return -ENOMEM; 205c6d9b132SKunihiko Hayashi 206c6d9b132SKunihiko Hayashi priv->data = of_device_get_match_data(dev); 207c6d9b132SKunihiko Hayashi if (WARN_ON(!priv->data)) 208c6d9b132SKunihiko Hayashi return -EINVAL; 209c6d9b132SKunihiko Hayashi 210c6d9b132SKunihiko Hayashi priv->dev = dev; 211c6d9b132SKunihiko Hayashi 21240d76346SKunihiko Hayashi priv->base = devm_platform_ioremap_resource(pdev, 0); 213c6d9b132SKunihiko Hayashi if (IS_ERR(priv->base)) 214c6d9b132SKunihiko Hayashi return PTR_ERR(priv->base); 215c6d9b132SKunihiko Hayashi 21604de8fa2SKunihiko Hayashi if (priv->data->is_legacy) { 21704de8fa2SKunihiko Hayashi priv->clk_gio = devm_clk_get(dev, "gio"); 21804de8fa2SKunihiko Hayashi if (IS_ERR(priv->clk_gio)) 21904de8fa2SKunihiko Hayashi return PTR_ERR(priv->clk_gio); 22004de8fa2SKunihiko Hayashi 22104de8fa2SKunihiko Hayashi priv->rst_gio = 22204de8fa2SKunihiko Hayashi devm_reset_control_get_shared(dev, "gio"); 22304de8fa2SKunihiko Hayashi if (IS_ERR(priv->rst_gio)) 22404de8fa2SKunihiko Hayashi return PTR_ERR(priv->rst_gio); 22504de8fa2SKunihiko Hayashi 22604de8fa2SKunihiko Hayashi priv->clk = devm_clk_get(dev, "link"); 22704de8fa2SKunihiko Hayashi if (IS_ERR(priv->clk)) 22804de8fa2SKunihiko Hayashi return PTR_ERR(priv->clk); 22904de8fa2SKunihiko Hayashi 23004de8fa2SKunihiko Hayashi priv->rst = devm_reset_control_get_shared(dev, "link"); 23104de8fa2SKunihiko Hayashi if (IS_ERR(priv->rst)) 23204de8fa2SKunihiko Hayashi return PTR_ERR(priv->rst); 23304de8fa2SKunihiko Hayashi } else { 234c6d9b132SKunihiko Hayashi priv->clk = devm_clk_get(dev, NULL); 235c6d9b132SKunihiko Hayashi if (IS_ERR(priv->clk)) 236c6d9b132SKunihiko Hayashi return PTR_ERR(priv->clk); 237c6d9b132SKunihiko Hayashi 238c6d9b132SKunihiko Hayashi priv->rst = devm_reset_control_get_shared(dev, NULL); 239c6d9b132SKunihiko Hayashi if (IS_ERR(priv->rst)) 240c6d9b132SKunihiko Hayashi return PTR_ERR(priv->rst); 24104de8fa2SKunihiko Hayashi } 242c6d9b132SKunihiko Hayashi 243c6d9b132SKunihiko Hayashi phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops); 244c6d9b132SKunihiko Hayashi if (IS_ERR(phy)) 245c6d9b132SKunihiko Hayashi return PTR_ERR(phy); 246c6d9b132SKunihiko Hayashi 247c6d9b132SKunihiko Hayashi regmap = syscon_regmap_lookup_by_phandle(dev->of_node, 248c6d9b132SKunihiko Hayashi "socionext,syscon"); 2496861781aSKunihiko Hayashi if (!IS_ERR(regmap) && priv->data->set_phymode) 2506861781aSKunihiko Hayashi priv->data->set_phymode(regmap); 251c6d9b132SKunihiko Hayashi 252c6d9b132SKunihiko Hayashi phy_set_drvdata(phy, priv); 253c6d9b132SKunihiko Hayashi phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 254c6d9b132SKunihiko Hayashi 255c6d9b132SKunihiko Hayashi return PTR_ERR_OR_ZERO(phy_provider); 256c6d9b132SKunihiko Hayashi } 257c6d9b132SKunihiko Hayashi 2586861781aSKunihiko Hayashi static void uniphier_pciephy_ld20_setmode(struct regmap *regmap) 2596861781aSKunihiko Hayashi { 2606861781aSKunihiko Hayashi regmap_update_bits(regmap, SG_USBPCIESEL, 2616861781aSKunihiko Hayashi SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE); 2626861781aSKunihiko Hayashi } 2636861781aSKunihiko Hayashi 26404de8fa2SKunihiko Hayashi static const struct uniphier_pciephy_soc_data uniphier_pro5_data = { 26504de8fa2SKunihiko Hayashi .is_legacy = true, 26604de8fa2SKunihiko Hayashi }; 26704de8fa2SKunihiko Hayashi 268c6d9b132SKunihiko Hayashi static const struct uniphier_pciephy_soc_data uniphier_ld20_data = { 26904de8fa2SKunihiko Hayashi .is_legacy = false, 2706861781aSKunihiko Hayashi .set_phymode = uniphier_pciephy_ld20_setmode, 271c6d9b132SKunihiko Hayashi }; 272c6d9b132SKunihiko Hayashi 273c6d9b132SKunihiko Hayashi static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = { 27404de8fa2SKunihiko Hayashi .is_legacy = false, 275c6d9b132SKunihiko Hayashi }; 276c6d9b132SKunihiko Hayashi 277c6d9b132SKunihiko Hayashi static const struct of_device_id uniphier_pciephy_match[] = { 278c6d9b132SKunihiko Hayashi { 27904de8fa2SKunihiko Hayashi .compatible = "socionext,uniphier-pro5-pcie-phy", 28004de8fa2SKunihiko Hayashi .data = &uniphier_pro5_data, 28104de8fa2SKunihiko Hayashi }, 28204de8fa2SKunihiko Hayashi { 283c6d9b132SKunihiko Hayashi .compatible = "socionext,uniphier-ld20-pcie-phy", 284c6d9b132SKunihiko Hayashi .data = &uniphier_ld20_data, 285c6d9b132SKunihiko Hayashi }, 286c6d9b132SKunihiko Hayashi { 287c6d9b132SKunihiko Hayashi .compatible = "socionext,uniphier-pxs3-pcie-phy", 288c6d9b132SKunihiko Hayashi .data = &uniphier_pxs3_data, 289c6d9b132SKunihiko Hayashi }, 290c6d9b132SKunihiko Hayashi { /* sentinel */ }, 291c6d9b132SKunihiko Hayashi }; 292c6d9b132SKunihiko Hayashi MODULE_DEVICE_TABLE(of, uniphier_pciephy_match); 293c6d9b132SKunihiko Hayashi 294c6d9b132SKunihiko Hayashi static struct platform_driver uniphier_pciephy_driver = { 295c6d9b132SKunihiko Hayashi .probe = uniphier_pciephy_probe, 296c6d9b132SKunihiko Hayashi .driver = { 297c6d9b132SKunihiko Hayashi .name = "uniphier-pcie-phy", 298c6d9b132SKunihiko Hayashi .of_match_table = uniphier_pciephy_match, 299c6d9b132SKunihiko Hayashi }, 300c6d9b132SKunihiko Hayashi }; 301c6d9b132SKunihiko Hayashi module_platform_driver(uniphier_pciephy_driver); 302c6d9b132SKunihiko Hayashi 303c6d9b132SKunihiko Hayashi MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); 304c6d9b132SKunihiko Hayashi MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller"); 305c6d9b132SKunihiko Hayashi MODULE_LICENSE("GPL v2"); 306