1c6d9b132SKunihiko Hayashi // SPDX-License-Identifier: GPL-2.0 2c6d9b132SKunihiko Hayashi /* 3c6d9b132SKunihiko Hayashi * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller 4c6d9b132SKunihiko Hayashi * Copyright 2018, Socionext Inc. 5c6d9b132SKunihiko Hayashi * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 6c6d9b132SKunihiko Hayashi */ 7c6d9b132SKunihiko Hayashi 8c6d9b132SKunihiko Hayashi #include <linux/bitops.h> 9c6d9b132SKunihiko Hayashi #include <linux/bitfield.h> 10c6d9b132SKunihiko Hayashi #include <linux/clk.h> 11c6d9b132SKunihiko Hayashi #include <linux/iopoll.h> 12c6d9b132SKunihiko Hayashi #include <linux/mfd/syscon.h> 13c6d9b132SKunihiko Hayashi #include <linux/module.h> 14c6d9b132SKunihiko Hayashi #include <linux/of_device.h> 15c6d9b132SKunihiko Hayashi #include <linux/phy/phy.h> 16c6d9b132SKunihiko Hayashi #include <linux/platform_device.h> 17c6d9b132SKunihiko Hayashi #include <linux/regmap.h> 18c6d9b132SKunihiko Hayashi #include <linux/reset.h> 19c6d9b132SKunihiko Hayashi #include <linux/resource.h> 20c6d9b132SKunihiko Hayashi 21c6d9b132SKunihiko Hayashi /* PHY */ 22c6d9b132SKunihiko Hayashi #define PCL_PHY_TEST_I 0x2000 23c6d9b132SKunihiko Hayashi #define PCL_PHY_TEST_O 0x2004 24c6d9b132SKunihiko Hayashi #define TESTI_DAT_MASK GENMASK(13, 6) 25c6d9b132SKunihiko Hayashi #define TESTI_ADR_MASK GENMASK(5, 1) 26c6d9b132SKunihiko Hayashi #define TESTI_WR_EN BIT(0) 27c6d9b132SKunihiko Hayashi 28c6d9b132SKunihiko Hayashi #define PCL_PHY_RESET 0x200c 29c6d9b132SKunihiko Hayashi #define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */ 30c6d9b132SKunihiko Hayashi #define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */ 31c6d9b132SKunihiko Hayashi 32c6d9b132SKunihiko Hayashi /* SG */ 33c6d9b132SKunihiko Hayashi #define SG_USBPCIESEL 0x590 34c6d9b132SKunihiko Hayashi #define SG_USBPCIESEL_PCIE BIT(0) 35c6d9b132SKunihiko Hayashi 36c6d9b132SKunihiko Hayashi #define PCL_PHY_R00 0 37c6d9b132SKunihiko Hayashi #define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */ 38c6d9b132SKunihiko Hayashi #define PCL_PHY_R06 6 39c6d9b132SKunihiko Hayashi #define RX_EQ_ADJ GENMASK(5, 0) /* EQ adjustment value */ 40c6d9b132SKunihiko Hayashi #define RX_EQ_ADJ_VAL 0 41c6d9b132SKunihiko Hayashi #define PCL_PHY_R26 26 42c6d9b132SKunihiko Hayashi #define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */ 43c6d9b132SKunihiko Hayashi #define VCO_CTRL_INIT_VAL 5 44c6d9b132SKunihiko Hayashi 45c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv { 46c6d9b132SKunihiko Hayashi void __iomem *base; 47c6d9b132SKunihiko Hayashi struct device *dev; 48c6d9b132SKunihiko Hayashi struct clk *clk; 49c6d9b132SKunihiko Hayashi struct reset_control *rst; 50c6d9b132SKunihiko Hayashi const struct uniphier_pciephy_soc_data *data; 51c6d9b132SKunihiko Hayashi }; 52c6d9b132SKunihiko Hayashi 53c6d9b132SKunihiko Hayashi struct uniphier_pciephy_soc_data { 54c6d9b132SKunihiko Hayashi bool has_syscon; 55c6d9b132SKunihiko Hayashi }; 56c6d9b132SKunihiko Hayashi 57c6d9b132SKunihiko Hayashi static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv, 58c6d9b132SKunihiko Hayashi u32 data) 59c6d9b132SKunihiko Hayashi { 60c6d9b132SKunihiko Hayashi /* need to read TESTO twice after accessing TESTI */ 61c6d9b132SKunihiko Hayashi writel(data, priv->base + PCL_PHY_TEST_I); 62c6d9b132SKunihiko Hayashi readl(priv->base + PCL_PHY_TEST_O); 63c6d9b132SKunihiko Hayashi readl(priv->base + PCL_PHY_TEST_O); 64c6d9b132SKunihiko Hayashi } 65c6d9b132SKunihiko Hayashi 66c6d9b132SKunihiko Hayashi static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv, 67c6d9b132SKunihiko Hayashi u32 reg, u32 mask, u32 param) 68c6d9b132SKunihiko Hayashi { 69c6d9b132SKunihiko Hayashi u32 val; 70c6d9b132SKunihiko Hayashi 71c6d9b132SKunihiko Hayashi /* read previous data */ 72c6d9b132SKunihiko Hayashi val = FIELD_PREP(TESTI_DAT_MASK, 1); 73c6d9b132SKunihiko Hayashi val |= FIELD_PREP(TESTI_ADR_MASK, reg); 74c6d9b132SKunihiko Hayashi uniphier_pciephy_testio_write(priv, val); 75c6d9b132SKunihiko Hayashi val = readl(priv->base + PCL_PHY_TEST_O); 76c6d9b132SKunihiko Hayashi 77c6d9b132SKunihiko Hayashi /* update value */ 78c6d9b132SKunihiko Hayashi val &= ~FIELD_PREP(TESTI_DAT_MASK, mask); 79c6d9b132SKunihiko Hayashi val = FIELD_PREP(TESTI_DAT_MASK, mask & param); 80c6d9b132SKunihiko Hayashi val |= FIELD_PREP(TESTI_ADR_MASK, reg); 81c6d9b132SKunihiko Hayashi uniphier_pciephy_testio_write(priv, val); 82c6d9b132SKunihiko Hayashi uniphier_pciephy_testio_write(priv, val | TESTI_WR_EN); 83c6d9b132SKunihiko Hayashi uniphier_pciephy_testio_write(priv, val); 84c6d9b132SKunihiko Hayashi 85c6d9b132SKunihiko Hayashi /* read current data as dummy */ 86c6d9b132SKunihiko Hayashi val = FIELD_PREP(TESTI_DAT_MASK, 1); 87c6d9b132SKunihiko Hayashi val |= FIELD_PREP(TESTI_ADR_MASK, reg); 88c6d9b132SKunihiko Hayashi uniphier_pciephy_testio_write(priv, val); 89c6d9b132SKunihiko Hayashi readl(priv->base + PCL_PHY_TEST_O); 90c6d9b132SKunihiko Hayashi } 91c6d9b132SKunihiko Hayashi 92c6d9b132SKunihiko Hayashi static void uniphier_pciephy_assert(struct uniphier_pciephy_priv *priv) 93c6d9b132SKunihiko Hayashi { 94c6d9b132SKunihiko Hayashi u32 val; 95c6d9b132SKunihiko Hayashi 96c6d9b132SKunihiko Hayashi val = readl(priv->base + PCL_PHY_RESET); 97c6d9b132SKunihiko Hayashi val &= ~PCL_PHY_RESET_N; 98c6d9b132SKunihiko Hayashi val |= PCL_PHY_RESET_N_MNMODE; 99c6d9b132SKunihiko Hayashi writel(val, priv->base + PCL_PHY_RESET); 100c6d9b132SKunihiko Hayashi } 101c6d9b132SKunihiko Hayashi 102c6d9b132SKunihiko Hayashi static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv) 103c6d9b132SKunihiko Hayashi { 104c6d9b132SKunihiko Hayashi u32 val; 105c6d9b132SKunihiko Hayashi 106c6d9b132SKunihiko Hayashi val = readl(priv->base + PCL_PHY_RESET); 107c6d9b132SKunihiko Hayashi val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N; 108c6d9b132SKunihiko Hayashi writel(val, priv->base + PCL_PHY_RESET); 109c6d9b132SKunihiko Hayashi } 110c6d9b132SKunihiko Hayashi 111c6d9b132SKunihiko Hayashi static int uniphier_pciephy_init(struct phy *phy) 112c6d9b132SKunihiko Hayashi { 113c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); 114c6d9b132SKunihiko Hayashi int ret; 115c6d9b132SKunihiko Hayashi 116c6d9b132SKunihiko Hayashi ret = clk_prepare_enable(priv->clk); 117c6d9b132SKunihiko Hayashi if (ret) 118c6d9b132SKunihiko Hayashi return ret; 119c6d9b132SKunihiko Hayashi 120c6d9b132SKunihiko Hayashi ret = reset_control_deassert(priv->rst); 121c6d9b132SKunihiko Hayashi if (ret) 122c6d9b132SKunihiko Hayashi goto out_clk_disable; 123c6d9b132SKunihiko Hayashi 124c6d9b132SKunihiko Hayashi uniphier_pciephy_set_param(priv, PCL_PHY_R00, 125c6d9b132SKunihiko Hayashi RX_EQ_ADJ_EN, RX_EQ_ADJ_EN); 126c6d9b132SKunihiko Hayashi uniphier_pciephy_set_param(priv, PCL_PHY_R06, RX_EQ_ADJ, 127c6d9b132SKunihiko Hayashi FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL)); 128c6d9b132SKunihiko Hayashi uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL, 129c6d9b132SKunihiko Hayashi FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL)); 130c6d9b132SKunihiko Hayashi usleep_range(1, 10); 131c6d9b132SKunihiko Hayashi 132c6d9b132SKunihiko Hayashi uniphier_pciephy_deassert(priv); 133c6d9b132SKunihiko Hayashi usleep_range(1, 10); 134c6d9b132SKunihiko Hayashi 135c6d9b132SKunihiko Hayashi return 0; 136c6d9b132SKunihiko Hayashi 137c6d9b132SKunihiko Hayashi out_clk_disable: 138c6d9b132SKunihiko Hayashi clk_disable_unprepare(priv->clk); 139c6d9b132SKunihiko Hayashi 140c6d9b132SKunihiko Hayashi return ret; 141c6d9b132SKunihiko Hayashi } 142c6d9b132SKunihiko Hayashi 143c6d9b132SKunihiko Hayashi static int uniphier_pciephy_exit(struct phy *phy) 144c6d9b132SKunihiko Hayashi { 145c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); 146c6d9b132SKunihiko Hayashi 147c6d9b132SKunihiko Hayashi uniphier_pciephy_assert(priv); 148c6d9b132SKunihiko Hayashi reset_control_assert(priv->rst); 149c6d9b132SKunihiko Hayashi clk_disable_unprepare(priv->clk); 150c6d9b132SKunihiko Hayashi 151c6d9b132SKunihiko Hayashi return 0; 152c6d9b132SKunihiko Hayashi } 153c6d9b132SKunihiko Hayashi 154c6d9b132SKunihiko Hayashi static const struct phy_ops uniphier_pciephy_ops = { 155c6d9b132SKunihiko Hayashi .init = uniphier_pciephy_init, 156c6d9b132SKunihiko Hayashi .exit = uniphier_pciephy_exit, 157c6d9b132SKunihiko Hayashi .owner = THIS_MODULE, 158c6d9b132SKunihiko Hayashi }; 159c6d9b132SKunihiko Hayashi 160c6d9b132SKunihiko Hayashi static int uniphier_pciephy_probe(struct platform_device *pdev) 161c6d9b132SKunihiko Hayashi { 162c6d9b132SKunihiko Hayashi struct uniphier_pciephy_priv *priv; 163c6d9b132SKunihiko Hayashi struct phy_provider *phy_provider; 164c6d9b132SKunihiko Hayashi struct device *dev = &pdev->dev; 165c6d9b132SKunihiko Hayashi struct regmap *regmap; 166c6d9b132SKunihiko Hayashi struct phy *phy; 167c6d9b132SKunihiko Hayashi 168c6d9b132SKunihiko Hayashi priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 169c6d9b132SKunihiko Hayashi if (!priv) 170c6d9b132SKunihiko Hayashi return -ENOMEM; 171c6d9b132SKunihiko Hayashi 172c6d9b132SKunihiko Hayashi priv->data = of_device_get_match_data(dev); 173c6d9b132SKunihiko Hayashi if (WARN_ON(!priv->data)) 174c6d9b132SKunihiko Hayashi return -EINVAL; 175c6d9b132SKunihiko Hayashi 176c6d9b132SKunihiko Hayashi priv->dev = dev; 177c6d9b132SKunihiko Hayashi 178*40d76346SKunihiko Hayashi priv->base = devm_platform_ioremap_resource(pdev, 0); 179c6d9b132SKunihiko Hayashi if (IS_ERR(priv->base)) 180c6d9b132SKunihiko Hayashi return PTR_ERR(priv->base); 181c6d9b132SKunihiko Hayashi 182c6d9b132SKunihiko Hayashi priv->clk = devm_clk_get(dev, NULL); 183c6d9b132SKunihiko Hayashi if (IS_ERR(priv->clk)) 184c6d9b132SKunihiko Hayashi return PTR_ERR(priv->clk); 185c6d9b132SKunihiko Hayashi 186c6d9b132SKunihiko Hayashi priv->rst = devm_reset_control_get_shared(dev, NULL); 187c6d9b132SKunihiko Hayashi if (IS_ERR(priv->rst)) 188c6d9b132SKunihiko Hayashi return PTR_ERR(priv->rst); 189c6d9b132SKunihiko Hayashi 190c6d9b132SKunihiko Hayashi phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops); 191c6d9b132SKunihiko Hayashi if (IS_ERR(phy)) 192c6d9b132SKunihiko Hayashi return PTR_ERR(phy); 193c6d9b132SKunihiko Hayashi 194c6d9b132SKunihiko Hayashi regmap = syscon_regmap_lookup_by_phandle(dev->of_node, 195c6d9b132SKunihiko Hayashi "socionext,syscon"); 196c6d9b132SKunihiko Hayashi if (!IS_ERR(regmap) && priv->data->has_syscon) 197c6d9b132SKunihiko Hayashi regmap_update_bits(regmap, SG_USBPCIESEL, 198c6d9b132SKunihiko Hayashi SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE); 199c6d9b132SKunihiko Hayashi 200c6d9b132SKunihiko Hayashi phy_set_drvdata(phy, priv); 201c6d9b132SKunihiko Hayashi phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 202c6d9b132SKunihiko Hayashi 203c6d9b132SKunihiko Hayashi return PTR_ERR_OR_ZERO(phy_provider); 204c6d9b132SKunihiko Hayashi } 205c6d9b132SKunihiko Hayashi 206c6d9b132SKunihiko Hayashi static const struct uniphier_pciephy_soc_data uniphier_ld20_data = { 207c6d9b132SKunihiko Hayashi .has_syscon = true, 208c6d9b132SKunihiko Hayashi }; 209c6d9b132SKunihiko Hayashi 210c6d9b132SKunihiko Hayashi static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = { 211c6d9b132SKunihiko Hayashi .has_syscon = false, 212c6d9b132SKunihiko Hayashi }; 213c6d9b132SKunihiko Hayashi 214c6d9b132SKunihiko Hayashi static const struct of_device_id uniphier_pciephy_match[] = { 215c6d9b132SKunihiko Hayashi { 216c6d9b132SKunihiko Hayashi .compatible = "socionext,uniphier-ld20-pcie-phy", 217c6d9b132SKunihiko Hayashi .data = &uniphier_ld20_data, 218c6d9b132SKunihiko Hayashi }, 219c6d9b132SKunihiko Hayashi { 220c6d9b132SKunihiko Hayashi .compatible = "socionext,uniphier-pxs3-pcie-phy", 221c6d9b132SKunihiko Hayashi .data = &uniphier_pxs3_data, 222c6d9b132SKunihiko Hayashi }, 223c6d9b132SKunihiko Hayashi { /* sentinel */ }, 224c6d9b132SKunihiko Hayashi }; 225c6d9b132SKunihiko Hayashi MODULE_DEVICE_TABLE(of, uniphier_pciephy_match); 226c6d9b132SKunihiko Hayashi 227c6d9b132SKunihiko Hayashi static struct platform_driver uniphier_pciephy_driver = { 228c6d9b132SKunihiko Hayashi .probe = uniphier_pciephy_probe, 229c6d9b132SKunihiko Hayashi .driver = { 230c6d9b132SKunihiko Hayashi .name = "uniphier-pcie-phy", 231c6d9b132SKunihiko Hayashi .of_match_table = uniphier_pciephy_match, 232c6d9b132SKunihiko Hayashi }, 233c6d9b132SKunihiko Hayashi }; 234c6d9b132SKunihiko Hayashi module_platform_driver(uniphier_pciephy_driver); 235c6d9b132SKunihiko Hayashi 236c6d9b132SKunihiko Hayashi MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); 237c6d9b132SKunihiko Hayashi MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller"); 238c6d9b132SKunihiko Hayashi MODULE_LICENSE("GPL v2"); 239