1*a1bf1c60SKunihiko Hayashi // SPDX-License-Identifier: GPL-2.0 2*a1bf1c60SKunihiko Hayashi /* 3*a1bf1c60SKunihiko Hayashi * phy-uniphier-ahci.c - PHY driver for UniPhier AHCI controller 4*a1bf1c60SKunihiko Hayashi * Copyright 2016-2020, Socionext Inc. 5*a1bf1c60SKunihiko Hayashi * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 6*a1bf1c60SKunihiko Hayashi */ 7*a1bf1c60SKunihiko Hayashi 8*a1bf1c60SKunihiko Hayashi #include <linux/bitfield.h> 9*a1bf1c60SKunihiko Hayashi #include <linux/bitops.h> 10*a1bf1c60SKunihiko Hayashi #include <linux/clk.h> 11*a1bf1c60SKunihiko Hayashi #include <linux/iopoll.h> 12*a1bf1c60SKunihiko Hayashi #include <linux/module.h> 13*a1bf1c60SKunihiko Hayashi #include <linux/of.h> 14*a1bf1c60SKunihiko Hayashi #include <linux/of_platform.h> 15*a1bf1c60SKunihiko Hayashi #include <linux/phy/phy.h> 16*a1bf1c60SKunihiko Hayashi #include <linux/platform_device.h> 17*a1bf1c60SKunihiko Hayashi #include <linux/reset.h> 18*a1bf1c60SKunihiko Hayashi 19*a1bf1c60SKunihiko Hayashi struct uniphier_ahciphy_priv { 20*a1bf1c60SKunihiko Hayashi struct device *dev; 21*a1bf1c60SKunihiko Hayashi void __iomem *base; 22*a1bf1c60SKunihiko Hayashi struct clk *clk, *clk_parent; 23*a1bf1c60SKunihiko Hayashi struct reset_control *rst, *rst_parent; 24*a1bf1c60SKunihiko Hayashi const struct uniphier_ahciphy_soc_data *data; 25*a1bf1c60SKunihiko Hayashi }; 26*a1bf1c60SKunihiko Hayashi 27*a1bf1c60SKunihiko Hayashi struct uniphier_ahciphy_soc_data { 28*a1bf1c60SKunihiko Hayashi int (*init)(struct uniphier_ahciphy_priv *priv); 29*a1bf1c60SKunihiko Hayashi int (*power_on)(struct uniphier_ahciphy_priv *priv); 30*a1bf1c60SKunihiko Hayashi int (*power_off)(struct uniphier_ahciphy_priv *priv); 31*a1bf1c60SKunihiko Hayashi bool is_ready_high; 32*a1bf1c60SKunihiko Hayashi bool is_phy_clk; 33*a1bf1c60SKunihiko Hayashi }; 34*a1bf1c60SKunihiko Hayashi 35*a1bf1c60SKunihiko Hayashi /* for PXs2/PXs3 */ 36*a1bf1c60SKunihiko Hayashi #define CKCTRL 0x0 37*a1bf1c60SKunihiko Hayashi #define CKCTRL_P0_READY BIT(15) 38*a1bf1c60SKunihiko Hayashi #define CKCTRL_P0_RESET BIT(10) 39*a1bf1c60SKunihiko Hayashi #define CKCTRL_REF_SSP_EN BIT(9) 40*a1bf1c60SKunihiko Hayashi #define TXCTRL0 0x4 41*a1bf1c60SKunihiko Hayashi #define TXCTRL0_AMP_G3_MASK GENMASK(22, 16) 42*a1bf1c60SKunihiko Hayashi #define TXCTRL0_AMP_G2_MASK GENMASK(14, 8) 43*a1bf1c60SKunihiko Hayashi #define TXCTRL0_AMP_G1_MASK GENMASK(6, 0) 44*a1bf1c60SKunihiko Hayashi #define TXCTRL1 0x8 45*a1bf1c60SKunihiko Hayashi #define TXCTRL1_DEEMPH_G3_MASK GENMASK(21, 16) 46*a1bf1c60SKunihiko Hayashi #define TXCTRL1_DEEMPH_G2_MASK GENMASK(13, 8) 47*a1bf1c60SKunihiko Hayashi #define TXCTRL1_DEEMPH_G1_MASK GENMASK(5, 0) 48*a1bf1c60SKunihiko Hayashi #define RXCTRL 0xc 49*a1bf1c60SKunihiko Hayashi #define RXCTRL_LOS_LVL_MASK GENMASK(20, 16) 50*a1bf1c60SKunihiko Hayashi #define RXCTRL_LOS_BIAS_MASK GENMASK(10, 8) 51*a1bf1c60SKunihiko Hayashi #define RXCTRL_RX_EQ_MASK GENMASK(2, 0) 52*a1bf1c60SKunihiko Hayashi 53*a1bf1c60SKunihiko Hayashi static void uniphier_ahciphy_pxs2_enable(struct uniphier_ahciphy_priv *priv, 54*a1bf1c60SKunihiko Hayashi bool enable) 55*a1bf1c60SKunihiko Hayashi { 56*a1bf1c60SKunihiko Hayashi u32 val; 57*a1bf1c60SKunihiko Hayashi 58*a1bf1c60SKunihiko Hayashi val = readl(priv->base + CKCTRL); 59*a1bf1c60SKunihiko Hayashi 60*a1bf1c60SKunihiko Hayashi if (enable) { 61*a1bf1c60SKunihiko Hayashi val |= CKCTRL_REF_SSP_EN; 62*a1bf1c60SKunihiko Hayashi writel(val, priv->base + CKCTRL); 63*a1bf1c60SKunihiko Hayashi val &= ~CKCTRL_P0_RESET; 64*a1bf1c60SKunihiko Hayashi writel(val, priv->base + CKCTRL); 65*a1bf1c60SKunihiko Hayashi } else { 66*a1bf1c60SKunihiko Hayashi val |= CKCTRL_P0_RESET; 67*a1bf1c60SKunihiko Hayashi writel(val, priv->base + CKCTRL); 68*a1bf1c60SKunihiko Hayashi val &= ~CKCTRL_REF_SSP_EN; 69*a1bf1c60SKunihiko Hayashi writel(val, priv->base + CKCTRL); 70*a1bf1c60SKunihiko Hayashi } 71*a1bf1c60SKunihiko Hayashi } 72*a1bf1c60SKunihiko Hayashi 73*a1bf1c60SKunihiko Hayashi static int uniphier_ahciphy_pxs2_power_on(struct uniphier_ahciphy_priv *priv) 74*a1bf1c60SKunihiko Hayashi { 75*a1bf1c60SKunihiko Hayashi int ret; 76*a1bf1c60SKunihiko Hayashi u32 val; 77*a1bf1c60SKunihiko Hayashi 78*a1bf1c60SKunihiko Hayashi uniphier_ahciphy_pxs2_enable(priv, true); 79*a1bf1c60SKunihiko Hayashi 80*a1bf1c60SKunihiko Hayashi /* wait until PLL is ready */ 81*a1bf1c60SKunihiko Hayashi if (priv->data->is_ready_high) 82*a1bf1c60SKunihiko Hayashi ret = readl_poll_timeout(priv->base + CKCTRL, val, 83*a1bf1c60SKunihiko Hayashi (val & CKCTRL_P0_READY), 200, 400); 84*a1bf1c60SKunihiko Hayashi else 85*a1bf1c60SKunihiko Hayashi ret = readl_poll_timeout(priv->base + CKCTRL, val, 86*a1bf1c60SKunihiko Hayashi !(val & CKCTRL_P0_READY), 200, 400); 87*a1bf1c60SKunihiko Hayashi if (ret) { 88*a1bf1c60SKunihiko Hayashi dev_err(priv->dev, "Failed to check whether PHY PLL is ready\n"); 89*a1bf1c60SKunihiko Hayashi uniphier_ahciphy_pxs2_enable(priv, false); 90*a1bf1c60SKunihiko Hayashi } 91*a1bf1c60SKunihiko Hayashi 92*a1bf1c60SKunihiko Hayashi return ret; 93*a1bf1c60SKunihiko Hayashi } 94*a1bf1c60SKunihiko Hayashi 95*a1bf1c60SKunihiko Hayashi static int uniphier_ahciphy_pxs2_power_off(struct uniphier_ahciphy_priv *priv) 96*a1bf1c60SKunihiko Hayashi { 97*a1bf1c60SKunihiko Hayashi uniphier_ahciphy_pxs2_enable(priv, false); 98*a1bf1c60SKunihiko Hayashi 99*a1bf1c60SKunihiko Hayashi return 0; 100*a1bf1c60SKunihiko Hayashi } 101*a1bf1c60SKunihiko Hayashi 102*a1bf1c60SKunihiko Hayashi static int uniphier_ahciphy_pxs3_init(struct uniphier_ahciphy_priv *priv) 103*a1bf1c60SKunihiko Hayashi { 104*a1bf1c60SKunihiko Hayashi int i; 105*a1bf1c60SKunihiko Hayashi u32 val; 106*a1bf1c60SKunihiko Hayashi 107*a1bf1c60SKunihiko Hayashi /* setup port parameter */ 108*a1bf1c60SKunihiko Hayashi val = readl(priv->base + TXCTRL0); 109*a1bf1c60SKunihiko Hayashi val &= ~TXCTRL0_AMP_G3_MASK; 110*a1bf1c60SKunihiko Hayashi val |= FIELD_PREP(TXCTRL0_AMP_G3_MASK, 0x73); 111*a1bf1c60SKunihiko Hayashi val &= ~TXCTRL0_AMP_G2_MASK; 112*a1bf1c60SKunihiko Hayashi val |= FIELD_PREP(TXCTRL0_AMP_G2_MASK, 0x46); 113*a1bf1c60SKunihiko Hayashi val &= ~TXCTRL0_AMP_G1_MASK; 114*a1bf1c60SKunihiko Hayashi val |= FIELD_PREP(TXCTRL0_AMP_G1_MASK, 0x42); 115*a1bf1c60SKunihiko Hayashi writel(val, priv->base + TXCTRL0); 116*a1bf1c60SKunihiko Hayashi 117*a1bf1c60SKunihiko Hayashi val = readl(priv->base + TXCTRL1); 118*a1bf1c60SKunihiko Hayashi val &= ~TXCTRL1_DEEMPH_G3_MASK; 119*a1bf1c60SKunihiko Hayashi val |= FIELD_PREP(TXCTRL1_DEEMPH_G3_MASK, 0x23); 120*a1bf1c60SKunihiko Hayashi val &= ~TXCTRL1_DEEMPH_G2_MASK; 121*a1bf1c60SKunihiko Hayashi val |= FIELD_PREP(TXCTRL1_DEEMPH_G2_MASK, 0x05); 122*a1bf1c60SKunihiko Hayashi val &= ~TXCTRL1_DEEMPH_G1_MASK; 123*a1bf1c60SKunihiko Hayashi val |= FIELD_PREP(TXCTRL1_DEEMPH_G1_MASK, 0x05); 124*a1bf1c60SKunihiko Hayashi 125*a1bf1c60SKunihiko Hayashi val = readl(priv->base + RXCTRL); 126*a1bf1c60SKunihiko Hayashi val &= ~RXCTRL_LOS_LVL_MASK; 127*a1bf1c60SKunihiko Hayashi val |= FIELD_PREP(RXCTRL_LOS_LVL_MASK, 0x9); 128*a1bf1c60SKunihiko Hayashi val &= ~RXCTRL_LOS_BIAS_MASK; 129*a1bf1c60SKunihiko Hayashi val |= FIELD_PREP(RXCTRL_LOS_BIAS_MASK, 0x2); 130*a1bf1c60SKunihiko Hayashi val &= ~RXCTRL_RX_EQ_MASK; 131*a1bf1c60SKunihiko Hayashi val |= FIELD_PREP(RXCTRL_RX_EQ_MASK, 0x1); 132*a1bf1c60SKunihiko Hayashi 133*a1bf1c60SKunihiko Hayashi /* dummy read 25 times to make a wait time for the phy to stabilize */ 134*a1bf1c60SKunihiko Hayashi for (i = 0; i < 25; i++) 135*a1bf1c60SKunihiko Hayashi readl(priv->base + CKCTRL); 136*a1bf1c60SKunihiko Hayashi 137*a1bf1c60SKunihiko Hayashi return 0; 138*a1bf1c60SKunihiko Hayashi } 139*a1bf1c60SKunihiko Hayashi 140*a1bf1c60SKunihiko Hayashi static int uniphier_ahciphy_init(struct phy *phy) 141*a1bf1c60SKunihiko Hayashi { 142*a1bf1c60SKunihiko Hayashi struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy); 143*a1bf1c60SKunihiko Hayashi int ret; 144*a1bf1c60SKunihiko Hayashi 145*a1bf1c60SKunihiko Hayashi ret = clk_prepare_enable(priv->clk_parent); 146*a1bf1c60SKunihiko Hayashi if (ret) 147*a1bf1c60SKunihiko Hayashi return ret; 148*a1bf1c60SKunihiko Hayashi 149*a1bf1c60SKunihiko Hayashi ret = reset_control_deassert(priv->rst_parent); 150*a1bf1c60SKunihiko Hayashi if (ret) 151*a1bf1c60SKunihiko Hayashi goto out_clk_disable; 152*a1bf1c60SKunihiko Hayashi 153*a1bf1c60SKunihiko Hayashi if (priv->data->init) { 154*a1bf1c60SKunihiko Hayashi ret = priv->data->init(priv); 155*a1bf1c60SKunihiko Hayashi if (ret) 156*a1bf1c60SKunihiko Hayashi goto out_rst_assert; 157*a1bf1c60SKunihiko Hayashi } 158*a1bf1c60SKunihiko Hayashi 159*a1bf1c60SKunihiko Hayashi return 0; 160*a1bf1c60SKunihiko Hayashi 161*a1bf1c60SKunihiko Hayashi out_rst_assert: 162*a1bf1c60SKunihiko Hayashi reset_control_assert(priv->rst_parent); 163*a1bf1c60SKunihiko Hayashi out_clk_disable: 164*a1bf1c60SKunihiko Hayashi clk_disable_unprepare(priv->clk_parent); 165*a1bf1c60SKunihiko Hayashi 166*a1bf1c60SKunihiko Hayashi return ret; 167*a1bf1c60SKunihiko Hayashi } 168*a1bf1c60SKunihiko Hayashi 169*a1bf1c60SKunihiko Hayashi static int uniphier_ahciphy_exit(struct phy *phy) 170*a1bf1c60SKunihiko Hayashi { 171*a1bf1c60SKunihiko Hayashi struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy); 172*a1bf1c60SKunihiko Hayashi 173*a1bf1c60SKunihiko Hayashi reset_control_assert(priv->rst_parent); 174*a1bf1c60SKunihiko Hayashi clk_disable_unprepare(priv->clk_parent); 175*a1bf1c60SKunihiko Hayashi 176*a1bf1c60SKunihiko Hayashi return 0; 177*a1bf1c60SKunihiko Hayashi } 178*a1bf1c60SKunihiko Hayashi 179*a1bf1c60SKunihiko Hayashi static int uniphier_ahciphy_power_on(struct phy *phy) 180*a1bf1c60SKunihiko Hayashi { 181*a1bf1c60SKunihiko Hayashi struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy); 182*a1bf1c60SKunihiko Hayashi int ret = 0; 183*a1bf1c60SKunihiko Hayashi 184*a1bf1c60SKunihiko Hayashi ret = clk_prepare_enable(priv->clk); 185*a1bf1c60SKunihiko Hayashi if (ret) 186*a1bf1c60SKunihiko Hayashi return ret; 187*a1bf1c60SKunihiko Hayashi 188*a1bf1c60SKunihiko Hayashi ret = reset_control_deassert(priv->rst); 189*a1bf1c60SKunihiko Hayashi if (ret) 190*a1bf1c60SKunihiko Hayashi goto out_clk_disable; 191*a1bf1c60SKunihiko Hayashi 192*a1bf1c60SKunihiko Hayashi if (priv->data->power_on) { 193*a1bf1c60SKunihiko Hayashi ret = priv->data->power_on(priv); 194*a1bf1c60SKunihiko Hayashi if (ret) 195*a1bf1c60SKunihiko Hayashi goto out_reset_assert; 196*a1bf1c60SKunihiko Hayashi } 197*a1bf1c60SKunihiko Hayashi 198*a1bf1c60SKunihiko Hayashi return 0; 199*a1bf1c60SKunihiko Hayashi 200*a1bf1c60SKunihiko Hayashi out_reset_assert: 201*a1bf1c60SKunihiko Hayashi reset_control_assert(priv->rst); 202*a1bf1c60SKunihiko Hayashi out_clk_disable: 203*a1bf1c60SKunihiko Hayashi clk_disable_unprepare(priv->clk); 204*a1bf1c60SKunihiko Hayashi 205*a1bf1c60SKunihiko Hayashi return ret; 206*a1bf1c60SKunihiko Hayashi } 207*a1bf1c60SKunihiko Hayashi 208*a1bf1c60SKunihiko Hayashi static int uniphier_ahciphy_power_off(struct phy *phy) 209*a1bf1c60SKunihiko Hayashi { 210*a1bf1c60SKunihiko Hayashi struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy); 211*a1bf1c60SKunihiko Hayashi int ret = 0; 212*a1bf1c60SKunihiko Hayashi 213*a1bf1c60SKunihiko Hayashi if (priv->data->power_off) 214*a1bf1c60SKunihiko Hayashi ret = priv->data->power_off(priv); 215*a1bf1c60SKunihiko Hayashi 216*a1bf1c60SKunihiko Hayashi reset_control_assert(priv->rst); 217*a1bf1c60SKunihiko Hayashi clk_disable_unprepare(priv->clk); 218*a1bf1c60SKunihiko Hayashi 219*a1bf1c60SKunihiko Hayashi return ret; 220*a1bf1c60SKunihiko Hayashi } 221*a1bf1c60SKunihiko Hayashi 222*a1bf1c60SKunihiko Hayashi static const struct phy_ops uniphier_ahciphy_ops = { 223*a1bf1c60SKunihiko Hayashi .init = uniphier_ahciphy_init, 224*a1bf1c60SKunihiko Hayashi .exit = uniphier_ahciphy_exit, 225*a1bf1c60SKunihiko Hayashi .power_on = uniphier_ahciphy_power_on, 226*a1bf1c60SKunihiko Hayashi .power_off = uniphier_ahciphy_power_off, 227*a1bf1c60SKunihiko Hayashi .owner = THIS_MODULE, 228*a1bf1c60SKunihiko Hayashi }; 229*a1bf1c60SKunihiko Hayashi 230*a1bf1c60SKunihiko Hayashi static int uniphier_ahciphy_probe(struct platform_device *pdev) 231*a1bf1c60SKunihiko Hayashi { 232*a1bf1c60SKunihiko Hayashi struct device *dev = &pdev->dev; 233*a1bf1c60SKunihiko Hayashi struct uniphier_ahciphy_priv *priv; 234*a1bf1c60SKunihiko Hayashi struct phy *phy; 235*a1bf1c60SKunihiko Hayashi struct phy_provider *phy_provider; 236*a1bf1c60SKunihiko Hayashi 237*a1bf1c60SKunihiko Hayashi priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 238*a1bf1c60SKunihiko Hayashi if (!priv) 239*a1bf1c60SKunihiko Hayashi return -ENOMEM; 240*a1bf1c60SKunihiko Hayashi 241*a1bf1c60SKunihiko Hayashi priv->dev = dev; 242*a1bf1c60SKunihiko Hayashi priv->data = of_device_get_match_data(dev); 243*a1bf1c60SKunihiko Hayashi if (WARN_ON(!priv->data)) 244*a1bf1c60SKunihiko Hayashi return -EINVAL; 245*a1bf1c60SKunihiko Hayashi 246*a1bf1c60SKunihiko Hayashi priv->base = devm_platform_ioremap_resource(pdev, 0); 247*a1bf1c60SKunihiko Hayashi if (IS_ERR(priv->base)) 248*a1bf1c60SKunihiko Hayashi return PTR_ERR(priv->base); 249*a1bf1c60SKunihiko Hayashi 250*a1bf1c60SKunihiko Hayashi priv->clk_parent = devm_clk_get(dev, "link"); 251*a1bf1c60SKunihiko Hayashi if (IS_ERR(priv->clk_parent)) 252*a1bf1c60SKunihiko Hayashi return PTR_ERR(priv->clk_parent); 253*a1bf1c60SKunihiko Hayashi 254*a1bf1c60SKunihiko Hayashi if (priv->data->is_phy_clk) { 255*a1bf1c60SKunihiko Hayashi priv->clk = devm_clk_get(dev, "phy"); 256*a1bf1c60SKunihiko Hayashi if (IS_ERR(priv->clk)) 257*a1bf1c60SKunihiko Hayashi return PTR_ERR(priv->clk); 258*a1bf1c60SKunihiko Hayashi } 259*a1bf1c60SKunihiko Hayashi 260*a1bf1c60SKunihiko Hayashi priv->rst_parent = devm_reset_control_get_shared(dev, "link"); 261*a1bf1c60SKunihiko Hayashi if (IS_ERR(priv->rst_parent)) 262*a1bf1c60SKunihiko Hayashi return PTR_ERR(priv->rst_parent); 263*a1bf1c60SKunihiko Hayashi 264*a1bf1c60SKunihiko Hayashi priv->rst = devm_reset_control_get_shared(dev, "phy"); 265*a1bf1c60SKunihiko Hayashi if (IS_ERR(priv->rst)) 266*a1bf1c60SKunihiko Hayashi return PTR_ERR(priv->rst); 267*a1bf1c60SKunihiko Hayashi 268*a1bf1c60SKunihiko Hayashi phy = devm_phy_create(dev, dev->of_node, &uniphier_ahciphy_ops); 269*a1bf1c60SKunihiko Hayashi if (IS_ERR(phy)) { 270*a1bf1c60SKunihiko Hayashi dev_err(dev, "failed to create phy\n"); 271*a1bf1c60SKunihiko Hayashi return PTR_ERR(phy); 272*a1bf1c60SKunihiko Hayashi } 273*a1bf1c60SKunihiko Hayashi 274*a1bf1c60SKunihiko Hayashi phy_set_drvdata(phy, priv); 275*a1bf1c60SKunihiko Hayashi phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 276*a1bf1c60SKunihiko Hayashi if (IS_ERR(phy_provider)) 277*a1bf1c60SKunihiko Hayashi return PTR_ERR(phy_provider); 278*a1bf1c60SKunihiko Hayashi 279*a1bf1c60SKunihiko Hayashi return 0; 280*a1bf1c60SKunihiko Hayashi } 281*a1bf1c60SKunihiko Hayashi 282*a1bf1c60SKunihiko Hayashi static const struct uniphier_ahciphy_soc_data uniphier_pxs2_data = { 283*a1bf1c60SKunihiko Hayashi .power_on = uniphier_ahciphy_pxs2_power_on, 284*a1bf1c60SKunihiko Hayashi .power_off = uniphier_ahciphy_pxs2_power_off, 285*a1bf1c60SKunihiko Hayashi .is_ready_high = false, 286*a1bf1c60SKunihiko Hayashi .is_phy_clk = false, 287*a1bf1c60SKunihiko Hayashi }; 288*a1bf1c60SKunihiko Hayashi 289*a1bf1c60SKunihiko Hayashi static const struct uniphier_ahciphy_soc_data uniphier_pxs3_data = { 290*a1bf1c60SKunihiko Hayashi .init = uniphier_ahciphy_pxs3_init, 291*a1bf1c60SKunihiko Hayashi .power_on = uniphier_ahciphy_pxs2_power_on, 292*a1bf1c60SKunihiko Hayashi .power_off = uniphier_ahciphy_pxs2_power_off, 293*a1bf1c60SKunihiko Hayashi .is_ready_high = true, 294*a1bf1c60SKunihiko Hayashi .is_phy_clk = true, 295*a1bf1c60SKunihiko Hayashi }; 296*a1bf1c60SKunihiko Hayashi 297*a1bf1c60SKunihiko Hayashi static const struct of_device_id uniphier_ahciphy_match[] = { 298*a1bf1c60SKunihiko Hayashi { 299*a1bf1c60SKunihiko Hayashi .compatible = "socionext,uniphier-pxs2-ahci-phy", 300*a1bf1c60SKunihiko Hayashi .data = &uniphier_pxs2_data, 301*a1bf1c60SKunihiko Hayashi }, 302*a1bf1c60SKunihiko Hayashi { 303*a1bf1c60SKunihiko Hayashi .compatible = "socionext,uniphier-pxs3-ahci-phy", 304*a1bf1c60SKunihiko Hayashi .data = &uniphier_pxs3_data, 305*a1bf1c60SKunihiko Hayashi }, 306*a1bf1c60SKunihiko Hayashi { /* Sentinel */ }, 307*a1bf1c60SKunihiko Hayashi }; 308*a1bf1c60SKunihiko Hayashi MODULE_DEVICE_TABLE(of, uniphier_ahciphy_match); 309*a1bf1c60SKunihiko Hayashi 310*a1bf1c60SKunihiko Hayashi static struct platform_driver uniphier_ahciphy_driver = { 311*a1bf1c60SKunihiko Hayashi .probe = uniphier_ahciphy_probe, 312*a1bf1c60SKunihiko Hayashi .driver = { 313*a1bf1c60SKunihiko Hayashi .name = "uniphier-ahci-phy", 314*a1bf1c60SKunihiko Hayashi .of_match_table = uniphier_ahciphy_match, 315*a1bf1c60SKunihiko Hayashi }, 316*a1bf1c60SKunihiko Hayashi }; 317*a1bf1c60SKunihiko Hayashi module_platform_driver(uniphier_ahciphy_driver); 318*a1bf1c60SKunihiko Hayashi 319*a1bf1c60SKunihiko Hayashi MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); 320*a1bf1c60SKunihiko Hayashi MODULE_DESCRIPTION("UniPhier PHY driver for AHCI controller"); 321*a1bf1c60SKunihiko Hayashi MODULE_LICENSE("GPL v2"); 322