1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * UFS PHY driver for Samsung SoC 4 * 5 * Copyright (C) 2020 Samsung Electronics Co., Ltd. 6 * Author: Seungwon Jeon <essuuj@gmail.com> 7 * Author: Alim Akhtar <alim.akhtar@samsung.com> 8 * 9 */ 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/of.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/module.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 22 #include "phy-samsung-ufs.h" 23 24 #define for_each_phy_lane(phy, i) \ 25 for (i = 0; i < (phy)->lane_cnt; i++) 26 #define for_each_phy_cfg(cfg) \ 27 for (; (cfg)->id; (cfg)++) 28 29 #define PHY_DEF_LANE_CNT 1 30 31 void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, 32 const struct samsung_ufs_phy_cfg *cfg, 33 u8 lane) 34 { 35 enum {LANE_0, LANE_1}; /* lane index */ 36 37 switch (lane) { 38 case LANE_0: 39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); 40 break; 41 case LANE_1: 42 if (cfg->id == PHY_TRSV_BLK) 43 writel(cfg->val, (phy)->reg_pma + cfg->off_1); 44 break; 45 } 46 } 47 48 int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane) 49 { 50 struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy); 51 const unsigned int timeout_us = 100000; 52 const unsigned int sleep_us = 10; 53 u32 val; 54 int err; 55 56 err = readl_poll_timeout( 57 ufs_phy->reg_pma + PHY_APB_ADDR(PHY_PLL_LOCK_STATUS), 58 val, (val & PHY_PLL_LOCK_BIT), sleep_us, timeout_us); 59 if (err) { 60 dev_err(ufs_phy->dev, 61 "failed to get phy pll lock acquisition %d\n", err); 62 goto out; 63 } 64 65 err = readl_poll_timeout( 66 ufs_phy->reg_pma + 67 PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset), 68 val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us); 69 if (err) 70 dev_err(ufs_phy->dev, 71 "failed to get phy cdr lock acquisition %d\n", err); 72 out: 73 return err; 74 } 75 76 static int samsung_ufs_phy_calibrate(struct phy *phy) 77 { 78 struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy); 79 const struct samsung_ufs_phy_cfg * const *cfgs = ufs_phy->cfgs; 80 const struct samsung_ufs_phy_cfg *cfg; 81 int err = 0; 82 int i; 83 84 if (unlikely(ufs_phy->ufs_phy_state < CFG_PRE_INIT || 85 ufs_phy->ufs_phy_state >= CFG_TAG_MAX)) { 86 dev_err(ufs_phy->dev, "invalid phy config index %d\n", ufs_phy->ufs_phy_state); 87 return -EINVAL; 88 } 89 90 cfg = cfgs[ufs_phy->ufs_phy_state]; 91 if (!cfg) 92 goto out; 93 94 for_each_phy_cfg(cfg) { 95 for_each_phy_lane(ufs_phy, i) { 96 samsung_ufs_phy_config(ufs_phy, cfg, i); 97 } 98 } 99 100 for_each_phy_lane(ufs_phy, i) { 101 if (ufs_phy->ufs_phy_state == CFG_PRE_INIT && 102 ufs_phy->drvdata->wait_for_cal) { 103 err = ufs_phy->drvdata->wait_for_cal(phy, i); 104 if (err) 105 goto out; 106 } 107 108 if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS && 109 ufs_phy->drvdata->wait_for_cdr) { 110 err = ufs_phy->drvdata->wait_for_cdr(phy, i); 111 if (err) 112 goto out; 113 } 114 } 115 116 /** 117 * In Samsung ufshci, PHY need to be calibrated at different 118 * stages / state mainly before Linkstartup, after Linkstartup, 119 * before power mode change and after power mode change. 120 * Below state machine to make sure to calibrate PHY in each 121 * state. Here after configuring PHY in a given state, will 122 * change the state to next state so that next state phy 123 * calibration value can be programed 124 */ 125 out: 126 switch (ufs_phy->ufs_phy_state) { 127 case CFG_PRE_INIT: 128 ufs_phy->ufs_phy_state = CFG_POST_INIT; 129 break; 130 case CFG_POST_INIT: 131 ufs_phy->ufs_phy_state = CFG_PRE_PWR_HS; 132 break; 133 case CFG_PRE_PWR_HS: 134 ufs_phy->ufs_phy_state = CFG_POST_PWR_HS; 135 break; 136 case CFG_POST_PWR_HS: 137 /* Change back to INIT state */ 138 ufs_phy->ufs_phy_state = CFG_PRE_INIT; 139 break; 140 default: 141 dev_err(ufs_phy->dev, "wrong state for phy calibration\n"); 142 } 143 144 return err; 145 } 146 147 static int samsung_ufs_phy_clks_init(struct samsung_ufs_phy *phy) 148 { 149 int i; 150 const struct samsung_ufs_phy_drvdata *drvdata = phy->drvdata; 151 int num_clks = drvdata->num_clks; 152 153 phy->clks = devm_kcalloc(phy->dev, num_clks, sizeof(*phy->clks), 154 GFP_KERNEL); 155 if (!phy->clks) 156 return -ENOMEM; 157 158 for (i = 0; i < num_clks; i++) 159 phy->clks[i].id = drvdata->clk_list[i]; 160 161 return devm_clk_bulk_get(phy->dev, num_clks, phy->clks); 162 } 163 164 static int samsung_ufs_phy_init(struct phy *phy) 165 { 166 struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); 167 168 ss_phy->lane_cnt = phy->attrs.bus_width; 169 ss_phy->ufs_phy_state = CFG_PRE_INIT; 170 171 return 0; 172 } 173 174 static int samsung_ufs_phy_power_on(struct phy *phy) 175 { 176 struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); 177 int ret; 178 179 samsung_ufs_phy_ctrl_isol(ss_phy, false); 180 181 ret = clk_bulk_prepare_enable(ss_phy->drvdata->num_clks, ss_phy->clks); 182 if (ret) { 183 dev_err(ss_phy->dev, "failed to enable ufs phy clocks\n"); 184 return ret; 185 } 186 187 if (ss_phy->ufs_phy_state == CFG_PRE_INIT) { 188 ret = samsung_ufs_phy_calibrate(phy); 189 if (ret) 190 dev_err(ss_phy->dev, "ufs phy calibration failed\n"); 191 } 192 193 return ret; 194 } 195 196 static int samsung_ufs_phy_power_off(struct phy *phy) 197 { 198 struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); 199 200 clk_bulk_disable_unprepare(ss_phy->drvdata->num_clks, ss_phy->clks); 201 202 samsung_ufs_phy_ctrl_isol(ss_phy, true); 203 204 return 0; 205 } 206 207 static int samsung_ufs_phy_set_mode(struct phy *generic_phy, 208 enum phy_mode mode, int submode) 209 { 210 struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(generic_phy); 211 212 ss_phy->mode = PHY_MODE_INVALID; 213 214 if (mode > 0) 215 ss_phy->mode = mode; 216 217 return 0; 218 } 219 220 static int samsung_ufs_phy_notify_state(struct phy *phy, 221 union phy_notify state) 222 { 223 struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy); 224 const struct samsung_ufs_phy_cfg *cfg; 225 int i, err = -EINVAL; 226 227 if (!ufs_phy->cfgs_hibern8) 228 return 0; 229 230 if (state.ufs_state == PHY_UFS_HIBERN8_ENTER) 231 cfg = ufs_phy->cfgs_hibern8[CFG_POST_HIBERN8_ENTER]; 232 else if (state.ufs_state == PHY_UFS_HIBERN8_EXIT) 233 cfg = ufs_phy->cfgs_hibern8[CFG_PRE_HIBERN8_EXIT]; 234 else 235 goto err_out; 236 237 for_each_phy_cfg(cfg) { 238 for_each_phy_lane(ufs_phy, i) { 239 samsung_ufs_phy_config(ufs_phy, cfg, i); 240 } 241 } 242 243 if (state.ufs_state == PHY_UFS_HIBERN8_EXIT) { 244 for_each_phy_lane(ufs_phy, i) { 245 if (ufs_phy->drvdata->wait_for_cdr) { 246 err = ufs_phy->drvdata->wait_for_cdr(phy, i); 247 if (err) 248 goto err_out; 249 } 250 } 251 } 252 253 return 0; 254 err_out: 255 return err; 256 } 257 258 static int samsung_ufs_phy_exit(struct phy *phy) 259 { 260 struct samsung_ufs_phy *ss_phy = get_samsung_ufs_phy(phy); 261 262 ss_phy->ufs_phy_state = CFG_TAG_MAX; 263 264 return 0; 265 } 266 267 static const struct phy_ops samsung_ufs_phy_ops = { 268 .init = samsung_ufs_phy_init, 269 .exit = samsung_ufs_phy_exit, 270 .power_on = samsung_ufs_phy_power_on, 271 .power_off = samsung_ufs_phy_power_off, 272 .calibrate = samsung_ufs_phy_calibrate, 273 .set_mode = samsung_ufs_phy_set_mode, 274 .notify_phystate = samsung_ufs_phy_notify_state, 275 .owner = THIS_MODULE, 276 }; 277 278 static const struct of_device_id samsung_ufs_phy_match[]; 279 280 static int samsung_ufs_phy_probe(struct platform_device *pdev) 281 { 282 struct device *dev = &pdev->dev; 283 const struct of_device_id *match; 284 struct samsung_ufs_phy *phy; 285 struct phy *gen_phy; 286 struct phy_provider *phy_provider; 287 const struct samsung_ufs_phy_drvdata *drvdata; 288 u32 isol_offset; 289 int err = 0; 290 291 match = of_match_node(samsung_ufs_phy_match, dev->of_node); 292 if (!match) { 293 err = -EINVAL; 294 dev_err(dev, "failed to get match_node\n"); 295 goto out; 296 } 297 298 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); 299 if (!phy) { 300 err = -ENOMEM; 301 goto out; 302 } 303 304 phy->reg_pma = devm_platform_ioremap_resource_byname(pdev, "phy-pma"); 305 if (IS_ERR(phy->reg_pma)) { 306 err = PTR_ERR(phy->reg_pma); 307 goto out; 308 } 309 310 phy->reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, 311 "samsung,pmu-syscon"); 312 if (IS_ERR(phy->reg_pmu)) { 313 err = PTR_ERR(phy->reg_pmu); 314 dev_err(dev, "failed syscon remap for pmu\n"); 315 goto out; 316 } 317 318 gen_phy = devm_phy_create(dev, NULL, &samsung_ufs_phy_ops); 319 if (IS_ERR(gen_phy)) { 320 err = PTR_ERR(gen_phy); 321 dev_err(dev, "failed to create PHY for ufs-phy\n"); 322 goto out; 323 } 324 325 drvdata = match->data; 326 phy->dev = dev; 327 phy->drvdata = drvdata; 328 phy->cfgs = drvdata->cfgs; 329 phy->cfgs_hibern8 = drvdata->cfgs_hibern8; 330 memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol)); 331 332 if (!of_property_read_u32_index(dev->of_node, "samsung,pmu-syscon", 1, 333 &isol_offset)) 334 phy->isol.offset = isol_offset; 335 336 phy->lane_cnt = PHY_DEF_LANE_CNT; 337 338 err = samsung_ufs_phy_clks_init(phy); 339 if (err) { 340 dev_err(dev, "failed to get phy clocks\n"); 341 goto out; 342 } 343 344 phy_set_drvdata(gen_phy, phy); 345 346 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 347 if (IS_ERR(phy_provider)) { 348 err = PTR_ERR(phy_provider); 349 dev_err(dev, "failed to register phy-provider\n"); 350 goto out; 351 } 352 out: 353 return err; 354 } 355 356 static const struct of_device_id samsung_ufs_phy_match[] = { 357 { 358 .compatible = "google,gs101-ufs-phy", 359 .data = &tensor_gs101_ufs_phy, 360 }, { 361 .compatible = "samsung,exynos7-ufs-phy", 362 .data = &exynos7_ufs_phy, 363 }, { 364 .compatible = "samsung,exynosautov9-ufs-phy", 365 .data = &exynosautov9_ufs_phy, 366 }, { 367 .compatible = "samsung,exynosautov920-ufs-phy", 368 .data = &exynosautov920_ufs_phy, 369 }, { 370 .compatible = "tesla,fsd-ufs-phy", 371 .data = &fsd_ufs_phy, 372 }, 373 {}, 374 }; 375 MODULE_DEVICE_TABLE(of, samsung_ufs_phy_match); 376 377 static struct platform_driver samsung_ufs_phy_driver = { 378 .probe = samsung_ufs_phy_probe, 379 .driver = { 380 .name = "samsung-ufs-phy", 381 .of_match_table = samsung_ufs_phy_match, 382 }, 383 }; 384 module_platform_driver(samsung_ufs_phy_driver); 385 MODULE_DESCRIPTION("Samsung SoC UFS PHY Driver"); 386 MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>"); 387 MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>"); 388 MODULE_LICENSE("GPL v2"); 389