1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * UFS PHY driver data for Samsung EXYNOS7 SoC 4 * 5 * Copyright (C) 2020 Samsung Electronics Co., Ltd. 6 */ 7 8 #include "phy-samsung-ufs.h" 9 10 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720 11 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 12 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) 13 14 #define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e 15 16 /* Calibration for phy initialization */ 17 static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = { 18 PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), 19 PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY), 20 PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY), 21 PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY), 22 PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY), 23 PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY), 24 PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY), 25 PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY), 26 PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY), 27 PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY), 28 PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY), 29 PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY), 30 PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY), 31 PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY), 32 END_UFS_PHY_CFG 33 }; 34 35 /* Calibration for HS mode series A/B */ 36 static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = { 37 PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY), 38 PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY), 39 PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY), 40 /* Setting order: 1st(0x16, 2nd(0x15) */ 41 PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY), 42 PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY), 43 PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY), 44 PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY), 45 PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY), 46 PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY), 47 PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A), 48 PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B), 49 PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY), 50 PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY), 51 PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A), 52 PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B), 53 PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A), 54 PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B), 55 END_UFS_PHY_CFG 56 }; 57 58 /* Calibration for HS mode series A/B atfer PMC */ 59 static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = { 60 PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY), 61 PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY), 62 END_UFS_PHY_CFG 63 }; 64 65 static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = { 66 [CFG_PRE_INIT] = exynos7_pre_init_cfg, 67 [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg, 68 [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg, 69 }; 70 71 static const char * const exynos7_ufs_phy_clks[] = { 72 "tx0_symbol_clk", "rx0_symbol_clk", "rx1_symbol_clk", "ref_clk", 73 }; 74 75 const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = { 76 .cfgs = exynos7_ufs_phy_cfgs, 77 .isol = { 78 .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL, 79 .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK, 80 .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN, 81 }, 82 .clk_list = exynos7_ufs_phy_clks, 83 .num_clks = ARRAY_SIZE(exynos7_ufs_phy_clks), 84 .cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, 85 .wait_for_cdr = samsung_ufs_phy_wait_for_lock_acq, 86 }; 87