1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd 6 * Copyright (C) 2024 Collabora Ltd 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 #include <linux/usb/ch9.h> 25 #include <linux/usb/typec_dp.h> 26 #include <linux/usb/typec_mux.h> 27 28 /* USBDP PHY Register Definitions */ 29 #define UDPHY_PCS 0x4000 30 #define UDPHY_PMA 0x8000 31 32 /* VO0 GRF Registers */ 33 #define DP_SINK_HPD_CFG BIT(11) 34 #define DP_SINK_HPD_SEL BIT(10) 35 #define DP_AUX_DIN_SEL BIT(9) 36 #define DP_AUX_DOUT_SEL BIT(8) 37 #define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) 38 #define DP_LANE_SEL_ALL GENMASK(7, 0) 39 40 /* PMA CMN Registers */ 41 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ 42 #define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) 43 #define CMN_DP_LANE_EN_N(n) BIT(n) 44 #define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) 45 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0) 46 47 #define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */ 48 #define CMN_DP_TX_LINK_BW GENMASK(6, 5) 49 #define CMN_DP_TX_LANE_SWAP_EN BIT(2) 50 51 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ 52 #define CMN_ROPLL_SSC_EN BIT(1) 53 #define CMN_LCPLL_SSC_EN BIT(0) 54 55 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ 56 #define CMN_ANA_LCPLL_LOCK_DONE BIT(7) 57 #define CMN_ANA_LCPLL_AFC_DONE BIT(6) 58 59 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ 60 #define CMN_ANA_ROPLL_LOCK_DONE BIT(1) 61 #define CMN_ANA_ROPLL_AFC_DONE BIT(0) 62 63 #define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ 64 #define CMN_DP_INIT_RSTN BIT(3) 65 #define CMN_DP_CMN_RSTN BIT(2) 66 #define CMN_CDR_WTCHDG_EN BIT(1) 67 #define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) 68 69 #define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ 70 #define LN_ANA_TX_SER_TXCLK_INV BIT(1) 71 72 #define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ 73 #define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) 74 75 #define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ 76 #define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) 77 78 #define BIT_WRITEABLE_SHIFT 16 79 #define PHY_AUX_DP_DATA_POL_NORMAL 0 80 #define PHY_AUX_DP_DATA_POL_INVERT 1 81 #define PHY_LANE_MUX_USB 0 82 #define PHY_LANE_MUX_DP 1 83 84 enum { 85 DP_BW_RBR, 86 DP_BW_HBR, 87 DP_BW_HBR2, 88 DP_BW_HBR3, 89 }; 90 91 enum { 92 UDPHY_MODE_NONE = 0, 93 UDPHY_MODE_USB = BIT(0), 94 UDPHY_MODE_DP = BIT(1), 95 UDPHY_MODE_DP_USB = BIT(1) | BIT(0), 96 }; 97 98 struct rk_udphy_grf_reg { 99 unsigned int offset; 100 unsigned int disable; 101 unsigned int enable; 102 }; 103 104 #define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \ 105 {\ 106 offset, \ 107 FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \ 108 FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \ 109 } 110 111 #define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \ 112 _RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable) 113 114 struct rk_udphy_grf_cfg { 115 /* u2phy-grf */ 116 struct rk_udphy_grf_reg bvalid_phy_con; 117 struct rk_udphy_grf_reg bvalid_grf_con; 118 119 /* usb-grf */ 120 struct rk_udphy_grf_reg usb3otg0_cfg; 121 struct rk_udphy_grf_reg usb3otg1_cfg; 122 123 /* usbdpphy-grf */ 124 struct rk_udphy_grf_reg low_pwrn; 125 struct rk_udphy_grf_reg rx_lfps; 126 }; 127 128 struct rk_udphy_vogrf_cfg { 129 /* vo-grf */ 130 struct rk_udphy_grf_reg hpd_trigger; 131 u32 dp_lane_reg; 132 }; 133 134 struct rk_udphy_dp_tx_drv_ctrl { 135 u32 trsv_reg0204; 136 u32 trsv_reg0205; 137 u32 trsv_reg0206; 138 u32 trsv_reg0207; 139 }; 140 141 struct rk_udphy_cfg { 142 unsigned int num_phys; 143 unsigned int phy_ids[2]; 144 /* resets to be requested */ 145 const char * const *rst_list; 146 int num_rsts; 147 148 struct rk_udphy_grf_cfg grfcfg; 149 struct rk_udphy_vogrf_cfg vogrfcfg[2]; 150 const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; 151 const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4]; 152 }; 153 154 struct rk_udphy { 155 struct device *dev; 156 struct regmap *pma_regmap; 157 struct regmap *u2phygrf; 158 struct regmap *udphygrf; 159 struct regmap *usbgrf; 160 struct regmap *vogrf; 161 struct typec_switch_dev *sw; 162 struct typec_mux_dev *mux; 163 struct mutex mutex; /* mutex to protect access to individual PHYs */ 164 165 /* clocks and rests */ 166 int num_clks; 167 struct clk_bulk_data *clks; 168 struct clk *refclk; 169 int num_rsts; 170 struct reset_control_bulk_data *rsts; 171 172 /* PHY status management */ 173 bool flip; 174 bool mode_change; 175 u8 mode; 176 u8 status; 177 178 /* utilized for USB */ 179 bool hs; /* flag for high-speed */ 180 181 /* utilized for DP */ 182 struct gpio_desc *sbu1_dc_gpio; 183 struct gpio_desc *sbu2_dc_gpio; 184 u32 lane_mux_sel[4]; 185 u32 dp_lane_sel[4]; 186 u32 dp_aux_dout_sel; 187 u32 dp_aux_din_sel; 188 bool dp_sink_hpd_sel; 189 bool dp_sink_hpd_cfg; 190 u8 bw; 191 int id; 192 193 bool dp_in_use; 194 195 /* PHY const config */ 196 const struct rk_udphy_cfg *cfgs; 197 198 /* PHY devices */ 199 struct phy *phy_dp; 200 struct phy *phy_u3; 201 }; 202 203 static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = { 204 /* voltage swing 0, pre-emphasis 0->3 */ 205 { 206 { 0x20, 0x10, 0x42, 0xe5 }, 207 { 0x26, 0x14, 0x42, 0xe5 }, 208 { 0x29, 0x18, 0x42, 0xe5 }, 209 { 0x2b, 0x1c, 0x43, 0xe7 }, 210 }, 211 212 /* voltage swing 1, pre-emphasis 0->2 */ 213 { 214 { 0x23, 0x10, 0x42, 0xe7 }, 215 { 0x2a, 0x17, 0x43, 0xe7 }, 216 { 0x2b, 0x1a, 0x43, 0xe7 }, 217 }, 218 219 /* voltage swing 2, pre-emphasis 0->1 */ 220 { 221 { 0x27, 0x10, 0x42, 0xe7 }, 222 { 0x2b, 0x17, 0x43, 0xe7 }, 223 }, 224 225 /* voltage swing 3, pre-emphasis 0 */ 226 { 227 { 0x29, 0x10, 0x43, 0xe7 }, 228 }, 229 }; 230 231 static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = { 232 /* voltage swing 0, pre-emphasis 0->3 */ 233 { 234 { 0x20, 0x10, 0x42, 0xe5 }, 235 { 0x26, 0x14, 0x42, 0xe5 }, 236 { 0x29, 0x18, 0x42, 0xe5 }, 237 { 0x2b, 0x1c, 0x43, 0xe7 }, 238 }, 239 240 /* voltage swing 1, pre-emphasis 0->2 */ 241 { 242 { 0x23, 0x10, 0x42, 0xe7 }, 243 { 0x2a, 0x17, 0x43, 0xe7 }, 244 { 0x2b, 0x1a, 0x43, 0xe7 }, 245 }, 246 247 /* voltage swing 2, pre-emphasis 0->1 */ 248 { 249 { 0x27, 0x10, 0x43, 0x67 }, 250 { 0x2b, 0x17, 0x43, 0xe7 }, 251 }, 252 253 /* voltage swing 3, pre-emphasis 0 */ 254 { 255 { 0x29, 0x10, 0x43, 0xe7 }, 256 }, 257 }; 258 259 static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = { 260 /* voltage swing 0, pre-emphasis 0->3 */ 261 { 262 { 0x21, 0x10, 0x42, 0xe5 }, 263 { 0x26, 0x14, 0x42, 0xe5 }, 264 { 0x26, 0x16, 0x43, 0xe5 }, 265 { 0x2a, 0x19, 0x43, 0xe7 }, 266 }, 267 268 /* voltage swing 1, pre-emphasis 0->2 */ 269 { 270 { 0x24, 0x10, 0x42, 0xe7 }, 271 { 0x2a, 0x17, 0x43, 0xe7 }, 272 { 0x2b, 0x1a, 0x43, 0xe7 }, 273 }, 274 275 /* voltage swing 2, pre-emphasis 0->1 */ 276 { 277 { 0x28, 0x10, 0x42, 0xe7 }, 278 { 0x2b, 0x17, 0x43, 0xe7 }, 279 }, 280 281 /* voltage swing 3, pre-emphasis 0 */ 282 { 283 { 0x28, 0x10, 0x43, 0xe7 }, 284 }, 285 }; 286 287 static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = { 288 /* voltage swing 0, pre-emphasis 0->3 */ 289 { 290 { 0x21, 0x10, 0x42, 0xe5 }, 291 { 0x26, 0x14, 0x42, 0xe5 }, 292 { 0x26, 0x16, 0x43, 0xe5 }, 293 { 0x29, 0x18, 0x43, 0xe7 }, 294 }, 295 296 /* voltage swing 1, pre-emphasis 0->2 */ 297 { 298 { 0x24, 0x10, 0x42, 0xe7 }, 299 { 0x2a, 0x18, 0x43, 0xe7 }, 300 { 0x2b, 0x1b, 0x43, 0xe7 } 301 }, 302 303 /* voltage swing 2, pre-emphasis 0->1 */ 304 { 305 { 0x27, 0x10, 0x42, 0xe7 }, 306 { 0x2b, 0x18, 0x43, 0xe7 } 307 }, 308 309 /* voltage swing 3, pre-emphasis 0 */ 310 { 311 { 0x28, 0x10, 0x43, 0xe7 }, 312 }, 313 }; 314 315 static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = { 316 {0x0090, 0x68}, {0x0094, 0x68}, 317 {0x0128, 0x24}, {0x012c, 0x44}, 318 {0x0130, 0x3f}, {0x0134, 0x44}, 319 {0x015c, 0xa9}, {0x0160, 0x71}, 320 {0x0164, 0x71}, {0x0168, 0xa9}, 321 {0x0174, 0xa9}, {0x0178, 0x71}, 322 {0x017c, 0x71}, {0x0180, 0xa9}, 323 {0x018c, 0x41}, {0x0190, 0x00}, 324 {0x0194, 0x05}, {0x01ac, 0x2a}, 325 {0x01b0, 0x17}, {0x01b4, 0x17}, 326 {0x01b8, 0x2a}, {0x01c8, 0x04}, 327 {0x01cc, 0x08}, {0x01d0, 0x08}, 328 {0x01d4, 0x04}, {0x01d8, 0x20}, 329 {0x01dc, 0x01}, {0x01e0, 0x09}, 330 {0x01e4, 0x03}, {0x01f0, 0x29}, 331 {0x01f4, 0x02}, {0x01f8, 0x02}, 332 {0x01fc, 0x29}, {0x0208, 0x2a}, 333 {0x020c, 0x17}, {0x0210, 0x17}, 334 {0x0214, 0x2a}, {0x0224, 0x20}, 335 {0x03f0, 0x0a}, {0x03f4, 0x07}, 336 {0x03f8, 0x07}, {0x03fc, 0x0c}, 337 {0x0404, 0x12}, {0x0408, 0x1a}, 338 {0x040c, 0x1a}, {0x0410, 0x3f}, 339 {0x0ce0, 0x68}, {0x0ce8, 0xd0}, 340 {0x0cf0, 0x87}, {0x0cf8, 0x70}, 341 {0x0d00, 0x70}, {0x0d08, 0xa9}, 342 {0x1ce0, 0x68}, {0x1ce8, 0xd0}, 343 {0x1cf0, 0x87}, {0x1cf8, 0x70}, 344 {0x1d00, 0x70}, {0x1d08, 0xa9}, 345 {0x0a3c, 0xd0}, {0x0a44, 0xd0}, 346 {0x0a48, 0x01}, {0x0a4c, 0x0d}, 347 {0x0a54, 0xe0}, {0x0a5c, 0xe0}, 348 {0x0a64, 0xa8}, {0x1a3c, 0xd0}, 349 {0x1a44, 0xd0}, {0x1a48, 0x01}, 350 {0x1a4c, 0x0d}, {0x1a54, 0xe0}, 351 {0x1a5c, 0xe0}, {0x1a64, 0xa8} 352 }; 353 354 static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = { 355 {0x0830, 0x07}, {0x085c, 0x80}, 356 {0x1030, 0x07}, {0x105c, 0x80}, 357 {0x1830, 0x07}, {0x185c, 0x80}, 358 {0x2030, 0x07}, {0x205c, 0x80}, 359 {0x0228, 0x38}, {0x0104, 0x44}, 360 {0x0248, 0x44}, {0x038c, 0x02}, 361 {0x0878, 0x04}, {0x1878, 0x04}, 362 {0x0898, 0x77}, {0x1898, 0x77}, 363 {0x0054, 0x01}, {0x00e0, 0x38}, 364 {0x0060, 0x24}, {0x0064, 0x77}, 365 {0x0070, 0x76}, {0x0234, 0xe8}, 366 {0x0af4, 0x15}, {0x1af4, 0x15}, 367 {0x081c, 0xe5}, {0x181c, 0xe5}, 368 {0x099c, 0x48}, {0x199c, 0x48}, 369 {0x09a4, 0x07}, {0x09a8, 0x22}, 370 {0x19a4, 0x07}, {0x19a8, 0x22}, 371 {0x09b8, 0x3e}, {0x19b8, 0x3e}, 372 {0x09e4, 0x02}, {0x19e4, 0x02}, 373 {0x0a34, 0x1e}, {0x1a34, 0x1e}, 374 {0x0a98, 0x2f}, {0x1a98, 0x2f}, 375 {0x0c30, 0x0e}, {0x0c48, 0x06}, 376 {0x1c30, 0x0e}, {0x1c48, 0x06}, 377 {0x028c, 0x18}, {0x0af0, 0x00}, 378 {0x1af0, 0x00} 379 }; 380 381 static const struct reg_sequence rk_udphy_init_sequence[] = { 382 {0x0104, 0x44}, {0x0234, 0xe8}, 383 {0x0248, 0x44}, {0x028c, 0x18}, 384 {0x081c, 0xe5}, {0x0878, 0x00}, 385 {0x0994, 0x1c}, {0x0af0, 0x00}, 386 {0x181c, 0xe5}, {0x1878, 0x00}, 387 {0x1994, 0x1c}, {0x1af0, 0x00}, 388 {0x0428, 0x60}, {0x0d58, 0x33}, 389 {0x1d58, 0x33}, {0x0990, 0x74}, 390 {0x0d64, 0x17}, {0x08c8, 0x13}, 391 {0x1990, 0x74}, {0x1d64, 0x17}, 392 {0x18c8, 0x13}, {0x0d90, 0x40}, 393 {0x0da8, 0x40}, {0x0dc0, 0x40}, 394 {0x0dd8, 0x40}, {0x1d90, 0x40}, 395 {0x1da8, 0x40}, {0x1dc0, 0x40}, 396 {0x1dd8, 0x40}, {0x03c0, 0x30}, 397 {0x03c4, 0x06}, {0x0e10, 0x00}, 398 {0x1e10, 0x00}, {0x043c, 0x0f}, 399 {0x0d2c, 0xff}, {0x1d2c, 0xff}, 400 {0x0d34, 0x0f}, {0x1d34, 0x0f}, 401 {0x08fc, 0x2a}, {0x0914, 0x28}, 402 {0x0a30, 0x03}, {0x0e38, 0x03}, 403 {0x0ecc, 0x27}, {0x0ed0, 0x22}, 404 {0x0ed4, 0x26}, {0x18fc, 0x2a}, 405 {0x1914, 0x28}, {0x1a30, 0x03}, 406 {0x1e38, 0x03}, {0x1ecc, 0x27}, 407 {0x1ed0, 0x22}, {0x1ed4, 0x26}, 408 {0x0048, 0x0f}, {0x0060, 0x3c}, 409 {0x0064, 0xf7}, {0x006c, 0x20}, 410 {0x0070, 0x7d}, {0x0074, 0x68}, 411 {0x0af4, 0x1a}, {0x1af4, 0x1a}, 412 {0x0440, 0x3f}, {0x10d4, 0x08}, 413 {0x20d4, 0x08}, {0x00d4, 0x30}, 414 {0x0024, 0x6e}, 415 }; 416 417 static inline int rk_udphy_grfreg_write(struct regmap *base, 418 const struct rk_udphy_grf_reg *reg, bool en) 419 { 420 return regmap_write(base, reg->offset, en ? reg->enable : reg->disable); 421 } 422 423 static int rk_udphy_clk_init(struct rk_udphy *udphy, struct device *dev) 424 { 425 int i; 426 427 udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks); 428 if (udphy->num_clks < 1) 429 return -ENODEV; 430 431 /* used for configure phy reference clock frequency */ 432 for (i = 0; i < udphy->num_clks; i++) { 433 if (!strncmp(udphy->clks[i].id, "refclk", 6)) { 434 udphy->refclk = udphy->clks[i].clk; 435 break; 436 } 437 } 438 439 if (!udphy->refclk) 440 return dev_err_probe(udphy->dev, -EINVAL, "no refclk found\n"); 441 442 return 0; 443 } 444 445 static int rk_udphy_reset_assert_all(struct rk_udphy *udphy) 446 { 447 return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts); 448 } 449 450 static int rk_udphy_reset_deassert_all(struct rk_udphy *udphy) 451 { 452 return reset_control_bulk_deassert(udphy->num_rsts, udphy->rsts); 453 } 454 455 static int rk_udphy_reset_deassert(struct rk_udphy *udphy, char *name) 456 { 457 struct reset_control_bulk_data *list = udphy->rsts; 458 int idx; 459 460 for (idx = 0; idx < udphy->num_rsts; idx++) { 461 if (!strcmp(list[idx].id, name)) 462 return reset_control_deassert(list[idx].rstc); 463 } 464 465 return -EINVAL; 466 } 467 468 static int rk_udphy_reset_init(struct rk_udphy *udphy, struct device *dev) 469 { 470 const struct rk_udphy_cfg *cfg = udphy->cfgs; 471 int idx; 472 473 udphy->num_rsts = cfg->num_rsts; 474 udphy->rsts = devm_kcalloc(dev, udphy->num_rsts, 475 sizeof(*udphy->rsts), GFP_KERNEL); 476 if (!udphy->rsts) 477 return -ENOMEM; 478 479 for (idx = 0; idx < cfg->num_rsts; idx++) 480 udphy->rsts[idx].id = cfg->rst_list[idx]; 481 482 return devm_reset_control_bulk_get_exclusive(dev, cfg->num_rsts, 483 udphy->rsts); 484 } 485 486 static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable) 487 { 488 const struct rk_udphy_cfg *cfg = udphy->cfgs; 489 const struct rk_udphy_grf_reg *preg; 490 491 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; 492 rk_udphy_grfreg_write(udphy->usbgrf, preg, disable); 493 } 494 495 static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable) 496 { 497 const struct rk_udphy_cfg *cfg = udphy->cfgs; 498 499 rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); 500 rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); 501 } 502 503 /* 504 * In usb/dp combo phy driver, here are 2 ways to mapping lanes. 505 * 506 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) 507 * --------------------------------------------------------------------------- 508 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 509 * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 510 * C/E(Normal) dpln3 dpln2 dpln0 dpln1 511 * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 512 * D/F(Normal) usbrx usbtx dpln0 dpln1 513 * D/F(Flip ) dpln0 dpln1 usbrx usbtx 514 * A(Normal ) dpln3 dpln1 dpln2 dpln0 515 * A(Flip ) dpln2 dpln0 dpln3 dpln1 516 * B(Normal ) usbrx usbtx dpln1 dpln0 517 * B(Flip ) dpln1 dpln0 usbrx usbtx 518 * --------------------------------------------------------------------------- 519 * 520 * 2 Mapping the lanes in dtsi 521 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>; 522 * sample as follow: 523 * --------------------------------------------------------------------------- 524 * B11-B10 A2-A3 A11-A10 B2-B3 525 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 526 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 527 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 528 * --------------------------------------------------------------------------- 529 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>; 530 * sample as follow: 531 * --------------------------------------------------------------------------- 532 * B11-B10 A2-A3 A11-A10 B2-B3 533 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 534 * <0 1> dpln0 dpln1 usbrx usbtx 535 * <2 3> usbrx usbtx dpln0 dpln1 536 * --------------------------------------------------------------------------- 537 */ 538 539 static void rk_udphy_dplane_select(struct rk_udphy *udphy) 540 { 541 const struct rk_udphy_cfg *cfg = udphy->cfgs; 542 u32 value = 0; 543 544 switch (udphy->mode) { 545 case UDPHY_MODE_DP: 546 value |= 2 << udphy->dp_lane_sel[2] * 2; 547 value |= 3 << udphy->dp_lane_sel[3] * 2; 548 fallthrough; 549 550 case UDPHY_MODE_DP_USB: 551 value |= 0 << udphy->dp_lane_sel[0] * 2; 552 value |= 1 << udphy->dp_lane_sel[1] * 2; 553 break; 554 555 case UDPHY_MODE_USB: 556 break; 557 558 default: 559 break; 560 } 561 562 regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg, 563 ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | 564 FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | 565 FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); 566 } 567 568 static int rk_udphy_dplane_get(struct rk_udphy *udphy) 569 { 570 int dp_lanes; 571 572 switch (udphy->mode) { 573 case UDPHY_MODE_DP: 574 dp_lanes = 4; 575 break; 576 577 case UDPHY_MODE_DP_USB: 578 dp_lanes = 2; 579 break; 580 581 case UDPHY_MODE_USB: 582 default: 583 dp_lanes = 0; 584 break; 585 } 586 587 return dp_lanes; 588 } 589 590 static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes) 591 { 592 u32 val = 0; 593 int i; 594 595 for (i = 0; i < dp_lanes; i++) 596 val |= BIT(udphy->dp_lane_sel[i]); 597 598 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, 599 FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); 600 601 if (!dp_lanes) 602 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 603 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); 604 } 605 606 static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd) 607 { 608 const struct rk_udphy_cfg *cfg = udphy->cfgs; 609 610 udphy->dp_sink_hpd_sel = true; 611 udphy->dp_sink_hpd_cfg = hpd; 612 613 if (!udphy->dp_in_use) 614 return; 615 616 rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd); 617 } 618 619 static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy) 620 { 621 if (udphy->flip) { 622 udphy->dp_lane_sel[0] = 0; 623 udphy->dp_lane_sel[1] = 1; 624 udphy->dp_lane_sel[2] = 3; 625 udphy->dp_lane_sel[3] = 2; 626 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; 627 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; 628 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; 629 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; 630 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; 631 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; 632 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1); 633 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); 634 } else { 635 udphy->dp_lane_sel[0] = 2; 636 udphy->dp_lane_sel[1] = 3; 637 udphy->dp_lane_sel[2] = 1; 638 udphy->dp_lane_sel[3] = 0; 639 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; 640 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; 641 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; 642 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; 643 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; 644 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; 645 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); 646 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1); 647 } 648 649 udphy->mode = UDPHY_MODE_DP_USB; 650 } 651 652 static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw, 653 enum typec_orientation orien) 654 { 655 struct rk_udphy *udphy = typec_switch_get_drvdata(sw); 656 657 mutex_lock(&udphy->mutex); 658 659 if (orien == TYPEC_ORIENTATION_NONE) { 660 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); 661 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); 662 /* unattached */ 663 rk_udphy_usb_bvalid_enable(udphy, false); 664 goto unlock_ret; 665 } 666 667 udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false; 668 rk_udphy_set_typec_default_mapping(udphy); 669 rk_udphy_usb_bvalid_enable(udphy, true); 670 671 unlock_ret: 672 mutex_unlock(&udphy->mutex); 673 return 0; 674 } 675 676 static void rk_udphy_orien_switch_unregister(void *data) 677 { 678 struct rk_udphy *udphy = data; 679 680 typec_switch_unregister(udphy->sw); 681 } 682 683 static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy) 684 { 685 struct typec_switch_desc sw_desc = { }; 686 687 sw_desc.drvdata = udphy; 688 sw_desc.fwnode = dev_fwnode(udphy->dev); 689 sw_desc.set = rk_udphy_orien_sw_set; 690 691 udphy->sw = typec_switch_register(udphy->dev, &sw_desc); 692 if (IS_ERR(udphy->sw)) { 693 dev_err(udphy->dev, "Error register typec orientation switch: %ld\n", 694 PTR_ERR(udphy->sw)); 695 return PTR_ERR(udphy->sw); 696 } 697 698 return devm_add_action_or_reset(udphy->dev, 699 rk_udphy_orien_switch_unregister, udphy); 700 } 701 702 static int rk_udphy_refclk_set(struct rk_udphy *udphy) 703 { 704 unsigned long rate; 705 int ret; 706 707 /* configure phy reference clock */ 708 rate = clk_get_rate(udphy->refclk); 709 dev_dbg(udphy->dev, "refclk freq %ld\n", rate); 710 711 switch (rate) { 712 case 24000000: 713 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_24m_refclk_cfg, 714 ARRAY_SIZE(rk_udphy_24m_refclk_cfg)); 715 if (ret) 716 return ret; 717 break; 718 719 case 26000000: 720 /* register default is 26MHz */ 721 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cfg, 722 ARRAY_SIZE(rk_udphy_26m_refclk_cfg)); 723 if (ret) 724 return ret; 725 break; 726 727 default: 728 dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate); 729 return -EINVAL; 730 } 731 732 return 0; 733 } 734 735 static int rk_udphy_status_check(struct rk_udphy *udphy) 736 { 737 unsigned int val; 738 int ret; 739 740 /* LCPLL check */ 741 if (udphy->mode & UDPHY_MODE_USB) { 742 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, 743 val, (val & CMN_ANA_LCPLL_AFC_DONE) && 744 (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000); 745 if (ret) { 746 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); 747 /* 748 * If earlier software (U-Boot) enabled USB once already 749 * the PLL may have problems locking on the first try. 750 * It will be successful on the second try, so for the 751 * time being a -EPROBE_DEFER will solve the issue. 752 * 753 * This requires further investigation to understand the 754 * root cause, especially considering that the driver is 755 * asserting all reset lines at probe time. 756 */ 757 return -EPROBE_DEFER; 758 } 759 760 if (!udphy->flip) { 761 ret = regmap_read_poll_timeout(udphy->pma_regmap, 762 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, 763 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, 764 200, 100000); 765 if (ret) 766 dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); 767 } else { 768 ret = regmap_read_poll_timeout(udphy->pma_regmap, 769 TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, 770 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, 771 200, 100000); 772 if (ret) 773 dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); 774 } 775 } 776 777 return 0; 778 } 779 780 static int rk_udphy_init(struct rk_udphy *udphy) 781 { 782 const struct rk_udphy_cfg *cfg = udphy->cfgs; 783 int ret; 784 785 rk_udphy_reset_assert_all(udphy); 786 usleep_range(10000, 11000); 787 788 /* enable rx lfps for usb */ 789 if (udphy->mode & UDPHY_MODE_USB) 790 rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); 791 792 /* Step 1: power on pma and deassert apb rstn */ 793 rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); 794 795 rk_udphy_reset_deassert(udphy, "pma_apb"); 796 rk_udphy_reset_deassert(udphy, "pcs_apb"); 797 798 /* Step 2: set init sequence and phy refclk */ 799 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_init_sequence, 800 ARRAY_SIZE(rk_udphy_init_sequence)); 801 if (ret) { 802 dev_err(udphy->dev, "init sequence set error %d\n", ret); 803 goto assert_resets; 804 } 805 806 ret = rk_udphy_refclk_set(udphy); 807 if (ret) { 808 dev_err(udphy->dev, "refclk set error %d\n", ret); 809 goto assert_resets; 810 } 811 812 /* Step 3: configure lane mux */ 813 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, 814 CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, 815 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | 816 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | 817 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | 818 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | 819 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); 820 821 /* Step 4: deassert init rstn and wait for 200ns from datasheet */ 822 if (udphy->mode & UDPHY_MODE_USB) 823 rk_udphy_reset_deassert(udphy, "init"); 824 825 if (udphy->mode & UDPHY_MODE_DP) { 826 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 827 CMN_DP_INIT_RSTN, 828 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); 829 } 830 831 udelay(1); 832 833 /* Step 5: deassert cmn/lane rstn */ 834 if (udphy->mode & UDPHY_MODE_USB) { 835 rk_udphy_reset_deassert(udphy, "cmn"); 836 rk_udphy_reset_deassert(udphy, "lane"); 837 } 838 839 /* Step 6: wait for lock done of pll */ 840 ret = rk_udphy_status_check(udphy); 841 if (ret) 842 goto assert_resets; 843 844 return 0; 845 846 assert_resets: 847 rk_udphy_reset_assert_all(udphy); 848 return ret; 849 } 850 851 static int rk_udphy_setup(struct rk_udphy *udphy) 852 { 853 int ret; 854 855 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); 856 if (ret) { 857 dev_err(udphy->dev, "failed to enable clk\n"); 858 return ret; 859 } 860 861 ret = rk_udphy_init(udphy); 862 if (ret) { 863 dev_err(udphy->dev, "failed to init combophy\n"); 864 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); 865 return ret; 866 } 867 868 return 0; 869 } 870 871 static void rk_udphy_disable(struct rk_udphy *udphy) 872 { 873 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); 874 rk_udphy_reset_assert_all(udphy); 875 } 876 877 static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy) 878 { 879 int ret, i, num_lanes; 880 881 num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux"); 882 if (num_lanes < 0) { 883 dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n"); 884 udphy->mode = UDPHY_MODE_USB; 885 return 0; 886 } 887 888 if (num_lanes != 2 && num_lanes != 4) 889 return dev_err_probe(udphy->dev, -EINVAL, 890 "invalid number of lane mux\n"); 891 892 ret = device_property_read_u32_array(udphy->dev, "rockchip,dp-lane-mux", 893 udphy->dp_lane_sel, num_lanes); 894 if (ret) 895 return dev_err_probe(udphy->dev, ret, "get dp lane mux failed\n"); 896 897 for (i = 0; i < num_lanes; i++) { 898 int j; 899 900 if (udphy->dp_lane_sel[i] > 3) 901 return dev_err_probe(udphy->dev, -EINVAL, 902 "lane mux between 0 and 3, exceeding the range\n"); 903 904 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; 905 906 for (j = i + 1; j < num_lanes; j++) { 907 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) 908 return dev_err_probe(udphy->dev, -EINVAL, 909 "set repeat lane mux value\n"); 910 } 911 } 912 913 udphy->mode = UDPHY_MODE_DP; 914 if (num_lanes == 2) { 915 udphy->mode |= UDPHY_MODE_USB; 916 udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP); 917 } 918 919 return 0; 920 } 921 922 static int rk_udphy_get_initial_status(struct rk_udphy *udphy) 923 { 924 int ret; 925 u32 value; 926 927 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); 928 if (ret) { 929 dev_err(udphy->dev, "failed to enable clk\n"); 930 return ret; 931 } 932 933 rk_udphy_reset_deassert_all(udphy); 934 935 regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value); 936 if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value)) 937 udphy->status = UDPHY_MODE_DP; 938 else 939 rk_udphy_disable(udphy); 940 941 return 0; 942 } 943 944 static int rk_udphy_parse_dt(struct rk_udphy *udphy) 945 { 946 struct device *dev = udphy->dev; 947 struct device_node *np = dev_of_node(dev); 948 enum usb_device_speed maximum_speed; 949 int ret; 950 951 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf"); 952 if (IS_ERR(udphy->u2phygrf)) 953 return dev_err_probe(dev, PTR_ERR(udphy->u2phygrf), "failed to get u2phy-grf\n"); 954 955 udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf"); 956 if (IS_ERR(udphy->udphygrf)) 957 return dev_err_probe(dev, PTR_ERR(udphy->udphygrf), "failed to get usbdpphy-grf\n"); 958 959 udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf"); 960 if (IS_ERR(udphy->usbgrf)) 961 return dev_err_probe(dev, PTR_ERR(udphy->usbgrf), "failed to get usb-grf\n"); 962 963 udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf"); 964 if (IS_ERR(udphy->vogrf)) 965 return dev_err_probe(dev, PTR_ERR(udphy->vogrf), "failed to get vo-grf\n"); 966 967 ret = rk_udphy_parse_lane_mux_data(udphy); 968 if (ret) 969 return ret; 970 971 udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW); 972 if (IS_ERR(udphy->sbu1_dc_gpio)) 973 return PTR_ERR(udphy->sbu1_dc_gpio); 974 975 udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW); 976 if (IS_ERR(udphy->sbu2_dc_gpio)) 977 return PTR_ERR(udphy->sbu2_dc_gpio); 978 979 if (device_property_present(dev, "maximum-speed")) { 980 maximum_speed = usb_get_maximum_speed(dev); 981 udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; 982 } 983 984 ret = rk_udphy_clk_init(udphy, dev); 985 if (ret) 986 return ret; 987 988 return rk_udphy_reset_init(udphy, dev); 989 } 990 991 static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode) 992 { 993 int ret; 994 995 if (!(udphy->mode & mode)) { 996 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); 997 return 0; 998 } 999 1000 if (udphy->status == UDPHY_MODE_NONE) { 1001 udphy->mode_change = false; 1002 ret = rk_udphy_setup(udphy); 1003 if (ret) 1004 return ret; 1005 1006 if (udphy->mode & UDPHY_MODE_USB) 1007 rk_udphy_u3_port_disable(udphy, false); 1008 } else if (udphy->mode_change) { 1009 udphy->mode_change = false; 1010 udphy->status = UDPHY_MODE_NONE; 1011 if (udphy->mode == UDPHY_MODE_DP) 1012 rk_udphy_u3_port_disable(udphy, true); 1013 1014 rk_udphy_disable(udphy); 1015 ret = rk_udphy_setup(udphy); 1016 if (ret) 1017 return ret; 1018 } 1019 1020 udphy->status |= mode; 1021 1022 return 0; 1023 } 1024 1025 static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode) 1026 { 1027 if (!(udphy->mode & mode)) { 1028 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); 1029 return; 1030 } 1031 1032 if (!udphy->status) 1033 return; 1034 1035 udphy->status &= ~mode; 1036 1037 if (udphy->status == UDPHY_MODE_NONE) 1038 rk_udphy_disable(udphy); 1039 } 1040 1041 static int rk_udphy_dp_phy_init(struct phy *phy) 1042 { 1043 struct rk_udphy *udphy = phy_get_drvdata(phy); 1044 1045 mutex_lock(&udphy->mutex); 1046 1047 udphy->dp_in_use = true; 1048 rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); 1049 1050 mutex_unlock(&udphy->mutex); 1051 1052 return 0; 1053 } 1054 1055 static int rk_udphy_dp_phy_exit(struct phy *phy) 1056 { 1057 struct rk_udphy *udphy = phy_get_drvdata(phy); 1058 1059 mutex_lock(&udphy->mutex); 1060 udphy->dp_in_use = false; 1061 mutex_unlock(&udphy->mutex); 1062 return 0; 1063 } 1064 1065 static int rk_udphy_dp_phy_power_on(struct phy *phy) 1066 { 1067 struct rk_udphy *udphy = phy_get_drvdata(phy); 1068 int ret, dp_lanes; 1069 1070 mutex_lock(&udphy->mutex); 1071 1072 dp_lanes = rk_udphy_dplane_get(udphy); 1073 phy_set_bus_width(phy, dp_lanes); 1074 1075 ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP); 1076 if (ret) 1077 goto unlock; 1078 1079 rk_udphy_dplane_enable(udphy, dp_lanes); 1080 1081 rk_udphy_dplane_select(udphy); 1082 1083 unlock: 1084 mutex_unlock(&udphy->mutex); 1085 /* 1086 * If data send by aux channel too fast after phy power on, 1087 * the aux may be not ready which will cause aux error. Adding 1088 * delay to avoid this issue. 1089 */ 1090 usleep_range(10000, 11000); 1091 return ret; 1092 } 1093 1094 static int rk_udphy_dp_phy_power_off(struct phy *phy) 1095 { 1096 struct rk_udphy *udphy = phy_get_drvdata(phy); 1097 1098 mutex_lock(&udphy->mutex); 1099 rk_udphy_dplane_enable(udphy, 0); 1100 rk_udphy_power_off(udphy, UDPHY_MODE_DP); 1101 mutex_unlock(&udphy->mutex); 1102 1103 return 0; 1104 } 1105 1106 static int rk_udphy_dp_phy_verify_link_rate(unsigned int link_rate) 1107 { 1108 switch (link_rate) { 1109 case 1620: 1110 case 2700: 1111 case 5400: 1112 case 8100: 1113 break; 1114 1115 default: 1116 return -EINVAL; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static int rk_udphy_dp_phy_verify_config(struct rk_udphy *udphy, 1123 struct phy_configure_opts_dp *dp) 1124 { 1125 int i, ret; 1126 1127 /* If changing link rate was required, verify it's supported. */ 1128 ret = rk_udphy_dp_phy_verify_link_rate(dp->link_rate); 1129 if (ret) 1130 return ret; 1131 1132 /* Verify lane count. */ 1133 switch (dp->lanes) { 1134 case 1: 1135 case 2: 1136 case 4: 1137 /* valid lane count. */ 1138 break; 1139 1140 default: 1141 return -EINVAL; 1142 } 1143 1144 /* 1145 * If changing voltages is required, check swing and pre-emphasis 1146 * levels, per-lane. 1147 */ 1148 if (dp->set_voltages) { 1149 /* Lane count verified previously. */ 1150 for (i = 0; i < dp->lanes; i++) { 1151 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 1152 return -EINVAL; 1153 1154 /* 1155 * Sum of voltage swing and pre-emphasis levels cannot 1156 * exceed 3. 1157 */ 1158 if (dp->voltage[i] + dp->pre[i] > 3) 1159 return -EINVAL; 1160 } 1161 } 1162 1163 return 0; 1164 } 1165 1166 static void rk_udphy_dp_set_voltage(struct rk_udphy *udphy, u8 bw, 1167 u32 voltage, u32 pre, u32 lane) 1168 { 1169 const struct rk_udphy_cfg *cfg = udphy->cfgs; 1170 const struct rk_udphy_dp_tx_drv_ctrl (*dp_ctrl)[4]; 1171 u32 offset = 0x800 * lane; 1172 u32 val; 1173 1174 if (udphy->mux) 1175 dp_ctrl = cfg->dp_tx_ctrl_cfg_typec[bw]; 1176 else 1177 dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; 1178 1179 val = dp_ctrl[voltage][pre].trsv_reg0204; 1180 regmap_write(udphy->pma_regmap, 0x0810 + offset, val); 1181 1182 val = dp_ctrl[voltage][pre].trsv_reg0205; 1183 regmap_write(udphy->pma_regmap, 0x0814 + offset, val); 1184 1185 val = dp_ctrl[voltage][pre].trsv_reg0206; 1186 regmap_write(udphy->pma_regmap, 0x0818 + offset, val); 1187 1188 val = dp_ctrl[voltage][pre].trsv_reg0207; 1189 regmap_write(udphy->pma_regmap, 0x081c + offset, val); 1190 } 1191 1192 static int rk_udphy_dp_phy_configure(struct phy *phy, 1193 union phy_configure_opts *opts) 1194 { 1195 struct rk_udphy *udphy = phy_get_drvdata(phy); 1196 struct phy_configure_opts_dp *dp = &opts->dp; 1197 u32 i, val, lane; 1198 int ret; 1199 1200 ret = rk_udphy_dp_phy_verify_config(udphy, dp); 1201 if (ret) 1202 return ret; 1203 1204 if (dp->set_rate) { 1205 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 1206 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); 1207 1208 switch (dp->link_rate) { 1209 case 1620: 1210 udphy->bw = DP_BW_RBR; 1211 break; 1212 1213 case 2700: 1214 udphy->bw = DP_BW_HBR; 1215 break; 1216 1217 case 5400: 1218 udphy->bw = DP_BW_HBR2; 1219 break; 1220 1221 case 8100: 1222 udphy->bw = DP_BW_HBR3; 1223 break; 1224 1225 default: 1226 return -EINVAL; 1227 } 1228 1229 regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, 1230 FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); 1231 regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, 1232 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); 1233 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, 1234 FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); 1235 1236 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, 1237 FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && 1238 FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), 1239 0, 1000); 1240 if (ret) { 1241 dev_err(udphy->dev, "ROPLL is not lock, set_rate failed\n"); 1242 return ret; 1243 } 1244 } 1245 1246 if (dp->set_voltages) { 1247 for (i = 0; i < dp->lanes; i++) { 1248 lane = udphy->dp_lane_sel[i]; 1249 switch (dp->link_rate) { 1250 case 1620: 1251 case 2700: 1252 regmap_update_bits(udphy->pma_regmap, 1253 TRSV_ANA_TX_CLK_OFFSET_N(lane), 1254 LN_ANA_TX_SER_TXCLK_INV, 1255 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 1256 udphy->lane_mux_sel[lane])); 1257 break; 1258 1259 case 5400: 1260 case 8100: 1261 regmap_update_bits(udphy->pma_regmap, 1262 TRSV_ANA_TX_CLK_OFFSET_N(lane), 1263 LN_ANA_TX_SER_TXCLK_INV, 1264 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); 1265 break; 1266 } 1267 1268 rk_udphy_dp_set_voltage(udphy, udphy->bw, dp->voltage[i], 1269 dp->pre[i], lane); 1270 } 1271 } 1272 1273 return 0; 1274 } 1275 1276 static const struct phy_ops rk_udphy_dp_phy_ops = { 1277 .init = rk_udphy_dp_phy_init, 1278 .exit = rk_udphy_dp_phy_exit, 1279 .power_on = rk_udphy_dp_phy_power_on, 1280 .power_off = rk_udphy_dp_phy_power_off, 1281 .configure = rk_udphy_dp_phy_configure, 1282 .owner = THIS_MODULE, 1283 }; 1284 1285 static int rk_udphy_usb3_phy_init(struct phy *phy) 1286 { 1287 struct rk_udphy *udphy = phy_get_drvdata(phy); 1288 int ret = 0; 1289 1290 mutex_lock(&udphy->mutex); 1291 /* DP only or high-speed, disable U3 port */ 1292 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { 1293 rk_udphy_u3_port_disable(udphy, true); 1294 goto unlock; 1295 } 1296 1297 ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB); 1298 1299 unlock: 1300 mutex_unlock(&udphy->mutex); 1301 return ret; 1302 } 1303 1304 static int rk_udphy_usb3_phy_exit(struct phy *phy) 1305 { 1306 struct rk_udphy *udphy = phy_get_drvdata(phy); 1307 1308 mutex_lock(&udphy->mutex); 1309 /* DP only or high-speed */ 1310 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) 1311 goto unlock; 1312 1313 rk_udphy_power_off(udphy, UDPHY_MODE_USB); 1314 1315 unlock: 1316 mutex_unlock(&udphy->mutex); 1317 return 0; 1318 } 1319 1320 static const struct phy_ops rk_udphy_usb3_phy_ops = { 1321 .init = rk_udphy_usb3_phy_init, 1322 .exit = rk_udphy_usb3_phy_exit, 1323 .owner = THIS_MODULE, 1324 }; 1325 1326 static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux, 1327 struct typec_mux_state *state) 1328 { 1329 struct rk_udphy *udphy = typec_mux_get_drvdata(mux); 1330 u8 mode; 1331 1332 mutex_lock(&udphy->mutex); 1333 1334 switch (state->mode) { 1335 case TYPEC_DP_STATE_C: 1336 case TYPEC_DP_STATE_E: 1337 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; 1338 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; 1339 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; 1340 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; 1341 mode = UDPHY_MODE_DP; 1342 break; 1343 1344 case TYPEC_DP_STATE_D: 1345 default: 1346 if (udphy->flip) { 1347 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; 1348 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; 1349 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; 1350 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; 1351 } else { 1352 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; 1353 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; 1354 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; 1355 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; 1356 } 1357 mode = UDPHY_MODE_DP_USB; 1358 break; 1359 } 1360 1361 if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) { 1362 struct typec_displayport_data *data = state->data; 1363 1364 if (!data) { 1365 rk_udphy_dp_hpd_event_trigger(udphy, false); 1366 } else if (data->status & DP_STATUS_IRQ_HPD) { 1367 rk_udphy_dp_hpd_event_trigger(udphy, false); 1368 usleep_range(750, 800); 1369 rk_udphy_dp_hpd_event_trigger(udphy, true); 1370 } else if (data->status & DP_STATUS_HPD_STATE) { 1371 if (udphy->mode != mode) { 1372 udphy->mode = mode; 1373 udphy->mode_change = true; 1374 } 1375 rk_udphy_dp_hpd_event_trigger(udphy, true); 1376 } else { 1377 rk_udphy_dp_hpd_event_trigger(udphy, false); 1378 } 1379 } 1380 1381 mutex_unlock(&udphy->mutex); 1382 return 0; 1383 } 1384 1385 static void rk_udphy_typec_mux_unregister(void *data) 1386 { 1387 struct rk_udphy *udphy = data; 1388 1389 typec_mux_unregister(udphy->mux); 1390 } 1391 1392 static int rk_udphy_setup_typec_mux(struct rk_udphy *udphy) 1393 { 1394 struct typec_mux_desc mux_desc = {}; 1395 1396 mux_desc.drvdata = udphy; 1397 mux_desc.fwnode = dev_fwnode(udphy->dev); 1398 mux_desc.set = rk_udphy_typec_mux_set; 1399 1400 udphy->mux = typec_mux_register(udphy->dev, &mux_desc); 1401 if (IS_ERR(udphy->mux)) { 1402 dev_err(udphy->dev, "Error register typec mux: %ld\n", 1403 PTR_ERR(udphy->mux)); 1404 return PTR_ERR(udphy->mux); 1405 } 1406 1407 return devm_add_action_or_reset(udphy->dev, rk_udphy_typec_mux_unregister, 1408 udphy); 1409 } 1410 1411 static const struct regmap_config rk_udphy_pma_regmap_cfg = { 1412 .reg_bits = 32, 1413 .reg_stride = 4, 1414 .val_bits = 32, 1415 .fast_io = true, 1416 .max_register = 0x20dc, 1417 }; 1418 1419 static struct phy *rk_udphy_phy_xlate(struct device *dev, const struct of_phandle_args *args) 1420 { 1421 struct rk_udphy *udphy = dev_get_drvdata(dev); 1422 1423 if (args->args_count == 0) 1424 return ERR_PTR(-EINVAL); 1425 1426 switch (args->args[0]) { 1427 case PHY_TYPE_USB3: 1428 return udphy->phy_u3; 1429 case PHY_TYPE_DP: 1430 return udphy->phy_dp; 1431 } 1432 1433 return ERR_PTR(-EINVAL); 1434 } 1435 1436 static int rk_udphy_probe(struct platform_device *pdev) 1437 { 1438 struct device *dev = &pdev->dev; 1439 struct phy_provider *phy_provider; 1440 struct resource *res; 1441 struct rk_udphy *udphy; 1442 void __iomem *base; 1443 int id, ret; 1444 1445 udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL); 1446 if (!udphy) 1447 return -ENOMEM; 1448 1449 udphy->cfgs = device_get_match_data(dev); 1450 if (!udphy->cfgs) 1451 return dev_err_probe(dev, -EINVAL, "missing match data\n"); 1452 1453 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1454 if (IS_ERR(base)) 1455 return PTR_ERR(base); 1456 1457 /* find the phy-id from the io address */ 1458 udphy->id = -ENODEV; 1459 for (id = 0; id < udphy->cfgs->num_phys; id++) { 1460 if (res->start == udphy->cfgs->phy_ids[id]) { 1461 udphy->id = id; 1462 break; 1463 } 1464 } 1465 1466 if (udphy->id < 0) 1467 return dev_err_probe(dev, -ENODEV, "no matching device found\n"); 1468 1469 udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA, 1470 &rk_udphy_pma_regmap_cfg); 1471 if (IS_ERR(udphy->pma_regmap)) 1472 return PTR_ERR(udphy->pma_regmap); 1473 1474 udphy->dev = dev; 1475 ret = rk_udphy_parse_dt(udphy); 1476 if (ret) 1477 return ret; 1478 1479 ret = rk_udphy_get_initial_status(udphy); 1480 if (ret) 1481 return ret; 1482 1483 mutex_init(&udphy->mutex); 1484 platform_set_drvdata(pdev, udphy); 1485 1486 if (device_property_present(dev, "orientation-switch")) { 1487 ret = rk_udphy_setup_orien_switch(udphy); 1488 if (ret) 1489 return ret; 1490 } 1491 1492 if (device_property_present(dev, "mode-switch")) { 1493 ret = rk_udphy_setup_typec_mux(udphy); 1494 if (ret) 1495 return ret; 1496 } 1497 1498 udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops); 1499 if (IS_ERR(udphy->phy_u3)) { 1500 ret = PTR_ERR(udphy->phy_u3); 1501 return dev_err_probe(dev, ret, "failed to create USB3 phy\n"); 1502 } 1503 phy_set_drvdata(udphy->phy_u3, udphy); 1504 1505 udphy->phy_dp = devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops); 1506 if (IS_ERR(udphy->phy_dp)) { 1507 ret = PTR_ERR(udphy->phy_dp); 1508 return dev_err_probe(dev, ret, "failed to create DP phy\n"); 1509 } 1510 phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy)); 1511 udphy->phy_dp->attrs.max_link_rate = 8100; 1512 phy_set_drvdata(udphy->phy_dp, udphy); 1513 1514 phy_provider = devm_of_phy_provider_register(dev, rk_udphy_phy_xlate); 1515 if (IS_ERR(phy_provider)) { 1516 ret = PTR_ERR(phy_provider); 1517 return dev_err_probe(dev, ret, "failed to register phy provider\n"); 1518 } 1519 1520 return 0; 1521 } 1522 1523 static int __maybe_unused rk_udphy_resume(struct device *dev) 1524 { 1525 struct rk_udphy *udphy = dev_get_drvdata(dev); 1526 1527 if (udphy->dp_sink_hpd_sel) 1528 rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); 1529 1530 return 0; 1531 } 1532 1533 static const struct dev_pm_ops rk_udphy_pm_ops = { 1534 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume) 1535 }; 1536 1537 static const char * const rk_udphy_rst_list[] = { 1538 "init", "cmn", "lane", "pcs_apb", "pma_apb" 1539 }; 1540 1541 static const struct rk_udphy_cfg rk3588_udphy_cfgs = { 1542 .num_phys = 2, 1543 .phy_ids = { 1544 0xfed80000, 1545 0xfed90000, 1546 }, 1547 .num_rsts = ARRAY_SIZE(rk_udphy_rst_list), 1548 .rst_list = rk_udphy_rst_list, 1549 .grfcfg = { 1550 /* u2phy-grf */ 1551 .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3), 1552 .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3), 1553 1554 /* usb-grf */ 1555 .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188), 1556 .usb3otg1_cfg = RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188), 1557 1558 /* usbdpphy-grf */ 1559 .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1), 1560 .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1), 1561 }, 1562 .vogrfcfg = { 1563 { 1564 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3), 1565 .dp_lane_reg = 0x0000, 1566 }, 1567 { 1568 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3), 1569 .dp_lane_reg = 0x0008, 1570 }, 1571 }, 1572 .dp_tx_ctrl_cfg = { 1573 rk3588_dp_tx_drv_ctrl_rbr_hbr, 1574 rk3588_dp_tx_drv_ctrl_rbr_hbr, 1575 rk3588_dp_tx_drv_ctrl_hbr2, 1576 rk3588_dp_tx_drv_ctrl_hbr3, 1577 }, 1578 .dp_tx_ctrl_cfg_typec = { 1579 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, 1580 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, 1581 rk3588_dp_tx_drv_ctrl_hbr2, 1582 rk3588_dp_tx_drv_ctrl_hbr3, 1583 }, 1584 }; 1585 1586 static const struct of_device_id rk_udphy_dt_match[] = { 1587 { 1588 .compatible = "rockchip,rk3588-usbdp-phy", 1589 .data = &rk3588_udphy_cfgs 1590 }, 1591 { /* sentinel */ } 1592 }; 1593 MODULE_DEVICE_TABLE(of, rk_udphy_dt_match); 1594 1595 static struct platform_driver rk_udphy_driver = { 1596 .probe = rk_udphy_probe, 1597 .driver = { 1598 .name = "rockchip-usbdp-phy", 1599 .of_match_table = rk_udphy_dt_match, 1600 .pm = &rk_udphy_pm_ops, 1601 }, 1602 }; 1603 module_platform_driver(rk_udphy_driver); 1604 1605 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>"); 1606 MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>"); 1607 MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver"); 1608 MODULE_LICENSE("GPL"); 1609