1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Collabora Ltd. 5 * 6 * Author: Algea Cao <algea.cao@rock-chips.com> 7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> 8 */ 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_platform.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/rational.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 24 #define GRF_HDPTX_CON0 0x00 25 #define HDPTX_I_PLL_EN BIT(7) 26 #define HDPTX_I_BIAS_EN BIT(6) 27 #define HDPTX_I_BGR_EN BIT(5) 28 #define HDPTX_MODE_SEL BIT(0) 29 #define GRF_HDPTX_STATUS 0x80 30 #define HDPTX_O_PLL_LOCK_DONE BIT(3) 31 #define HDPTX_O_PHY_CLK_RDY BIT(2) 32 #define HDPTX_O_PHY_RDY BIT(1) 33 #define HDPTX_O_SB_RDY BIT(0) 34 35 #define HDTPX_REG(_n, _min, _max) \ 36 ( \ 37 BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \ 38 BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \ 39 ((0x##_n) * 4) \ 40 ) 41 42 #define CMN_REG(n) HDTPX_REG(n, 0000, 00a7) 43 #define SB_REG(n) HDTPX_REG(n, 0100, 0129) 44 #define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229) 45 #define LANE_REG(n) HDTPX_REG(n, 0300, 062d) 46 47 /* CMN_REG(0008) */ 48 #define OVRD_LCPLL_EN_MASK BIT(7) 49 #define LCPLL_EN_MASK BIT(6) 50 #define LCPLL_LCVCO_MODE_EN_MASK BIT(4) 51 /* CMN_REG(001e) */ 52 #define LCPLL_PI_EN_MASK BIT(5) 53 #define LCPLL_100M_CLK_EN_MASK BIT(0) 54 /* CMN_REG(0025) */ 55 #define LCPLL_PMS_IQDIV_RSTN_MASK BIT(4) 56 /* CMN_REG(0028) */ 57 #define LCPLL_SDC_FRAC_EN_MASK BIT(2) 58 #define LCPLL_SDC_FRAC_RSTN_MASK BIT(0) 59 /* CMN_REG(002d) */ 60 #define LCPLL_SDC_N_MASK GENMASK(3, 1) 61 /* CMN_REG(002e) */ 62 #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0) 63 /* CMN_REG(002f) */ 64 #define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2) 65 #define LCPLL_SDC_NDIV_RSTN_MASK BIT(0) 66 /* CMN_REG(003c) */ 67 #define ANA_LCPLL_RESERVED7_MASK BIT(7) 68 /* CMN_REG(003d) */ 69 #define OVRD_ROPLL_EN_MASK BIT(7) 70 #define ROPLL_EN_MASK BIT(6) 71 #define ROPLL_LCVCO_EN_MASK BIT(4) 72 /* CMN_REG(0046) */ 73 #define ROPLL_ANA_CPP_CTRL_COARSE_MASK GENMASK(7, 4) 74 #define ROPLL_ANA_CPP_CTRL_FINE_MASK GENMASK(3, 0) 75 /* CMN_REG(0047) */ 76 #define ROPLL_ANA_LPF_C_SEL_COARSE_MASK GENMASK(5, 3) 77 #define ROPLL_ANA_LPF_C_SEL_FINE_MASK GENMASK(2, 0) 78 /* CMN_REG(004e) */ 79 #define ROPLL_PI_EN_MASK BIT(5) 80 /* CMN_REG(0051) */ 81 #define ROPLL_PMS_MDIV_MASK GENMASK(7, 0) 82 /* CMN_REG(0055) */ 83 #define ROPLL_PMS_MDIV_AFC_MASK GENMASK(7, 0) 84 /* CMN_REG(0059) */ 85 #define ANA_ROPLL_PMS_PDIV_MASK GENMASK(7, 4) 86 #define ANA_ROPLL_PMS_REFDIV_MASK GENMASK(3, 0) 87 /* CMN_REG(005a) */ 88 #define ROPLL_PMS_SDIV_RBR_MASK GENMASK(7, 4) 89 #define ROPLL_PMS_SDIV_HBR_MASK GENMASK(3, 0) 90 /* CMN_REG(005b) */ 91 #define ROPLL_PMS_SDIV_HBR2_MASK GENMASK(7, 4) 92 /* CMN_REG(005c) */ 93 #define ROPLL_PMS_IQDIV_RSTN_MASK BIT(5) 94 /* CMN_REG(005e) */ 95 #define ROPLL_SDM_EN_MASK BIT(6) 96 #define OVRD_ROPLL_SDM_RSTN_MASK BIT(5) 97 #define ROPLL_SDM_RSTN_MASK BIT(4) 98 #define ROPLL_SDC_FRAC_EN_RBR_MASK BIT(3) 99 #define ROPLL_SDC_FRAC_EN_HBR_MASK BIT(2) 100 #define ROPLL_SDC_FRAC_EN_HBR2_MASK BIT(1) 101 #define ROPLL_SDM_FRAC_EN_HBR3_MASK BIT(0) 102 /* CMN_REG(005f) */ 103 #define OVRD_ROPLL_SDC_RSTN_MASK BIT(5) 104 #define ROPLL_SDC_RSTN_MASK BIT(4) 105 /* CMN_REG(0060) */ 106 #define ROPLL_SDM_DENOMINATOR_MASK GENMASK(7, 0) 107 /* CMN_REG(0064) */ 108 #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3) 109 #define ROPLL_SDM_NUM_SIGN_HBR_MASK BIT(2) 110 #define ROPLL_SDM_NUM_SIGN_HBR2_MASK BIT(1) 111 /* CMN_REG(0065) */ 112 #define ROPLL_SDM_NUM_MASK GENMASK(7, 0) 113 /* CMN_REG(0069) */ 114 #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0) 115 /* CMN_REG(006a) */ 116 #define ROPLL_SDC_N_HBR_MASK GENMASK(5, 3) 117 #define ROPLL_SDC_N_HBR2_MASK GENMASK(2, 0) 118 /* CMN_REG(006b) */ 119 #define ROPLL_SDC_N_HBR3_MASK GENMASK(3, 1) 120 /* CMN_REG(006c) */ 121 #define ROPLL_SDC_NUM_MASK GENMASK(5, 0) 122 /* cmn_reg0070 */ 123 #define ROPLL_SDC_DENO_MASK GENMASK(5, 0) 124 /* CMN_REG(0074) */ 125 #define OVRD_ROPLL_SDC_NDIV_RSTN_MASK BIT(3) 126 #define ROPLL_SDC_NDIV_RSTN_MASK BIT(2) 127 #define OVRD_ROPLL_SSC_EN_MASK BIT(1) 128 #define ROPLL_SSC_EN_MASK BIT(0) 129 /* CMN_REG(0075) */ 130 #define ANA_ROPLL_SSC_FM_DEVIATION_MASK GENMASK(5, 0) 131 /* CMN_REG(0076) */ 132 #define ANA_ROPLL_SSC_FM_FREQ_MASK GENMASK(6, 2) 133 /* CMN_REG(0077) */ 134 #define ANA_ROPLL_SSC_CLK_DIV_SEL_MASK GENMASK(6, 3) 135 /* CMN_REG(0081) */ 136 #define OVRD_PLL_CD_CLK_EN_MASK BIT(8) 137 #define ANA_PLL_CD_TX_SER_RATE_SEL_MASK BIT(3) 138 #define ANA_PLL_CD_HSCLK_WEST_EN_MASK BIT(1) 139 #define ANA_PLL_CD_HSCLK_EAST_EN_MASK BIT(0) 140 /* CMN_REG(0082) */ 141 #define ANA_PLL_CD_VREG_GAIN_CTRL_MASK GENMASK(3, 0) 142 /* CMN_REG(0083) */ 143 #define ANA_PLL_CD_VREG_ICTRL_MASK GENMASK(6, 5) 144 /* CMN_REG(0084) */ 145 #define PLL_LCRO_CLK_SEL_MASK BIT(5) 146 /* CMN_REG(0085) */ 147 #define ANA_PLL_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0) 148 /* CMN_REG(0086) */ 149 #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4) 150 #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1) 151 #define PLL_PCG_CLK_EN_MASK BIT(0) 152 /* CMN_REG(0087) */ 153 #define ANA_PLL_FRL_MODE_EN_MASK BIT(3) 154 #define ANA_PLL_TX_HS_CLK_EN_MASK BIT(2) 155 /* CMN_REG(0089) */ 156 #define LCPLL_ALONE_MODE_MASK BIT(1) 157 /* CMN_REG(0095) */ 158 #define DP_TX_LINK_BW_MASK GENMASK(1, 0) 159 /* CMN_REG(0097) */ 160 #define DIG_CLK_SEL_MASK BIT(1) 161 #define LCPLL_REF BIT(1) 162 #define ROPLL_REF 0 163 /* CMN_REG(0099) */ 164 #define SSC_EN_MASK GENMASK(7, 6) 165 #define CMN_ROPLL_ALONE_MODE_MASK BIT(2) 166 #define ROPLL_ALONE_MODE BIT(2) 167 /* CMN_REG(009a) */ 168 #define HS_SPEED_SEL_MASK BIT(0) 169 #define DIV_10_CLOCK BIT(0) 170 /* CMN_REG(009b) */ 171 #define LS_SPEED_SEL_MASK BIT(4) 172 #define LINK_SYMBOL_CLOCK BIT(4) 173 #define LINK_SYMBOL_CLOCK1_2 0 174 175 /* SB_REG(0102) */ 176 #define OVRD_SB_RXTERM_EN_MASK BIT(5) 177 #define SB_RXTERM_EN_MASK BIT(4) 178 #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0) 179 /* SB_REG(0103) */ 180 #define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3) 181 #define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1) 182 #define SB_RX_RESCAL_DONE_MASK BIT(0) 183 /* SB_REG(0104) */ 184 #define OVRD_SB_EN_MASK BIT(5) 185 #define SB_EN_MASK BIT(4) 186 #define OVRD_SB_AUX_EN_MASK BIT(1) 187 #define SB_AUX_EN_MASK BIT(0) 188 /* SB_REG(0105) */ 189 #define OVRD_SB_EARC_CMDC_EN_MASK BIT(6) 190 #define SB_EARC_CMDC_EN_MASK BIT(5) 191 #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0) 192 /* SB_REG(0106) */ 193 #define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4) 194 /* SB_REG(0109) */ 195 #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0) 196 /* SB_REG(010d) */ 197 #define ANA_SB_DMRX_LPBK_DATA_MASK BIT(4) 198 /* SB_REG(010f) */ 199 #define OVRD_SB_VREG_EN_MASK BIT(7) 200 #define SB_VREG_EN_MASK BIT(6) 201 #define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5) 202 #define SB_VREG_LPF_BYPASS_MASK BIT(4) 203 #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0) 204 /* SB_REG(0110) */ 205 #define ANA_SB_VREG_OUT_SEL_MASK BIT(1) 206 #define ANA_SB_VREG_REF_SEL_MASK BIT(0) 207 /* SB_REG(0113) */ 208 #define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4) 209 #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0) 210 /* SB_REG(0114) */ 211 #define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3) 212 #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0) 213 /* SB_REG(0115) */ 214 #define SB_READY_DELAY_TIME_MASK GENMASK(5, 3) 215 #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0) 216 /* SB_REG(0116) */ 217 #define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4) 218 /* SB_REG(0117) */ 219 #define FAST_PULSE_TIME_MASK GENMASK(3, 0) 220 /* SB_REG(0118) */ 221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK GENMASK(7, 0) 222 /* SB_REG(011a) */ 223 #define SB_TG_CNT_RUN_NO_7_0_MASK GENMASK(7, 0) 224 /* SB_REG(011b) */ 225 #define SB_EARC_SIG_DET_BYPASS_MASK BIT(4) 226 #define SB_AFC_TOL_MASK GENMASK(3, 0) 227 /* SB_REG(011c) */ 228 #define SB_AFC_STB_NUM_MASK GENMASK(3, 0) 229 /* SB_REG(011d) */ 230 #define SB_TG_OSC_CNT_MIN_MASK GENMASK(7, 0) 231 /* SB_REG(011e) */ 232 #define SB_TG_OSC_CNT_MAX_MASK GENMASK(7, 0) 233 /* SB_REG(011f) */ 234 #define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2) 235 #define SB_RCAL_RSTN_MASK BIT(1) 236 /* SB_REG(0120) */ 237 #define SB_AUX_EN_IN_MASK BIT(7) 238 #define SB_EARC_EN_MASK BIT(1) 239 #define SB_EARC_AFC_EN_MASK BIT(2) 240 /* SB_REG(0123) */ 241 #define OVRD_SB_READY_MASK BIT(5) 242 #define SB_READY_MASK BIT(4) 243 244 /* LNTOP_REG(0200) */ 245 #define PROTOCOL_SEL_MASK BIT(2) 246 #define HDMI_MODE BIT(2) 247 #define HDMI_TMDS_FRL_SEL BIT(1) 248 /* LNTOP_REG(0206) */ 249 #define DATA_BUS_WIDTH_MASK GENMASK(2, 1) 250 #define DATA_BUS_WIDTH_SEL_MASK BIT(0) 251 #define DATA_BUS_36_40 BIT(0) 252 /* LNTOP_REG(0207) */ 253 #define LANE_EN_MASK 0xf 254 #define ALL_LANE_EN 0xf 255 256 /* LANE_REG(0301) */ 257 #define OVRD_LN_TX_DRV_EI_EN_MASK BIT(7) 258 #define LN_TX_DRV_EI_EN_MASK BIT(6) 259 /* LANE_REG(0303) */ 260 #define OVRD_LN_TX_DRV_LVL_CTRL_MASK BIT(5) 261 #define LN_TX_DRV_LVL_CTRL_MASK GENMASK(4, 0) 262 /* LANE_REG(0304) */ 263 #define OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK BIT(4) 264 #define LN_TX_DRV_POST_LVL_CTRL_MASK GENMASK(3, 0) 265 /* LANE_REG(0305) */ 266 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK BIT(6) 267 #define LN_TX_DRV_PRE_LVL_CTRL_MASK GENMASK(5, 2) 268 /* LANE_REG(0306) */ 269 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK GENMASK(7, 5) 270 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK GENMASK(4, 2) 271 #define LN_ANA_TX_DRV_ACCDRV_EN_MASK BIT(0) 272 /* LANE_REG(0307) */ 273 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK BIT(6) 274 #define LN_ANA_TX_DRV_ACCDRV_CTRL_MASK GENMASK(5, 3) 275 /* LANE_REG(030a) */ 276 #define LN_ANA_TX_JEQ_EN_MASK BIT(4) 277 #define LN_TX_JEQ_EVEN_CTRL_RBR_MASK GENMASK(3, 0) 278 /* LANE_REG(030b) */ 279 #define LN_TX_JEQ_EVEN_CTRL_HBR_MASK GENMASK(7, 4) 280 #define LN_TX_JEQ_EVEN_CTRL_HBR2_MASK GENMASK(3, 0) 281 /* LANE_REG(030c) */ 282 #define LN_TX_JEQ_ODD_CTRL_RBR_MASK GENMASK(3, 0) 283 /* LANE_REG(030d) */ 284 #define LN_TX_JEQ_ODD_CTRL_HBR_MASK GENMASK(7, 4) 285 #define LN_TX_JEQ_ODD_CTRL_HBR2_MASK GENMASK(3, 0) 286 /* LANE_REG(0310) */ 287 #define LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0) 288 /* LANE_REG(0311) */ 289 #define LN_TX_SER_40BIT_EN_RBR_MASK BIT(3) 290 #define LN_TX_SER_40BIT_EN_HBR_MASK BIT(2) 291 #define LN_TX_SER_40BIT_EN_HBR2_MASK BIT(1) 292 /* LANE_REG(0312) */ 293 #define LN0_TX_SER_RATE_SEL_RBR_MASK BIT(5) 294 #define LN0_TX_SER_RATE_SEL_HBR_MASK BIT(4) 295 #define LN0_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 296 #define LN0_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 297 /* LANE_REG(0316) */ 298 #define LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK GENMASK(3, 0) 299 /* LANE_REG(031B) */ 300 #define LN_ANA_TX_RESERVED_MASK GENMASK(7, 0) 301 /* LANE_REG(031e) */ 302 #define LN_POLARITY_INV_MASK BIT(2) 303 #define LN_LANE_MODE_MASK BIT(1) 304 305 /* LANE_REG(0412) */ 306 #define LN1_TX_SER_RATE_SEL_RBR_MASK BIT(5) 307 #define LN1_TX_SER_RATE_SEL_HBR_MASK BIT(4) 308 #define LN1_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 309 #define LN1_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 310 311 /* LANE_REG(0512) */ 312 #define LN2_TX_SER_RATE_SEL_RBR_MASK BIT(5) 313 #define LN2_TX_SER_RATE_SEL_HBR_MASK BIT(4) 314 #define LN2_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 315 #define LN2_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 316 317 /* LANE_REG(0612) */ 318 #define LN3_TX_SER_RATE_SEL_RBR_MASK BIT(5) 319 #define LN3_TX_SER_RATE_SEL_HBR_MASK BIT(4) 320 #define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 321 #define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 322 323 #define HDMI14_MAX_RATE 340000000 324 #define HDMI20_MAX_RATE 600000000 325 326 enum dp_link_rate { 327 DP_BW_RBR, 328 DP_BW_HBR, 329 DP_BW_HBR2, 330 }; 331 332 struct ropll_config { 333 unsigned long long rate; 334 u8 pms_mdiv; 335 u8 pms_mdiv_afc; 336 u8 pms_pdiv; 337 u8 pms_refdiv; 338 u8 pms_sdiv; 339 u8 pms_iqdiv_rstn; 340 u8 ref_clk_sel; 341 u8 sdm_en; 342 u8 sdm_rstn; 343 u8 sdc_frac_en; 344 u8 sdc_rstn; 345 u8 sdm_clk_div; 346 u8 sdm_deno; 347 u8 sdm_num_sign; 348 u8 sdm_num; 349 u8 sdc_n; 350 u8 sdc_num; 351 u8 sdc_deno; 352 u8 sdc_ndiv_rstn; 353 u8 ssc_en; 354 u8 ssc_fm_dev; 355 u8 ssc_fm_freq; 356 u8 ssc_clk_div_sel; 357 u8 ana_cpp_ctrl; 358 u8 ana_lpf_c_sel; 359 u8 cd_tx_ser_rate_sel; 360 }; 361 362 struct tx_drv_ctrl { 363 u8 tx_drv_lvl_ctrl; 364 u8 tx_drv_post_lvl_ctrl; 365 u8 ana_tx_drv_idrv_idn_ctrl; 366 u8 ana_tx_drv_idrv_iup_ctrl; 367 u8 ana_tx_drv_accdrv_en; 368 u8 ana_tx_drv_accdrv_ctrl; 369 u8 tx_drv_pre_lvl_ctrl; 370 u8 ana_tx_jeq_en; 371 u8 tx_jeq_even_ctrl; 372 u8 tx_jeq_odd_ctrl; 373 }; 374 375 enum rk_hdptx_reset { 376 RST_APB = 0, 377 RST_INIT, 378 RST_CMN, 379 RST_LANE, 380 RST_MAX 381 }; 382 383 #define MAX_HDPTX_PHY_NUM 2 384 385 struct rk_hdptx_phy_cfg { 386 unsigned int num_phys; 387 unsigned int phy_ids[MAX_HDPTX_PHY_NUM]; 388 }; 389 390 struct rk_hdptx_phy { 391 struct device *dev; 392 struct regmap *regmap; 393 struct regmap *grf; 394 395 int phy_id; 396 struct phy *phy; 397 struct phy_configure_opts_hdmi hdmi_cfg; 398 struct clk_bulk_data *clks; 399 int nr_clks; 400 struct reset_control_bulk_data rsts[RST_MAX]; 401 402 /* clk provider */ 403 struct clk_hw hw; 404 unsigned long hw_rate; 405 bool restrict_rate_change; 406 407 atomic_t usage_count; 408 409 /* used for dp mode */ 410 unsigned int link_rate; 411 unsigned int lanes; 412 }; 413 414 static const struct ropll_config ropll_tmds_cfg[] = { 415 { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 416 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 417 { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 418 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 419 { 297000000ULL, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 420 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 421 { 162000000ULL, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 422 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 423 { 185625000ULL, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 424 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 425 { 154000000ULL, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, 426 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 427 { 148500000ULL, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 428 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 429 { 146250000ULL, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, 430 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 431 { 119000000ULL, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, 432 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 433 { 106500000ULL, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, 434 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 435 { 108000000ULL, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 436 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 437 { 85500000ULL, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, 438 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 439 { 83500000ULL, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, 440 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 441 { 92812500ULL, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 442 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 443 { 74250000ULL, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 444 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 445 { 65000000ULL, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, 446 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 447 { 50250000ULL, 84, 84, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 11, 1, 4, 5, 448 4, 11, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 449 { 33750000ULL, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 450 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 451 { 40000000ULL, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 452 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 453 { 27000000ULL, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 454 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 455 { 25175000ULL, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, 456 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 457 }; 458 459 static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = { 460 REG_SEQ0(CMN_REG(0009), 0x0c), 461 REG_SEQ0(CMN_REG(000a), 0x83), 462 REG_SEQ0(CMN_REG(000b), 0x06), 463 REG_SEQ0(CMN_REG(000c), 0x20), 464 REG_SEQ0(CMN_REG(000d), 0xb8), 465 REG_SEQ0(CMN_REG(000e), 0x0f), 466 REG_SEQ0(CMN_REG(000f), 0x0f), 467 REG_SEQ0(CMN_REG(0010), 0x04), 468 REG_SEQ0(CMN_REG(0011), 0x00), 469 REG_SEQ0(CMN_REG(0012), 0x26), 470 REG_SEQ0(CMN_REG(0013), 0x22), 471 REG_SEQ0(CMN_REG(0014), 0x24), 472 REG_SEQ0(CMN_REG(0015), 0x77), 473 REG_SEQ0(CMN_REG(0016), 0x08), 474 REG_SEQ0(CMN_REG(0017), 0x00), 475 REG_SEQ0(CMN_REG(0018), 0x04), 476 REG_SEQ0(CMN_REG(0019), 0x48), 477 REG_SEQ0(CMN_REG(001a), 0x01), 478 REG_SEQ0(CMN_REG(001b), 0x00), 479 REG_SEQ0(CMN_REG(001c), 0x01), 480 REG_SEQ0(CMN_REG(001d), 0x64), 481 REG_SEQ0(CMN_REG(001f), 0x00), 482 REG_SEQ0(CMN_REG(0026), 0x53), 483 REG_SEQ0(CMN_REG(0029), 0x01), 484 REG_SEQ0(CMN_REG(0030), 0x00), 485 REG_SEQ0(CMN_REG(0031), 0x20), 486 REG_SEQ0(CMN_REG(0032), 0x30), 487 REG_SEQ0(CMN_REG(0033), 0x0b), 488 REG_SEQ0(CMN_REG(0034), 0x23), 489 REG_SEQ0(CMN_REG(0035), 0x00), 490 REG_SEQ0(CMN_REG(0038), 0x00), 491 REG_SEQ0(CMN_REG(0039), 0x00), 492 REG_SEQ0(CMN_REG(003a), 0x00), 493 REG_SEQ0(CMN_REG(003b), 0x00), 494 REG_SEQ0(CMN_REG(003c), 0x80), 495 REG_SEQ0(CMN_REG(003e), 0x0c), 496 REG_SEQ0(CMN_REG(003f), 0x83), 497 REG_SEQ0(CMN_REG(0040), 0x06), 498 REG_SEQ0(CMN_REG(0041), 0x20), 499 REG_SEQ0(CMN_REG(0042), 0xb8), 500 REG_SEQ0(CMN_REG(0043), 0x00), 501 REG_SEQ0(CMN_REG(0044), 0x46), 502 REG_SEQ0(CMN_REG(0045), 0x24), 503 REG_SEQ0(CMN_REG(0046), 0xff), 504 REG_SEQ0(CMN_REG(0047), 0x00), 505 REG_SEQ0(CMN_REG(0048), 0x44), 506 REG_SEQ0(CMN_REG(0049), 0xfa), 507 REG_SEQ0(CMN_REG(004a), 0x08), 508 REG_SEQ0(CMN_REG(004b), 0x00), 509 REG_SEQ0(CMN_REG(004c), 0x01), 510 REG_SEQ0(CMN_REG(004d), 0x64), 511 REG_SEQ0(CMN_REG(004e), 0x14), 512 REG_SEQ0(CMN_REG(004f), 0x00), 513 REG_SEQ0(CMN_REG(0050), 0x00), 514 REG_SEQ0(CMN_REG(005d), 0x0c), 515 REG_SEQ0(CMN_REG(005f), 0x01), 516 REG_SEQ0(CMN_REG(006b), 0x04), 517 REG_SEQ0(CMN_REG(0073), 0x30), 518 REG_SEQ0(CMN_REG(0074), 0x00), 519 REG_SEQ0(CMN_REG(0075), 0x20), 520 REG_SEQ0(CMN_REG(0076), 0x30), 521 REG_SEQ0(CMN_REG(0077), 0x08), 522 REG_SEQ0(CMN_REG(0078), 0x0c), 523 REG_SEQ0(CMN_REG(0079), 0x00), 524 REG_SEQ0(CMN_REG(007b), 0x00), 525 REG_SEQ0(CMN_REG(007c), 0x00), 526 REG_SEQ0(CMN_REG(007d), 0x00), 527 REG_SEQ0(CMN_REG(007e), 0x00), 528 REG_SEQ0(CMN_REG(007f), 0x00), 529 REG_SEQ0(CMN_REG(0080), 0x00), 530 REG_SEQ0(CMN_REG(0081), 0x09), 531 REG_SEQ0(CMN_REG(0082), 0x04), 532 REG_SEQ0(CMN_REG(0083), 0x24), 533 REG_SEQ0(CMN_REG(0084), 0x20), 534 REG_SEQ0(CMN_REG(0085), 0x03), 535 REG_SEQ0(CMN_REG(0086), 0x01), 536 REG_SEQ0(CMN_REG(0087), 0x0c), 537 REG_SEQ0(CMN_REG(008a), 0x55), 538 REG_SEQ0(CMN_REG(008b), 0x25), 539 REG_SEQ0(CMN_REG(008c), 0x2c), 540 REG_SEQ0(CMN_REG(008d), 0x22), 541 REG_SEQ0(CMN_REG(008e), 0x14), 542 REG_SEQ0(CMN_REG(008f), 0x20), 543 REG_SEQ0(CMN_REG(0090), 0x00), 544 REG_SEQ0(CMN_REG(0091), 0x00), 545 REG_SEQ0(CMN_REG(0092), 0x00), 546 REG_SEQ0(CMN_REG(0093), 0x00), 547 REG_SEQ0(CMN_REG(009a), 0x11), 548 REG_SEQ0(CMN_REG(009b), 0x10), 549 }; 550 551 static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = { 552 REG_SEQ0(CMN_REG(0008), 0x00), 553 REG_SEQ0(CMN_REG(0011), 0x01), 554 REG_SEQ0(CMN_REG(0017), 0x20), 555 REG_SEQ0(CMN_REG(001e), 0x14), 556 REG_SEQ0(CMN_REG(0020), 0x00), 557 REG_SEQ0(CMN_REG(0021), 0x00), 558 REG_SEQ0(CMN_REG(0022), 0x11), 559 REG_SEQ0(CMN_REG(0023), 0x00), 560 REG_SEQ0(CMN_REG(0024), 0x00), 561 REG_SEQ0(CMN_REG(0025), 0x53), 562 REG_SEQ0(CMN_REG(0026), 0x00), 563 REG_SEQ0(CMN_REG(0027), 0x00), 564 REG_SEQ0(CMN_REG(0028), 0x01), 565 REG_SEQ0(CMN_REG(002a), 0x00), 566 REG_SEQ0(CMN_REG(002b), 0x00), 567 REG_SEQ0(CMN_REG(002c), 0x00), 568 REG_SEQ0(CMN_REG(002d), 0x00), 569 REG_SEQ0(CMN_REG(002e), 0x04), 570 REG_SEQ0(CMN_REG(002f), 0x00), 571 REG_SEQ0(CMN_REG(0030), 0x20), 572 REG_SEQ0(CMN_REG(0031), 0x30), 573 REG_SEQ0(CMN_REG(0032), 0x0b), 574 REG_SEQ0(CMN_REG(0033), 0x23), 575 REG_SEQ0(CMN_REG(0034), 0x00), 576 REG_SEQ0(CMN_REG(003d), 0x40), 577 REG_SEQ0(CMN_REG(0042), 0x78), 578 REG_SEQ0(CMN_REG(004e), 0x34), 579 REG_SEQ0(CMN_REG(005c), 0x25), 580 REG_SEQ0(CMN_REG(005e), 0x4f), 581 REG_SEQ0(CMN_REG(0074), 0x04), 582 REG_SEQ0(CMN_REG(0081), 0x01), 583 REG_SEQ0(CMN_REG(0087), 0x04), 584 REG_SEQ0(CMN_REG(0089), 0x00), 585 REG_SEQ0(CMN_REG(0095), 0x00), 586 REG_SEQ0(CMN_REG(0097), 0x02), 587 REG_SEQ0(CMN_REG(0099), 0x04), 588 REG_SEQ0(CMN_REG(009b), 0x00), 589 }; 590 591 static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = { 592 REG_SEQ0(SB_REG(0114), 0x00), 593 REG_SEQ0(SB_REG(0115), 0x00), 594 REG_SEQ0(SB_REG(0116), 0x00), 595 REG_SEQ0(SB_REG(0117), 0x00), 596 }; 597 598 static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = { 599 REG_SEQ0(LNTOP_REG(0201), 0x00), 600 REG_SEQ0(LNTOP_REG(0202), 0x00), 601 REG_SEQ0(LNTOP_REG(0203), 0x0f), 602 REG_SEQ0(LNTOP_REG(0204), 0xff), 603 REG_SEQ0(LNTOP_REG(0205), 0xff), 604 }; 605 606 static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = { 607 REG_SEQ0(LNTOP_REG(0201), 0x07), 608 REG_SEQ0(LNTOP_REG(0202), 0xc1), 609 REG_SEQ0(LNTOP_REG(0203), 0xf0), 610 REG_SEQ0(LNTOP_REG(0204), 0x7c), 611 REG_SEQ0(LNTOP_REG(0205), 0x1f), 612 }; 613 614 static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = { 615 REG_SEQ0(LANE_REG(0303), 0x0c), 616 REG_SEQ0(LANE_REG(0307), 0x20), 617 REG_SEQ0(LANE_REG(030a), 0x17), 618 REG_SEQ0(LANE_REG(030b), 0x77), 619 REG_SEQ0(LANE_REG(030c), 0x77), 620 REG_SEQ0(LANE_REG(030d), 0x77), 621 REG_SEQ0(LANE_REG(030e), 0x38), 622 REG_SEQ0(LANE_REG(0310), 0x03), 623 REG_SEQ0(LANE_REG(0311), 0x0f), 624 REG_SEQ0(LANE_REG(0316), 0x02), 625 REG_SEQ0(LANE_REG(031b), 0x01), 626 REG_SEQ0(LANE_REG(031f), 0x15), 627 REG_SEQ0(LANE_REG(0320), 0xa0), 628 REG_SEQ0(LANE_REG(0403), 0x0c), 629 REG_SEQ0(LANE_REG(0407), 0x20), 630 REG_SEQ0(LANE_REG(040a), 0x17), 631 REG_SEQ0(LANE_REG(040b), 0x77), 632 REG_SEQ0(LANE_REG(040c), 0x77), 633 REG_SEQ0(LANE_REG(040d), 0x77), 634 REG_SEQ0(LANE_REG(040e), 0x38), 635 REG_SEQ0(LANE_REG(0410), 0x03), 636 REG_SEQ0(LANE_REG(0411), 0x0f), 637 REG_SEQ0(LANE_REG(0416), 0x02), 638 REG_SEQ0(LANE_REG(041b), 0x01), 639 REG_SEQ0(LANE_REG(041f), 0x15), 640 REG_SEQ0(LANE_REG(0420), 0xa0), 641 REG_SEQ0(LANE_REG(0503), 0x0c), 642 REG_SEQ0(LANE_REG(0507), 0x20), 643 REG_SEQ0(LANE_REG(050a), 0x17), 644 REG_SEQ0(LANE_REG(050b), 0x77), 645 REG_SEQ0(LANE_REG(050c), 0x77), 646 REG_SEQ0(LANE_REG(050d), 0x77), 647 REG_SEQ0(LANE_REG(050e), 0x38), 648 REG_SEQ0(LANE_REG(0510), 0x03), 649 REG_SEQ0(LANE_REG(0511), 0x0f), 650 REG_SEQ0(LANE_REG(0516), 0x02), 651 REG_SEQ0(LANE_REG(051b), 0x01), 652 REG_SEQ0(LANE_REG(051f), 0x15), 653 REG_SEQ0(LANE_REG(0520), 0xa0), 654 REG_SEQ0(LANE_REG(0603), 0x0c), 655 REG_SEQ0(LANE_REG(0607), 0x20), 656 REG_SEQ0(LANE_REG(060a), 0x17), 657 REG_SEQ0(LANE_REG(060b), 0x77), 658 REG_SEQ0(LANE_REG(060c), 0x77), 659 REG_SEQ0(LANE_REG(060d), 0x77), 660 REG_SEQ0(LANE_REG(060e), 0x38), 661 REG_SEQ0(LANE_REG(0610), 0x03), 662 REG_SEQ0(LANE_REG(0611), 0x0f), 663 REG_SEQ0(LANE_REG(0616), 0x02), 664 REG_SEQ0(LANE_REG(061b), 0x01), 665 REG_SEQ0(LANE_REG(061f), 0x15), 666 REG_SEQ0(LANE_REG(0620), 0xa0), 667 }; 668 669 static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = { 670 REG_SEQ0(LANE_REG(0312), 0x00), 671 REG_SEQ0(LANE_REG(031e), 0x00), 672 REG_SEQ0(LANE_REG(0412), 0x00), 673 REG_SEQ0(LANE_REG(041e), 0x00), 674 REG_SEQ0(LANE_REG(0512), 0x00), 675 REG_SEQ0(LANE_REG(051e), 0x00), 676 REG_SEQ0(LANE_REG(0612), 0x00), 677 REG_SEQ0(LANE_REG(061e), 0x08), 678 REG_SEQ0(LANE_REG(0303), 0x2f), 679 REG_SEQ0(LANE_REG(0403), 0x2f), 680 REG_SEQ0(LANE_REG(0503), 0x2f), 681 REG_SEQ0(LANE_REG(0603), 0x2f), 682 REG_SEQ0(LANE_REG(0305), 0x03), 683 REG_SEQ0(LANE_REG(0405), 0x03), 684 REG_SEQ0(LANE_REG(0505), 0x03), 685 REG_SEQ0(LANE_REG(0605), 0x03), 686 REG_SEQ0(LANE_REG(0306), 0x1c), 687 REG_SEQ0(LANE_REG(0406), 0x1c), 688 REG_SEQ0(LANE_REG(0506), 0x1c), 689 REG_SEQ0(LANE_REG(0606), 0x1c), 690 }; 691 692 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = { 693 /* voltage swing 0, pre-emphasis 0->3 */ 694 { 695 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 696 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 697 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 698 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 699 }, 700 701 /* voltage swing 1, pre-emphasis 0->2 */ 702 { 703 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 704 { 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 705 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 706 }, 707 708 /* voltage swing 2, pre-emphasis 0->1 */ 709 { 710 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 711 { 0xc, 0x5, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 712 }, 713 714 /* voltage swing 3, pre-emphasis 0 */ 715 { 716 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, 717 } 718 }; 719 720 static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = { 721 /* voltage swing 0, pre-emphasis 0->3 */ 722 { 723 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 724 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 725 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 726 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 727 }, 728 729 /* voltage swing 1, pre-emphasis 0->2 */ 730 { 731 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 732 { 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 733 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 734 }, 735 736 /* voltage swing 2, pre-emphasis 0->1 */ 737 { 738 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 739 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 740 }, 741 742 /* voltage swing 3, pre-emphasis 0 */ 743 { 744 { 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, 745 } 746 }; 747 748 static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = { 749 /* voltage swing 0, pre-emphasis 0->3 */ 750 { 751 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 752 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 753 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4, 0x0, 0x1, 0x7, 0x7 }, 754 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 755 }, 756 757 /* voltage swing 1, pre-emphasis 0->2 */ 758 { 759 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 760 { 0xb, 0x7, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 761 { 0xd, 0x9, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 762 }, 763 764 /* voltage swing 2, pre-emphasis 0->1 */ 765 { 766 { 0x8, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 767 { 0xc, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 768 }, 769 770 /* voltage swing 3, pre-emphasis 0 */ 771 { 772 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, 773 } 774 }; 775 776 static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg) 777 { 778 switch (reg) { 779 case 0x0000 ... 0x029c: /* CMN Register */ 780 case 0x0400 ... 0x04a4: /* Sideband Register */ 781 case 0x0800 ... 0x08a4: /* Lane Top Register */ 782 case 0x0c00 ... 0x0cb4: /* Lane 0 Register */ 783 case 0x1000 ... 0x10b4: /* Lane 1 Register */ 784 case 0x1400 ... 0x14b4: /* Lane 2 Register */ 785 case 0x1800 ... 0x18b4: /* Lane 3 Register */ 786 return true; 787 } 788 789 return false; 790 } 791 792 static const struct regmap_config rk_hdptx_phy_regmap_config = { 793 .reg_bits = 32, 794 .reg_stride = 4, 795 .val_bits = 32, 796 .writeable_reg = rk_hdptx_phy_is_rw_reg, 797 .readable_reg = rk_hdptx_phy_is_rw_reg, 798 .max_register = 0x18b4, 799 }; 800 801 #define rk_hdptx_multi_reg_write(hdptx, seq) \ 802 regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq)) 803 804 static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx) 805 { 806 u32 val; 807 808 reset_control_assert(hdptx->rsts[RST_APB].rstc); 809 usleep_range(20, 25); 810 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 811 812 reset_control_assert(hdptx->rsts[RST_LANE].rstc); 813 reset_control_assert(hdptx->rsts[RST_CMN].rstc); 814 reset_control_assert(hdptx->rsts[RST_INIT].rstc); 815 816 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; 817 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 818 } 819 820 static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx) 821 { 822 u32 val; 823 int ret; 824 825 reset_control_deassert(hdptx->rsts[RST_LANE].rstc); 826 827 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | 828 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; 829 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 830 831 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, 832 (val & HDPTX_O_PHY_RDY) && 833 (val & HDPTX_O_PLL_LOCK_DONE), 834 100, 5000); 835 if (ret) { 836 dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n", ret); 837 return ret; 838 } 839 840 dev_dbg(hdptx->dev, "PHY lane locked\n"); 841 842 return 0; 843 } 844 845 static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx) 846 { 847 u32 val; 848 int ret; 849 850 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | 851 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; 852 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 853 854 usleep_range(10, 15); 855 reset_control_deassert(hdptx->rsts[RST_INIT].rstc); 856 857 usleep_range(10, 15); 858 val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN; 859 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 860 861 usleep_range(10, 15); 862 reset_control_deassert(hdptx->rsts[RST_CMN].rstc); 863 864 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, 865 val & HDPTX_O_PHY_CLK_RDY, 20, 400); 866 if (ret) { 867 dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n", ret); 868 return ret; 869 } 870 871 dev_dbg(hdptx->dev, "PHY clk ready\n"); 872 873 return 0; 874 } 875 876 static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) 877 { 878 u32 val; 879 880 reset_control_assert(hdptx->rsts[RST_APB].rstc); 881 usleep_range(20, 30); 882 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 883 884 regmap_write(hdptx->regmap, LANE_REG(0300), 0x82); 885 regmap_write(hdptx->regmap, SB_REG(010f), 0xc1); 886 regmap_write(hdptx->regmap, SB_REG(0110), 0x1); 887 regmap_write(hdptx->regmap, LANE_REG(0301), 0x80); 888 regmap_write(hdptx->regmap, LANE_REG(0401), 0x80); 889 regmap_write(hdptx->regmap, LANE_REG(0501), 0x80); 890 regmap_write(hdptx->regmap, LANE_REG(0601), 0x80); 891 892 reset_control_assert(hdptx->rsts[RST_LANE].rstc); 893 reset_control_assert(hdptx->rsts[RST_CMN].rstc); 894 reset_control_assert(hdptx->rsts[RST_INIT].rstc); 895 896 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; 897 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 898 } 899 900 static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate, 901 struct ropll_config *cfg) 902 { 903 const unsigned int fout = div_u64(rate, 200), fref = 24000; 904 unsigned long k = 0, lc, k_sub, lc_sub; 905 unsigned int fvco, sdc; 906 u32 mdiv, sdiv, n = 8; 907 908 if (fout > 0xfffffff) 909 return false; 910 911 for (sdiv = 16; sdiv >= 1; sdiv--) { 912 if (sdiv % 2 && sdiv != 1) 913 continue; 914 915 fvco = fout * sdiv; 916 917 if (fvco < 2000000 || fvco > 4000000) 918 continue; 919 920 mdiv = DIV_ROUND_UP(fvco, fref); 921 if (mdiv < 20 || mdiv > 255) 922 continue; 923 924 if (fref * mdiv - fvco) { 925 for (sdc = 264000; sdc <= 750000; sdc += fref) 926 if (sdc * n > fref * mdiv) 927 break; 928 929 if (sdc > 750000) 930 continue; 931 932 rational_best_approximation(fref * mdiv - fvco, 933 sdc / 16, 934 GENMASK(6, 0), 935 GENMASK(7, 0), 936 &k, &lc); 937 938 rational_best_approximation(sdc * n - fref * mdiv, 939 sdc, 940 GENMASK(6, 0), 941 GENMASK(7, 0), 942 &k_sub, &lc_sub); 943 } 944 945 break; 946 } 947 948 if (sdiv < 1) 949 return false; 950 951 if (cfg) { 952 cfg->pms_mdiv = mdiv; 953 cfg->pms_mdiv_afc = mdiv; 954 cfg->pms_pdiv = 1; 955 cfg->pms_refdiv = 1; 956 cfg->pms_sdiv = sdiv - 1; 957 958 cfg->sdm_en = k > 0 ? 1 : 0; 959 if (cfg->sdm_en) { 960 cfg->sdm_deno = lc; 961 cfg->sdm_num_sign = 1; 962 cfg->sdm_num = k; 963 cfg->sdc_n = n - 3; 964 cfg->sdc_num = k_sub; 965 cfg->sdc_deno = lc_sub; 966 } 967 } 968 969 return true; 970 } 971 972 static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx) 973 { 974 const struct ropll_config *cfg = NULL; 975 struct ropll_config rc = {0}; 976 int ret, i; 977 978 if (!hdptx->hdmi_cfg.tmds_char_rate) 979 return 0; 980 981 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) 982 if (hdptx->hdmi_cfg.tmds_char_rate == ropll_tmds_cfg[i].rate) { 983 cfg = &ropll_tmds_cfg[i]; 984 break; 985 } 986 987 if (!cfg) { 988 if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.tmds_char_rate, &rc)) { 989 dev_err(hdptx->dev, "%s cannot find pll cfg for rate=%llu\n", 990 __func__, hdptx->hdmi_cfg.tmds_char_rate); 991 return -EINVAL; 992 } 993 994 cfg = &rc; 995 } 996 997 dev_dbg(hdptx->dev, "%s rate=%llu mdiv=%u sdiv=%u sdm_en=%u k_sign=%u k=%u lc=%u\n", 998 __func__, hdptx->hdmi_cfg.tmds_char_rate, cfg->pms_mdiv, cfg->pms_sdiv + 1, 999 cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); 1000 1001 rk_hdptx_pre_power_up(hdptx); 1002 1003 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); 1004 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq); 1005 1006 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv); 1007 regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc); 1008 regmap_write(hdptx->regmap, CMN_REG(0059), 1009 (cfg->pms_pdiv << 4) | cfg->pms_refdiv); 1010 regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4); 1011 1012 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, 1013 FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en)); 1014 if (!cfg->sdm_en) 1015 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0); 1016 1017 regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK, 1018 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign)); 1019 1020 regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno); 1021 regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num); 1022 1023 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK, 1024 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n)); 1025 1026 regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num); 1027 regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno); 1028 1029 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, 1030 FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); 1031 1032 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, 1033 FIELD_PREP(PLL_PCG_CLK_SEL_MASK, (hdptx->hdmi_cfg.bpc - 8) >> 1)); 1034 1035 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, 1036 FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); 1037 1038 ret = rk_hdptx_post_enable_pll(hdptx); 1039 if (!ret) 1040 hdptx->hw_rate = hdptx->hdmi_cfg.tmds_char_rate; 1041 1042 return ret; 1043 } 1044 1045 static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx) 1046 { 1047 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); 1048 1049 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); 1050 1051 if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) { 1052 /* For 1/40 bitrate clk */ 1053 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); 1054 } else { 1055 /* For 1/10 bitrate clk */ 1056 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq); 1057 } 1058 1059 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); 1060 regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); 1061 1062 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); 1063 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq); 1064 1065 return rk_hdptx_post_enable_lane(hdptx); 1066 } 1067 1068 static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx) 1069 { 1070 reset_control_assert(hdptx->rsts[RST_LANE].rstc); 1071 reset_control_assert(hdptx->rsts[RST_CMN].rstc); 1072 reset_control_assert(hdptx->rsts[RST_INIT].rstc); 1073 1074 reset_control_assert(hdptx->rsts[RST_APB].rstc); 1075 udelay(10); 1076 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 1077 1078 regmap_update_bits(hdptx->regmap, LANE_REG(0301), 1079 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1080 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1081 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1082 regmap_update_bits(hdptx->regmap, LANE_REG(0401), 1083 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1084 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1085 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1086 regmap_update_bits(hdptx->regmap, LANE_REG(0501), 1087 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1088 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1089 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1090 regmap_update_bits(hdptx->regmap, LANE_REG(0601), 1091 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1092 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1093 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1094 1095 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1096 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0)); 1097 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1098 HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x0)); 1099 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1100 HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0)); 1101 } 1102 1103 static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx) 1104 { 1105 enum phy_mode mode = phy_get_mode(hdptx->phy); 1106 u32 status; 1107 int ret; 1108 1109 if (atomic_inc_return(&hdptx->usage_count) > 1) 1110 return 0; 1111 1112 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); 1113 if (ret) 1114 goto dec_usage; 1115 1116 if (status & HDPTX_O_PLL_LOCK_DONE) 1117 dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n"); 1118 1119 if (mode == PHY_MODE_DP) { 1120 rk_hdptx_dp_reset(hdptx); 1121 } else { 1122 ret = rk_hdptx_ropll_tmds_cmn_config(hdptx); 1123 if (ret) 1124 goto dec_usage; 1125 } 1126 1127 return 0; 1128 1129 dec_usage: 1130 atomic_dec(&hdptx->usage_count); 1131 return ret; 1132 } 1133 1134 static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force) 1135 { 1136 enum phy_mode mode = phy_get_mode(hdptx->phy); 1137 u32 status; 1138 int ret; 1139 1140 ret = atomic_dec_return(&hdptx->usage_count); 1141 if (ret > 0) 1142 return 0; 1143 1144 if (ret < 0) { 1145 dev_warn(hdptx->dev, "Usage count underflow!\n"); 1146 ret = -EINVAL; 1147 } else { 1148 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); 1149 if (!ret) { 1150 if (status & HDPTX_O_PLL_LOCK_DONE) { 1151 if (mode == PHY_MODE_DP) 1152 rk_hdptx_dp_reset(hdptx); 1153 else 1154 rk_hdptx_phy_disable(hdptx); 1155 } 1156 return 0; 1157 } else if (force) { 1158 return 0; 1159 } 1160 } 1161 1162 atomic_inc(&hdptx->usage_count); 1163 return ret; 1164 } 1165 1166 static void rk_hdptx_dp_pll_init(struct rk_hdptx_phy *hdptx) 1167 { 1168 regmap_update_bits(hdptx->regmap, CMN_REG(003c), ANA_LCPLL_RESERVED7_MASK, 1169 FIELD_PREP(ANA_LCPLL_RESERVED7_MASK, 0x1)); 1170 1171 regmap_update_bits(hdptx->regmap, CMN_REG(0046), 1172 ROPLL_ANA_CPP_CTRL_COARSE_MASK | ROPLL_ANA_CPP_CTRL_FINE_MASK, 1173 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE_MASK, 0xe) | 1174 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE_MASK, 0xe)); 1175 regmap_update_bits(hdptx->regmap, CMN_REG(0047), 1176 ROPLL_ANA_LPF_C_SEL_COARSE_MASK | 1177 ROPLL_ANA_LPF_C_SEL_FINE_MASK, 1178 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE_MASK, 0x4) | 1179 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE_MASK, 0x4)); 1180 1181 regmap_write(hdptx->regmap, CMN_REG(0051), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x87)); 1182 regmap_write(hdptx->regmap, CMN_REG(0052), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71)); 1183 regmap_write(hdptx->regmap, CMN_REG(0053), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71)); 1184 1185 regmap_write(hdptx->regmap, CMN_REG(0055), 1186 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x87)); 1187 regmap_write(hdptx->regmap, CMN_REG(0056), 1188 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71)); 1189 regmap_write(hdptx->regmap, CMN_REG(0057), 1190 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71)); 1191 1192 regmap_write(hdptx->regmap, CMN_REG(0059), 1193 FIELD_PREP(ANA_ROPLL_PMS_PDIV_MASK, 0x1) | 1194 FIELD_PREP(ANA_ROPLL_PMS_REFDIV_MASK, 0x1)); 1195 regmap_write(hdptx->regmap, CMN_REG(005a), 1196 FIELD_PREP(ROPLL_PMS_SDIV_RBR_MASK, 0x3) | 1197 FIELD_PREP(ROPLL_PMS_SDIV_HBR_MASK, 0x1)); 1198 regmap_update_bits(hdptx->regmap, CMN_REG(005b), ROPLL_PMS_SDIV_HBR2_MASK, 1199 FIELD_PREP(ROPLL_PMS_SDIV_HBR2_MASK, 0x0)); 1200 1201 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, 1202 FIELD_PREP(ROPLL_SDM_EN_MASK, 0x1)); 1203 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 1204 OVRD_ROPLL_SDM_RSTN_MASK | ROPLL_SDM_RSTN_MASK, 1205 FIELD_PREP(OVRD_ROPLL_SDM_RSTN_MASK, 0x1) | 1206 FIELD_PREP(ROPLL_SDM_RSTN_MASK, 0x1)); 1207 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_RBR_MASK, 1208 FIELD_PREP(ROPLL_SDC_FRAC_EN_RBR_MASK, 0x1)); 1209 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR_MASK, 1210 FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR_MASK, 0x1)); 1211 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR2_MASK, 1212 FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR2_MASK, 0x1)); 1213 1214 regmap_update_bits(hdptx->regmap, CMN_REG(005f), 1215 OVRD_ROPLL_SDC_RSTN_MASK | ROPLL_SDC_RSTN_MASK, 1216 FIELD_PREP(OVRD_ROPLL_SDC_RSTN_MASK, 0x1) | 1217 FIELD_PREP(ROPLL_SDC_RSTN_MASK, 0x1)); 1218 regmap_write(hdptx->regmap, CMN_REG(0060), 1219 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x21)); 1220 regmap_write(hdptx->regmap, CMN_REG(0061), 1221 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27)); 1222 regmap_write(hdptx->regmap, CMN_REG(0062), 1223 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27)); 1224 1225 regmap_update_bits(hdptx->regmap, CMN_REG(0064), 1226 ROPLL_SDM_NUM_SIGN_RBR_MASK | 1227 ROPLL_SDM_NUM_SIGN_HBR_MASK | 1228 ROPLL_SDM_NUM_SIGN_HBR2_MASK, 1229 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, 0x0) | 1230 FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR_MASK, 0x1) | 1231 FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR2_MASK, 0x1)); 1232 regmap_write(hdptx->regmap, CMN_REG(0065), 1233 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0x0)); 1234 regmap_write(hdptx->regmap, CMN_REG(0066), 1235 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd)); 1236 regmap_write(hdptx->regmap, CMN_REG(0067), 1237 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd)); 1238 1239 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK, 1240 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, 0x2)); 1241 1242 regmap_update_bits(hdptx->regmap, CMN_REG(006a), 1243 ROPLL_SDC_N_HBR_MASK | ROPLL_SDC_N_HBR2_MASK, 1244 FIELD_PREP(ROPLL_SDC_N_HBR_MASK, 0x1) | 1245 FIELD_PREP(ROPLL_SDC_N_HBR2_MASK, 0x1)); 1246 1247 regmap_write(hdptx->regmap, CMN_REG(006c), 1248 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x3)); 1249 regmap_write(hdptx->regmap, CMN_REG(006d), 1250 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7)); 1251 regmap_write(hdptx->regmap, CMN_REG(006e), 1252 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7)); 1253 1254 regmap_write(hdptx->regmap, CMN_REG(0070), 1255 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x8)); 1256 regmap_write(hdptx->regmap, CMN_REG(0071), 1257 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18)); 1258 regmap_write(hdptx->regmap, CMN_REG(0072), 1259 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18)); 1260 1261 regmap_update_bits(hdptx->regmap, CMN_REG(0074), 1262 OVRD_ROPLL_SDC_NDIV_RSTN_MASK | ROPLL_SDC_NDIV_RSTN_MASK, 1263 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN_MASK, 0x1) | 1264 FIELD_PREP(ROPLL_SDC_NDIV_RSTN_MASK, 0x1)); 1265 1266 regmap_update_bits(hdptx->regmap, CMN_REG(0077), ANA_ROPLL_SSC_CLK_DIV_SEL_MASK, 1267 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL_MASK, 0x1)); 1268 1269 regmap_update_bits(hdptx->regmap, CMN_REG(0081), ANA_PLL_CD_TX_SER_RATE_SEL_MASK, 1270 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL_MASK, 0x0)); 1271 regmap_update_bits(hdptx->regmap, CMN_REG(0081), 1272 ANA_PLL_CD_HSCLK_EAST_EN_MASK | ANA_PLL_CD_HSCLK_WEST_EN_MASK, 1273 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN_MASK, 0x1) | 1274 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN_MASK, 0x0)); 1275 1276 regmap_update_bits(hdptx->regmap, CMN_REG(0082), ANA_PLL_CD_VREG_GAIN_CTRL_MASK, 1277 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL_MASK, 0x4)); 1278 regmap_update_bits(hdptx->regmap, CMN_REG(0083), ANA_PLL_CD_VREG_ICTRL_MASK, 1279 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL_MASK, 0x1)); 1280 regmap_update_bits(hdptx->regmap, CMN_REG(0084), PLL_LCRO_CLK_SEL_MASK, 1281 FIELD_PREP(PLL_LCRO_CLK_SEL_MASK, 0x1)); 1282 regmap_update_bits(hdptx->regmap, CMN_REG(0085), ANA_PLL_SYNC_LOSS_DET_MODE_MASK, 1283 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE_MASK, 0x3)); 1284 1285 regmap_update_bits(hdptx->regmap, CMN_REG(0087), ANA_PLL_TX_HS_CLK_EN_MASK, 1286 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN_MASK, 0x1)); 1287 1288 regmap_update_bits(hdptx->regmap, CMN_REG(0097), DIG_CLK_SEL_MASK, 1289 FIELD_PREP(DIG_CLK_SEL_MASK, 0x1)); 1290 1291 regmap_update_bits(hdptx->regmap, CMN_REG(0099), CMN_ROPLL_ALONE_MODE_MASK, 1292 FIELD_PREP(CMN_ROPLL_ALONE_MODE_MASK, 0x1)); 1293 regmap_update_bits(hdptx->regmap, CMN_REG(009a), HS_SPEED_SEL_MASK, 1294 FIELD_PREP(HS_SPEED_SEL_MASK, 0x1)); 1295 regmap_update_bits(hdptx->regmap, CMN_REG(009b), LS_SPEED_SEL_MASK, 1296 FIELD_PREP(LS_SPEED_SEL_MASK, 0x1)); 1297 } 1298 1299 static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy *hdptx) 1300 { 1301 u32 status; 1302 int ret; 1303 1304 regmap_update_bits(hdptx->regmap, SB_REG(0102), ANA_SB_RXTERM_OFFSP_MASK, 1305 FIELD_PREP(ANA_SB_RXTERM_OFFSP_MASK, 0x3)); 1306 regmap_update_bits(hdptx->regmap, SB_REG(0103), ANA_SB_RXTERM_OFFSN_MASK, 1307 FIELD_PREP(ANA_SB_RXTERM_OFFSN_MASK, 0x3)); 1308 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK, 1309 FIELD_PREP(SB_AUX_EN_MASK, 0x1)); 1310 regmap_update_bits(hdptx->regmap, SB_REG(0105), ANA_SB_TX_HLVL_PROG_MASK, 1311 FIELD_PREP(ANA_SB_TX_HLVL_PROG_MASK, 0x7)); 1312 regmap_update_bits(hdptx->regmap, SB_REG(0106), ANA_SB_TX_LLVL_PROG_MASK, 1313 FIELD_PREP(ANA_SB_TX_LLVL_PROG_MASK, 0x7)); 1314 1315 regmap_update_bits(hdptx->regmap, SB_REG(010d), ANA_SB_DMRX_LPBK_DATA_MASK, 1316 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA_MASK, 0x1)); 1317 1318 regmap_update_bits(hdptx->regmap, SB_REG(010f), ANA_SB_VREG_GAIN_CTRL_MASK, 1319 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL_MASK, 0x0)); 1320 regmap_update_bits(hdptx->regmap, SB_REG(0110), 1321 ANA_SB_VREG_OUT_SEL_MASK | ANA_SB_VREG_REF_SEL_MASK, 1322 FIELD_PREP(ANA_SB_VREG_OUT_SEL_MASK, 0x1) | 1323 FIELD_PREP(ANA_SB_VREG_REF_SEL_MASK, 0x1)); 1324 1325 regmap_update_bits(hdptx->regmap, SB_REG(0113), 1326 SB_RX_RCAL_OPT_CODE_MASK | SB_RX_RTERM_CTRL_MASK, 1327 FIELD_PREP(SB_RX_RCAL_OPT_CODE_MASK, 0x1) | 1328 FIELD_PREP(SB_RX_RTERM_CTRL_MASK, 0x3)); 1329 regmap_update_bits(hdptx->regmap, SB_REG(0114), 1330 SB_TG_SB_EN_DELAY_TIME_MASK | SB_TG_RXTERM_EN_DELAY_TIME_MASK, 1331 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME_MASK, 0x2) | 1332 FIELD_PREP(SB_TG_RXTERM_EN_DELAY_TIME_MASK, 0x2)); 1333 regmap_update_bits(hdptx->regmap, SB_REG(0115), 1334 SB_READY_DELAY_TIME_MASK | SB_TG_OSC_EN_DELAY_TIME_MASK, 1335 FIELD_PREP(SB_READY_DELAY_TIME_MASK, 0x2) | 1336 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME_MASK, 0x2)); 1337 regmap_update_bits(hdptx->regmap, SB_REG(0116), 1338 AFC_RSTN_DELAY_TIME_MASK, 1339 FIELD_PREP(AFC_RSTN_DELAY_TIME_MASK, 0x2)); 1340 regmap_update_bits(hdptx->regmap, SB_REG(0117), 1341 FAST_PULSE_TIME_MASK, 1342 FIELD_PREP(FAST_PULSE_TIME_MASK, 0x4)); 1343 regmap_update_bits(hdptx->regmap, SB_REG(0118), 1344 SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK, 1345 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK, 0xa)); 1346 1347 regmap_update_bits(hdptx->regmap, SB_REG(011a), SB_TG_CNT_RUN_NO_7_0_MASK, 1348 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0_MASK, 0x3)); 1349 regmap_update_bits(hdptx->regmap, SB_REG(011b), 1350 SB_EARC_SIG_DET_BYPASS_MASK | SB_AFC_TOL_MASK, 1351 FIELD_PREP(SB_EARC_SIG_DET_BYPASS_MASK, 0x1) | 1352 FIELD_PREP(SB_AFC_TOL_MASK, 0x3)); 1353 regmap_update_bits(hdptx->regmap, SB_REG(011c), SB_AFC_STB_NUM_MASK, 1354 FIELD_PREP(SB_AFC_STB_NUM_MASK, 0x4)); 1355 regmap_update_bits(hdptx->regmap, SB_REG(011d), SB_TG_OSC_CNT_MIN_MASK, 1356 FIELD_PREP(SB_TG_OSC_CNT_MIN_MASK, 0x67)); 1357 regmap_update_bits(hdptx->regmap, SB_REG(011e), SB_TG_OSC_CNT_MAX_MASK, 1358 FIELD_PREP(SB_TG_OSC_CNT_MAX_MASK, 0x6a)); 1359 regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_PWM_AFC_CTRL_MASK, 1360 FIELD_PREP(SB_PWM_AFC_CTRL_MASK, 0x5)); 1361 regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_RCAL_RSTN_MASK, 1362 FIELD_PREP(SB_RCAL_RSTN_MASK, 0x1)); 1363 regmap_update_bits(hdptx->regmap, SB_REG(0120), SB_AUX_EN_IN_MASK, 1364 FIELD_PREP(SB_AUX_EN_IN_MASK, 0x1)); 1365 1366 regmap_update_bits(hdptx->regmap, SB_REG(0102), OVRD_SB_RXTERM_EN_MASK, 1367 FIELD_PREP(OVRD_SB_RXTERM_EN_MASK, 0x1)); 1368 regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK, 1369 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1)); 1370 regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_EN_MASK, 1371 FIELD_PREP(OVRD_SB_EN_MASK, 0x1)); 1372 regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_AUX_EN_MASK, 1373 FIELD_PREP(OVRD_SB_AUX_EN_MASK, 0x1)); 1374 1375 regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_EN_MASK, 1376 FIELD_PREP(OVRD_SB_VREG_EN_MASK, 0x1)); 1377 1378 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1379 HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x1)); 1380 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1381 HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x1)); 1382 usleep_range(20, 25); 1383 1384 reset_control_deassert(hdptx->rsts[RST_INIT].rstc); 1385 usleep_range(20, 25); 1386 reset_control_deassert(hdptx->rsts[RST_CMN].rstc); 1387 usleep_range(20, 25); 1388 1389 regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK, 1390 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1)); 1391 usleep_range(100, 110); 1392 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_EN_MASK, 1393 FIELD_PREP(SB_EN_MASK, 0x1)); 1394 usleep_range(100, 110); 1395 regmap_update_bits(hdptx->regmap, SB_REG(0102), SB_RXTERM_EN_MASK, 1396 FIELD_PREP(SB_RXTERM_EN_MASK, 0x1)); 1397 usleep_range(20, 25); 1398 regmap_update_bits(hdptx->regmap, SB_REG(010f), SB_VREG_EN_MASK, 1399 FIELD_PREP(SB_VREG_EN_MASK, 0x1)); 1400 usleep_range(20, 25); 1401 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK, 1402 FIELD_PREP(SB_AUX_EN_MASK, 0x1)); 1403 usleep_range(100, 110); 1404 1405 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, 1406 status, FIELD_GET(HDPTX_O_SB_RDY, status), 1407 50, 1000); 1408 if (ret) { 1409 dev_err(hdptx->dev, "Failed to get phy sb ready: %d\n", ret); 1410 return ret; 1411 } 1412 1413 return 0; 1414 } 1415 1416 static int rk_hdptx_phy_power_on(struct phy *phy) 1417 { 1418 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1419 enum phy_mode mode = phy_get_mode(phy); 1420 int ret, lane; 1421 1422 if (mode != PHY_MODE_DP) { 1423 if (!hdptx->hdmi_cfg.tmds_char_rate) { 1424 /* 1425 * FIXME: Temporary workaround to setup TMDS char rate 1426 * from the RK DW HDMI QP bridge driver. 1427 * Will be removed as soon the switch to the HDMI PHY 1428 * configuration API has been completed on both ends. 1429 */ 1430 hdptx->hdmi_cfg.tmds_char_rate = phy_get_bus_width(hdptx->phy) & 0xfffffff; 1431 hdptx->hdmi_cfg.tmds_char_rate *= 100; 1432 } 1433 1434 dev_dbg(hdptx->dev, "%s rate=%llu bpc=%u\n", __func__, 1435 hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc); 1436 } 1437 1438 ret = rk_hdptx_phy_consumer_get(hdptx); 1439 if (ret) 1440 return ret; 1441 1442 if (mode == PHY_MODE_DP) { 1443 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1444 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x1)); 1445 1446 for (lane = 0; lane < 4; lane++) { 1447 regmap_update_bits(hdptx->regmap, LANE_REG(031e) + 0x400 * lane, 1448 LN_POLARITY_INV_MASK | LN_LANE_MODE_MASK, 1449 FIELD_PREP(LN_POLARITY_INV_MASK, 0) | 1450 FIELD_PREP(LN_LANE_MODE_MASK, 1)); 1451 } 1452 1453 regmap_update_bits(hdptx->regmap, LNTOP_REG(0200), PROTOCOL_SEL_MASK, 1454 FIELD_PREP(PROTOCOL_SEL_MASK, 0x0)); 1455 regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_MASK, 1456 FIELD_PREP(DATA_BUS_WIDTH_MASK, 0x1)); 1457 regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_SEL_MASK, 1458 FIELD_PREP(DATA_BUS_WIDTH_SEL_MASK, 0x0)); 1459 1460 rk_hdptx_dp_pll_init(hdptx); 1461 1462 ret = rk_hdptx_dp_aux_init(hdptx); 1463 if (ret) 1464 rk_hdptx_phy_consumer_put(hdptx, true); 1465 } else { 1466 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1467 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); 1468 1469 ret = rk_hdptx_ropll_tmds_mode_config(hdptx); 1470 if (ret) 1471 rk_hdptx_phy_consumer_put(hdptx, true); 1472 } 1473 1474 return ret; 1475 } 1476 1477 static int rk_hdptx_phy_power_off(struct phy *phy) 1478 { 1479 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1480 1481 return rk_hdptx_phy_consumer_put(hdptx, false); 1482 } 1483 1484 static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx, 1485 struct phy_configure_opts_hdmi *hdmi) 1486 { 1487 int i; 1488 1489 if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) 1490 return -EINVAL; 1491 1492 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) 1493 if (hdmi->tmds_char_rate == ropll_tmds_cfg[i].rate) 1494 break; 1495 1496 if (i == ARRAY_SIZE(ropll_tmds_cfg) && 1497 !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL)) 1498 return -EINVAL; 1499 1500 if (!hdmi->bpc) 1501 hdmi->bpc = 8; 1502 1503 switch (hdmi->bpc) { 1504 case 8: 1505 case 10: 1506 case 12: 1507 case 16: 1508 break; 1509 default: 1510 return -EINVAL; 1511 } 1512 1513 return 0; 1514 } 1515 1516 static int rk_hdptx_phy_verify_dp_config(struct rk_hdptx_phy *hdptx, 1517 struct phy_configure_opts_dp *dp) 1518 { 1519 int i; 1520 1521 if (dp->set_rate) { 1522 switch (dp->link_rate) { 1523 case 1620: 1524 case 2700: 1525 case 5400: 1526 break; 1527 default: 1528 return -EINVAL; 1529 } 1530 } 1531 1532 if (dp->set_lanes) { 1533 switch (dp->lanes) { 1534 case 1: 1535 case 2: 1536 case 4: 1537 break; 1538 default: 1539 return -EINVAL; 1540 } 1541 } 1542 1543 if (dp->set_voltages) { 1544 for (i = 0; i < hdptx->lanes; i++) { 1545 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 1546 return -EINVAL; 1547 1548 if (dp->voltage[i] + dp->pre[i] > 3) 1549 return -EINVAL; 1550 } 1551 } 1552 1553 return 0; 1554 } 1555 1556 static int rk_hdptx_phy_set_rate(struct rk_hdptx_phy *hdptx, 1557 struct phy_configure_opts_dp *dp) 1558 { 1559 u32 bw, status; 1560 int ret; 1561 1562 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1563 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0)); 1564 1565 switch (dp->link_rate) { 1566 case 1620: 1567 bw = DP_BW_RBR; 1568 break; 1569 case 2700: 1570 bw = DP_BW_HBR; 1571 break; 1572 case 5400: 1573 bw = DP_BW_HBR2; 1574 break; 1575 default: 1576 return -EINVAL; 1577 } 1578 hdptx->link_rate = dp->link_rate; 1579 1580 regmap_update_bits(hdptx->regmap, CMN_REG(0008), OVRD_LCPLL_EN_MASK | LCPLL_EN_MASK, 1581 FIELD_PREP(OVRD_LCPLL_EN_MASK, 0x1) | 1582 FIELD_PREP(LCPLL_EN_MASK, 0x0)); 1583 1584 regmap_update_bits(hdptx->regmap, CMN_REG(003d), OVRD_ROPLL_EN_MASK | ROPLL_EN_MASK, 1585 FIELD_PREP(OVRD_ROPLL_EN_MASK, 0x1) | 1586 FIELD_PREP(ROPLL_EN_MASK, 0x1)); 1587 1588 if (dp->ssc) { 1589 regmap_update_bits(hdptx->regmap, CMN_REG(0074), 1590 OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK, 1591 FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) | 1592 FIELD_PREP(ROPLL_SSC_EN_MASK, 0x1)); 1593 regmap_write(hdptx->regmap, CMN_REG(0075), 1594 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0xc)); 1595 regmap_update_bits(hdptx->regmap, CMN_REG(0076), 1596 ANA_ROPLL_SSC_FM_FREQ_MASK, 1597 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0x1f)); 1598 1599 regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK, 1600 FIELD_PREP(SSC_EN_MASK, 0x2)); 1601 } else { 1602 regmap_update_bits(hdptx->regmap, CMN_REG(0074), 1603 OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK, 1604 FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) | 1605 FIELD_PREP(ROPLL_SSC_EN_MASK, 0x0)); 1606 regmap_write(hdptx->regmap, CMN_REG(0075), 1607 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0x20)); 1608 regmap_update_bits(hdptx->regmap, CMN_REG(0076), 1609 ANA_ROPLL_SSC_FM_FREQ_MASK, 1610 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0xc)); 1611 1612 regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK, 1613 FIELD_PREP(SSC_EN_MASK, 0x0)); 1614 } 1615 1616 regmap_update_bits(hdptx->regmap, CMN_REG(0095), DP_TX_LINK_BW_MASK, 1617 FIELD_PREP(DP_TX_LINK_BW_MASK, bw)); 1618 1619 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1620 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x1)); 1621 1622 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, 1623 status, FIELD_GET(HDPTX_O_PLL_LOCK_DONE, status), 1624 50, 1000); 1625 if (ret) { 1626 dev_err(hdptx->dev, "Failed to get phy pll lock: %d\n", ret); 1627 return ret; 1628 } 1629 1630 return 0; 1631 } 1632 1633 static int rk_hdptx_phy_set_lanes(struct rk_hdptx_phy *hdptx, 1634 struct phy_configure_opts_dp *dp) 1635 { 1636 hdptx->lanes = dp->lanes; 1637 1638 regmap_update_bits(hdptx->regmap, LNTOP_REG(0207), LANE_EN_MASK, 1639 FIELD_PREP(LANE_EN_MASK, GENMASK(hdptx->lanes - 1, 0))); 1640 1641 return 0; 1642 } 1643 1644 static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx, 1645 struct phy_configure_opts_dp *dp, 1646 u8 lane) 1647 { 1648 const struct tx_drv_ctrl *ctrl; 1649 u32 offset = lane * 0x400; 1650 1651 switch (hdptx->link_rate) { 1652 case 1620: 1653 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; 1654 regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset, 1655 LN_TX_JEQ_EVEN_CTRL_RBR_MASK, 1656 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK, 1657 ctrl->tx_jeq_even_ctrl)); 1658 regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset, 1659 LN_TX_JEQ_ODD_CTRL_RBR_MASK, 1660 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK, 1661 ctrl->tx_jeq_odd_ctrl)); 1662 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, 1663 LN_TX_SER_40BIT_EN_RBR_MASK, 1664 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1)); 1665 break; 1666 case 2700: 1667 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; 1668 regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, 1669 LN_TX_JEQ_EVEN_CTRL_HBR_MASK, 1670 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK, 1671 ctrl->tx_jeq_even_ctrl)); 1672 regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, 1673 LN_TX_JEQ_ODD_CTRL_HBR_MASK, 1674 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK, 1675 ctrl->tx_jeq_odd_ctrl)); 1676 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, 1677 LN_TX_SER_40BIT_EN_HBR_MASK, 1678 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1)); 1679 break; 1680 case 5400: 1681 default: 1682 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]]; 1683 regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, 1684 LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, 1685 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, 1686 ctrl->tx_jeq_even_ctrl)); 1687 regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, 1688 LN_TX_JEQ_ODD_CTRL_HBR2_MASK, 1689 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK, 1690 ctrl->tx_jeq_odd_ctrl)); 1691 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, 1692 LN_TX_SER_40BIT_EN_HBR2_MASK, 1693 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1)); 1694 break; 1695 } 1696 1697 regmap_update_bits(hdptx->regmap, LANE_REG(0303) + offset, 1698 OVRD_LN_TX_DRV_LVL_CTRL_MASK | LN_TX_DRV_LVL_CTRL_MASK, 1699 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL_MASK, 0x1) | 1700 FIELD_PREP(LN_TX_DRV_LVL_CTRL_MASK, 1701 ctrl->tx_drv_lvl_ctrl)); 1702 regmap_update_bits(hdptx->regmap, LANE_REG(0304) + offset, 1703 OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK | 1704 LN_TX_DRV_POST_LVL_CTRL_MASK, 1705 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK, 0x1) | 1706 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, 1707 ctrl->tx_drv_post_lvl_ctrl)); 1708 regmap_update_bits(hdptx->regmap, LANE_REG(0305) + offset, 1709 OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK | 1710 LN_TX_DRV_PRE_LVL_CTRL_MASK, 1711 FIELD_PREP(OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK, 0x1) | 1712 FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, 1713 ctrl->tx_drv_pre_lvl_ctrl)); 1714 regmap_update_bits(hdptx->regmap, LANE_REG(0306) + offset, 1715 LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK | 1716 LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK | 1717 LN_ANA_TX_DRV_ACCDRV_EN_MASK, 1718 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK, 1719 ctrl->ana_tx_drv_idrv_idn_ctrl) | 1720 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK, 1721 ctrl->ana_tx_drv_idrv_iup_ctrl) | 1722 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN_MASK, 1723 ctrl->ana_tx_drv_accdrv_en)); 1724 regmap_update_bits(hdptx->regmap, LANE_REG(0307) + offset, 1725 LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK | 1726 LN_ANA_TX_DRV_ACCDRV_CTRL_MASK, 1727 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK, 0x1) | 1728 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL_MASK, 1729 ctrl->ana_tx_drv_accdrv_ctrl)); 1730 1731 regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset, 1732 LN_ANA_TX_JEQ_EN_MASK, 1733 FIELD_PREP(LN_ANA_TX_JEQ_EN_MASK, ctrl->ana_tx_jeq_en)); 1734 1735 regmap_update_bits(hdptx->regmap, LANE_REG(0310) + offset, 1736 LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK, 1737 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK, 0x3)); 1738 1739 regmap_update_bits(hdptx->regmap, LANE_REG(0316) + offset, 1740 LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK, 1741 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK, 0x2)); 1742 1743 regmap_update_bits(hdptx->regmap, LANE_REG(031b) + offset, 1744 LN_ANA_TX_RESERVED_MASK, 1745 FIELD_PREP(LN_ANA_TX_RESERVED_MASK, 0x1)); 1746 } 1747 1748 static int rk_hdptx_phy_set_voltages(struct rk_hdptx_phy *hdptx, 1749 struct phy_configure_opts_dp *dp) 1750 { 1751 u8 lane; 1752 u32 status; 1753 int ret; 1754 1755 for (lane = 0; lane < hdptx->lanes; lane++) 1756 rk_hdptx_phy_set_voltage(hdptx, dp, lane); 1757 1758 reset_control_deassert(hdptx->rsts[RST_LANE].rstc); 1759 1760 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, 1761 status, FIELD_GET(HDPTX_O_PHY_RDY, status), 1762 50, 5000); 1763 if (ret) { 1764 dev_err(hdptx->dev, "Failed to get phy ready: %d\n", ret); 1765 return ret; 1766 } 1767 1768 return 0; 1769 } 1770 1771 static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opts) 1772 { 1773 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1774 enum phy_mode mode = phy_get_mode(phy); 1775 int ret; 1776 1777 if (mode != PHY_MODE_DP) { 1778 ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); 1779 if (ret) { 1780 dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); 1781 } else { 1782 hdptx->hdmi_cfg = opts->hdmi; 1783 hdptx->restrict_rate_change = true; 1784 } 1785 1786 dev_dbg(hdptx->dev, "%s rate=%llu bpc=%u\n", __func__, 1787 hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc); 1788 return ret; 1789 } 1790 1791 ret = rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp); 1792 if (ret) { 1793 dev_err(hdptx->dev, "invalid dp params for phy configure\n"); 1794 return ret; 1795 } 1796 1797 if (opts->dp.set_rate) { 1798 ret = rk_hdptx_phy_set_rate(hdptx, &opts->dp); 1799 if (ret) { 1800 dev_err(hdptx->dev, "failed to set rate: %d\n", ret); 1801 return ret; 1802 } 1803 } 1804 1805 if (opts->dp.set_lanes) { 1806 ret = rk_hdptx_phy_set_lanes(hdptx, &opts->dp); 1807 if (ret) { 1808 dev_err(hdptx->dev, "failed to set lanes: %d\n", ret); 1809 return ret; 1810 } 1811 } 1812 1813 if (opts->dp.set_voltages) { 1814 ret = rk_hdptx_phy_set_voltages(hdptx, &opts->dp); 1815 if (ret) { 1816 dev_err(hdptx->dev, "failed to set voltages: %d\n", 1817 ret); 1818 return ret; 1819 } 1820 } 1821 1822 return 0; 1823 } 1824 1825 static int rk_hdptx_phy_validate(struct phy *phy, enum phy_mode mode, 1826 int submode, union phy_configure_opts *opts) 1827 { 1828 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1829 1830 if (mode != PHY_MODE_DP) 1831 return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); 1832 1833 return rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp); 1834 } 1835 1836 static const struct phy_ops rk_hdptx_phy_ops = { 1837 .power_on = rk_hdptx_phy_power_on, 1838 .power_off = rk_hdptx_phy_power_off, 1839 .configure = rk_hdptx_phy_configure, 1840 .validate = rk_hdptx_phy_validate, 1841 .owner = THIS_MODULE, 1842 }; 1843 1844 static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw) 1845 { 1846 return container_of(hw, struct rk_hdptx_phy, hw); 1847 } 1848 1849 static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) 1850 { 1851 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1852 1853 return rk_hdptx_phy_consumer_get(hdptx); 1854 } 1855 1856 static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) 1857 { 1858 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1859 1860 rk_hdptx_phy_consumer_put(hdptx, true); 1861 } 1862 1863 static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, 1864 unsigned long parent_rate) 1865 { 1866 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1867 1868 return hdptx->hw_rate; 1869 } 1870 1871 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, 1872 unsigned long *parent_rate) 1873 { 1874 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1875 1876 /* 1877 * FIXME: Temporarily allow altering TMDS char rate via CCF. 1878 * To be dropped as soon as the RK DW HDMI QP bridge driver 1879 * switches to make use of phy_configure(). 1880 */ 1881 if (!hdptx->restrict_rate_change && rate != hdptx->hdmi_cfg.tmds_char_rate) { 1882 struct phy_configure_opts_hdmi hdmi = { 1883 .tmds_char_rate = rate, 1884 }; 1885 int ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi); 1886 1887 if (ret) 1888 return ret; 1889 1890 hdptx->hdmi_cfg = hdmi; 1891 } 1892 1893 /* 1894 * The TMDS char rate shall be adjusted via phy_configure() only, 1895 * hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with 1896 * a different rate argument. 1897 */ 1898 return hdptx->hdmi_cfg.tmds_char_rate; 1899 } 1900 1901 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, 1902 unsigned long parent_rate) 1903 { 1904 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1905 1906 /* Revert any unlikely TMDS char rate change since round_rate() */ 1907 if (hdptx->hdmi_cfg.tmds_char_rate != rate) { 1908 dev_warn(hdptx->dev, "Reverting unexpected rate change from %lu to %llu\n", 1909 rate, hdptx->hdmi_cfg.tmds_char_rate); 1910 hdptx->hdmi_cfg.tmds_char_rate = rate; 1911 } 1912 1913 /* 1914 * The TMDS char rate would be normally programmed in HW during 1915 * phy_ops.power_on() or clk_ops.prepare() callbacks, but it might 1916 * happen that the former gets fired too late, i.e. after this call, 1917 * while the latter being executed only once, i.e. when clock remains 1918 * in the prepared state during rate changes. 1919 */ 1920 return rk_hdptx_ropll_tmds_cmn_config(hdptx); 1921 } 1922 1923 static const struct clk_ops hdptx_phy_clk_ops = { 1924 .prepare = rk_hdptx_phy_clk_prepare, 1925 .unprepare = rk_hdptx_phy_clk_unprepare, 1926 .recalc_rate = rk_hdptx_phy_clk_recalc_rate, 1927 .round_rate = rk_hdptx_phy_clk_round_rate, 1928 .set_rate = rk_hdptx_phy_clk_set_rate, 1929 }; 1930 1931 static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx) 1932 { 1933 struct device *dev = hdptx->dev; 1934 const char *name, *pname; 1935 struct clk *refclk; 1936 int ret; 1937 1938 refclk = devm_clk_get(dev, "ref"); 1939 if (IS_ERR(refclk)) 1940 return dev_err_probe(dev, PTR_ERR(refclk), 1941 "Failed to get ref clock\n"); 1942 1943 name = hdptx->phy_id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0"; 1944 pname = __clk_get_name(refclk); 1945 1946 hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops, 1947 CLK_GET_RATE_NOCACHE); 1948 1949 ret = devm_clk_hw_register(dev, &hdptx->hw); 1950 if (ret) 1951 return dev_err_probe(dev, ret, "Failed to register clock\n"); 1952 1953 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw); 1954 if (ret) 1955 return dev_err_probe(dev, ret, 1956 "Failed to register clk provider\n"); 1957 return 0; 1958 } 1959 1960 static int rk_hdptx_phy_runtime_suspend(struct device *dev) 1961 { 1962 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); 1963 1964 clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks); 1965 1966 return 0; 1967 } 1968 1969 static int rk_hdptx_phy_runtime_resume(struct device *dev) 1970 { 1971 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); 1972 int ret; 1973 1974 ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks); 1975 if (ret) 1976 dev_err(hdptx->dev, "Failed to enable clocks: %d\n", ret); 1977 1978 return ret; 1979 } 1980 1981 static int rk_hdptx_phy_probe(struct platform_device *pdev) 1982 { 1983 const struct rk_hdptx_phy_cfg *cfgs; 1984 struct phy_provider *phy_provider; 1985 struct device *dev = &pdev->dev; 1986 struct rk_hdptx_phy *hdptx; 1987 struct resource *res; 1988 void __iomem *regs; 1989 int ret, id; 1990 1991 hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL); 1992 if (!hdptx) 1993 return -ENOMEM; 1994 1995 hdptx->dev = dev; 1996 hdptx->hdmi_cfg.bpc = 8; 1997 1998 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1999 if (IS_ERR(regs)) 2000 return dev_err_probe(dev, PTR_ERR(regs), 2001 "Failed to ioremap resource\n"); 2002 2003 cfgs = device_get_match_data(dev); 2004 if (!cfgs) 2005 return dev_err_probe(dev, -EINVAL, "missing match data\n"); 2006 2007 /* find the phy-id from the io address */ 2008 hdptx->phy_id = -ENODEV; 2009 for (id = 0; id < cfgs->num_phys; id++) { 2010 if (res->start == cfgs->phy_ids[id]) { 2011 hdptx->phy_id = id; 2012 break; 2013 } 2014 } 2015 2016 if (hdptx->phy_id < 0) 2017 return dev_err_probe(dev, -ENODEV, "no matching device found\n"); 2018 2019 ret = devm_clk_bulk_get_all(dev, &hdptx->clks); 2020 if (ret < 0) 2021 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 2022 if (ret == 0) 2023 return dev_err_probe(dev, -EINVAL, "Missing clocks\n"); 2024 2025 hdptx->nr_clks = ret; 2026 2027 hdptx->regmap = devm_regmap_init_mmio(dev, regs, 2028 &rk_hdptx_phy_regmap_config); 2029 if (IS_ERR(hdptx->regmap)) 2030 return dev_err_probe(dev, PTR_ERR(hdptx->regmap), 2031 "Failed to init regmap\n"); 2032 2033 hdptx->rsts[RST_APB].id = "apb"; 2034 hdptx->rsts[RST_INIT].id = "init"; 2035 hdptx->rsts[RST_CMN].id = "cmn"; 2036 hdptx->rsts[RST_LANE].id = "lane"; 2037 2038 ret = devm_reset_control_bulk_get_exclusive(dev, RST_MAX, hdptx->rsts); 2039 if (ret) 2040 return dev_err_probe(dev, ret, "Failed to get resets\n"); 2041 2042 hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 2043 "rockchip,grf"); 2044 if (IS_ERR(hdptx->grf)) 2045 return dev_err_probe(dev, PTR_ERR(hdptx->grf), 2046 "Could not get GRF syscon\n"); 2047 2048 platform_set_drvdata(pdev, hdptx); 2049 2050 ret = devm_pm_runtime_enable(dev); 2051 if (ret) 2052 return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); 2053 2054 hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops); 2055 if (IS_ERR(hdptx->phy)) 2056 return dev_err_probe(dev, PTR_ERR(hdptx->phy), 2057 "Failed to create HDMI PHY\n"); 2058 2059 phy_set_drvdata(hdptx->phy, hdptx); 2060 phy_set_bus_width(hdptx->phy, 8); 2061 2062 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2063 if (IS_ERR(phy_provider)) 2064 return dev_err_probe(dev, PTR_ERR(phy_provider), 2065 "Failed to register PHY provider\n"); 2066 2067 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 2068 reset_control_deassert(hdptx->rsts[RST_CMN].rstc); 2069 reset_control_deassert(hdptx->rsts[RST_INIT].rstc); 2070 2071 return rk_hdptx_phy_clk_register(hdptx); 2072 } 2073 2074 static const struct dev_pm_ops rk_hdptx_phy_pm_ops = { 2075 RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend, 2076 rk_hdptx_phy_runtime_resume, NULL) 2077 }; 2078 2079 static const struct rk_hdptx_phy_cfg rk3576_hdptx_phy_cfgs = { 2080 .num_phys = 1, 2081 .phy_ids = { 2082 0x2b000000, 2083 }, 2084 }; 2085 2086 static const struct rk_hdptx_phy_cfg rk3588_hdptx_phy_cfgs = { 2087 .num_phys = 2, 2088 .phy_ids = { 2089 0xfed60000, 2090 0xfed70000, 2091 }, 2092 }; 2093 2094 static const struct of_device_id rk_hdptx_phy_of_match[] = { 2095 { 2096 .compatible = "rockchip,rk3576-hdptx-phy", 2097 .data = &rk3576_hdptx_phy_cfgs 2098 }, 2099 { 2100 .compatible = "rockchip,rk3588-hdptx-phy", 2101 .data = &rk3588_hdptx_phy_cfgs 2102 }, 2103 {} 2104 }; 2105 MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match); 2106 2107 static struct platform_driver rk_hdptx_phy_driver = { 2108 .probe = rk_hdptx_phy_probe, 2109 .driver = { 2110 .name = "rockchip-hdptx-phy", 2111 .pm = &rk_hdptx_phy_pm_ops, 2112 .of_match_table = rk_hdptx_phy_of_match, 2113 }, 2114 }; 2115 module_platform_driver(rk_hdptx_phy_driver); 2116 2117 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>"); 2118 MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>"); 2119 MODULE_AUTHOR("Damon Ding <damon.ding@rock-chips.com>"); 2120 MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver"); 2121 MODULE_LICENSE("GPL"); 2122