1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip PCIe PHY driver 4 * 5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com> 6 * Copyright (C) 2016 ROCKCHIP, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/io.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 21 /* 22 * The higher 16-bit of this register is used for write protection 23 * only if BIT(x + 16) set to 1 the BIT(x) can be written. 24 */ 25 #define HIWORD_UPDATE(val, mask, shift) \ 26 ((val) << (shift) | (mask) << ((shift) + 16)) 27 28 #define PHY_MAX_LANE_NUM 4 29 #define PHY_CFG_DATA_SHIFT 7 30 #define PHY_CFG_ADDR_SHIFT 1 31 #define PHY_CFG_DATA_MASK 0xf 32 #define PHY_CFG_ADDR_MASK 0x3f 33 #define PHY_CFG_WR_ENABLE 1 34 #define PHY_CFG_WR_DISABLE 0 35 #define PHY_CFG_WR_SHIFT 0 36 #define PHY_CFG_WR_MASK 1 37 #define PHY_CFG_PLL_LOCK 0x10 38 #define PHY_CFG_CLK_TEST 0x10 39 #define PHY_CFG_CLK_SCC 0x12 40 #define PHY_CFG_SEPE_RATE BIT(3) 41 #define PHY_CFG_PLL_100M BIT(3) 42 #define PHY_PLL_LOCKED BIT(9) 43 #define PHY_PLL_OUTPUT BIT(10) 44 #define PHY_LANE_A_STATUS 0x30 45 #define PHY_LANE_B_STATUS 0x31 46 #define PHY_LANE_C_STATUS 0x32 47 #define PHY_LANE_D_STATUS 0x33 48 #define PHY_LANE_RX_DET_SHIFT 11 49 #define PHY_LANE_RX_DET_TH 0x1 50 #define PHY_LANE_IDLE_OFF 0x1 51 #define PHY_LANE_IDLE_MASK 0x1 52 #define PHY_LANE_IDLE_A_SHIFT 3 53 #define PHY_LANE_IDLE_B_SHIFT 4 54 #define PHY_LANE_IDLE_C_SHIFT 5 55 #define PHY_LANE_IDLE_D_SHIFT 6 56 57 struct rockchip_pcie_data { 58 unsigned int pcie_conf; 59 unsigned int pcie_status; 60 unsigned int pcie_laneoff; 61 }; 62 63 struct rockchip_pcie_phy { 64 const struct rockchip_pcie_data *phy_data; 65 struct regmap *reg_base; 66 struct phy_pcie_instance { 67 struct phy *phy; 68 u32 index; 69 } phys[PHY_MAX_LANE_NUM]; 70 struct mutex pcie_mutex; 71 struct reset_control *phy_rst; 72 struct clk *clk_pciephy_ref; 73 int pwr_cnt; 74 int init_cnt; 75 }; 76 77 static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst) 78 { 79 return container_of(inst, struct rockchip_pcie_phy, 80 phys[inst->index]); 81 } 82 83 static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev, 84 const struct of_phandle_args *args) 85 { 86 struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev); 87 88 if (args->args_count == 0) 89 return rk_phy->phys[0].phy; 90 91 if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM)) 92 return ERR_PTR(-ENODEV); 93 94 return rk_phy->phys[args->args[0]].phy; 95 } 96 97 98 static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy, 99 u32 addr, u32 data) 100 { 101 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, 102 HIWORD_UPDATE(data, 103 PHY_CFG_DATA_MASK, 104 PHY_CFG_DATA_SHIFT) | 105 HIWORD_UPDATE(addr, 106 PHY_CFG_ADDR_MASK, 107 PHY_CFG_ADDR_SHIFT)); 108 udelay(1); 109 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, 110 HIWORD_UPDATE(PHY_CFG_WR_ENABLE, 111 PHY_CFG_WR_MASK, 112 PHY_CFG_WR_SHIFT)); 113 udelay(1); 114 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, 115 HIWORD_UPDATE(PHY_CFG_WR_DISABLE, 116 PHY_CFG_WR_MASK, 117 PHY_CFG_WR_SHIFT)); 118 } 119 120 static int rockchip_pcie_phy_power_off(struct phy *phy) 121 { 122 struct phy_pcie_instance *inst = phy_get_drvdata(phy); 123 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst); 124 int err = 0; 125 126 guard(mutex)(&rk_phy->pcie_mutex); 127 128 regmap_write(rk_phy->reg_base, 129 rk_phy->phy_data->pcie_laneoff, 130 HIWORD_UPDATE(PHY_LANE_IDLE_OFF, 131 PHY_LANE_IDLE_MASK, 132 PHY_LANE_IDLE_A_SHIFT + inst->index)); 133 134 if (--rk_phy->pwr_cnt) { 135 return 0; 136 } 137 138 err = reset_control_assert(rk_phy->phy_rst); 139 if (err) { 140 dev_err(&phy->dev, "assert phy_rst err %d\n", err); 141 rk_phy->pwr_cnt++; 142 regmap_write(rk_phy->reg_base, 143 rk_phy->phy_data->pcie_laneoff, 144 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, 145 PHY_LANE_IDLE_MASK, 146 PHY_LANE_IDLE_A_SHIFT + inst->index)); 147 return err; 148 } 149 150 return err; 151 } 152 153 static int rockchip_pcie_phy_power_on(struct phy *phy) 154 { 155 struct phy_pcie_instance *inst = phy_get_drvdata(phy); 156 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst); 157 int err = 0; 158 u32 status; 159 160 guard(mutex)(&rk_phy->pcie_mutex); 161 162 regmap_write(rk_phy->reg_base, 163 rk_phy->phy_data->pcie_laneoff, 164 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, 165 PHY_LANE_IDLE_MASK, 166 PHY_LANE_IDLE_A_SHIFT + inst->index)); 167 168 if (rk_phy->pwr_cnt++) { 169 return 0; 170 } 171 172 err = reset_control_deassert(rk_phy->phy_rst); 173 if (err) { 174 dev_err(&phy->dev, "deassert phy_rst err %d\n", err); 175 rk_phy->pwr_cnt--; 176 return err; 177 } 178 179 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, 180 HIWORD_UPDATE(PHY_CFG_PLL_LOCK, 181 PHY_CFG_ADDR_MASK, 182 PHY_CFG_ADDR_SHIFT)); 183 184 /* 185 * No documented timeout value for phy operation below, 186 * so we make it large enough here. And we use loop-break 187 * method which should not be harmful. 188 */ 189 err = regmap_read_poll_timeout(rk_phy->reg_base, 190 rk_phy->phy_data->pcie_status, 191 status, 192 status & PHY_PLL_LOCKED, 193 200, 100000); 194 if (err) { 195 dev_err(&phy->dev, "pll lock timeout!\n"); 196 goto err_pll_lock; 197 } 198 199 phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE); 200 phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M); 201 202 err = regmap_read_poll_timeout(rk_phy->reg_base, 203 rk_phy->phy_data->pcie_status, 204 status, 205 !(status & PHY_PLL_OUTPUT), 206 200, 100000); 207 if (err) { 208 dev_err(&phy->dev, "pll output enable timeout!\n"); 209 goto err_pll_lock; 210 } 211 212 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, 213 HIWORD_UPDATE(PHY_CFG_PLL_LOCK, 214 PHY_CFG_ADDR_MASK, 215 PHY_CFG_ADDR_SHIFT)); 216 217 err = regmap_read_poll_timeout(rk_phy->reg_base, 218 rk_phy->phy_data->pcie_status, 219 status, 220 status & PHY_PLL_LOCKED, 221 200, 100000); 222 if (err) { 223 dev_err(&phy->dev, "pll relock timeout!\n"); 224 goto err_pll_lock; 225 } 226 227 return err; 228 229 err_pll_lock: 230 reset_control_assert(rk_phy->phy_rst); 231 rk_phy->pwr_cnt--; 232 return err; 233 } 234 235 static int rockchip_pcie_phy_init(struct phy *phy) 236 { 237 struct phy_pcie_instance *inst = phy_get_drvdata(phy); 238 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst); 239 int err = 0; 240 241 guard(mutex)(&rk_phy->pcie_mutex); 242 243 if (rk_phy->init_cnt++) { 244 return 0; 245 } 246 247 err = reset_control_assert(rk_phy->phy_rst); 248 if (err) { 249 dev_err(&phy->dev, "assert phy_rst err %d\n", err); 250 rk_phy->init_cnt--; 251 return err; 252 } 253 254 return err; 255 } 256 257 static int rockchip_pcie_phy_exit(struct phy *phy) 258 { 259 struct phy_pcie_instance *inst = phy_get_drvdata(phy); 260 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst); 261 262 guard(mutex)(&rk_phy->pcie_mutex); 263 264 if (--rk_phy->init_cnt) 265 goto err_init_cnt; 266 267 err_init_cnt: 268 return 0; 269 } 270 271 static const struct phy_ops ops = { 272 .init = rockchip_pcie_phy_init, 273 .exit = rockchip_pcie_phy_exit, 274 .power_on = rockchip_pcie_phy_power_on, 275 .power_off = rockchip_pcie_phy_power_off, 276 .owner = THIS_MODULE, 277 }; 278 279 static const struct rockchip_pcie_data rk3399_pcie_data = { 280 .pcie_conf = 0xe220, 281 .pcie_status = 0xe2a4, 282 .pcie_laneoff = 0xe214, 283 }; 284 285 static const struct of_device_id rockchip_pcie_phy_dt_ids[] = { 286 { 287 .compatible = "rockchip,rk3399-pcie-phy", 288 .data = &rk3399_pcie_data, 289 }, 290 {} 291 }; 292 293 MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids); 294 295 static int rockchip_pcie_phy_probe(struct platform_device *pdev) 296 { 297 struct device *dev = &pdev->dev; 298 struct rockchip_pcie_phy *rk_phy; 299 struct phy_provider *phy_provider; 300 struct regmap *grf; 301 int i; 302 u32 phy_num; 303 304 grf = syscon_node_to_regmap(dev->parent->of_node); 305 if (IS_ERR(grf)) { 306 dev_err(dev, "Cannot find GRF syscon\n"); 307 return PTR_ERR(grf); 308 } 309 310 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL); 311 if (!rk_phy) 312 return -ENOMEM; 313 314 rk_phy->phy_data = device_get_match_data(&pdev->dev); 315 if (!rk_phy->phy_data) 316 return -EINVAL; 317 318 rk_phy->reg_base = grf; 319 320 mutex_init(&rk_phy->pcie_mutex); 321 322 rk_phy->phy_rst = devm_reset_control_get(dev, "phy"); 323 if (IS_ERR(rk_phy->phy_rst)) 324 return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->phy_rst), 325 "missing phy property for reset controller\n"); 326 327 rk_phy->clk_pciephy_ref = devm_clk_get_enabled(dev, "refclk"); 328 if (IS_ERR(rk_phy->clk_pciephy_ref)) 329 return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->clk_pciephy_ref), 330 "failed to get phyclk\n"); 331 332 /* parse #phy-cells to see if it's legacy PHY model */ 333 if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num)) 334 return -ENOENT; 335 336 phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM; 337 dev_dbg(dev, "phy number is %d\n", phy_num); 338 339 for (i = 0; i < phy_num; i++) { 340 rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops); 341 if (IS_ERR(rk_phy->phys[i].phy)) { 342 dev_err(dev, "failed to create PHY%d\n", i); 343 return PTR_ERR(rk_phy->phys[i].phy); 344 } 345 rk_phy->phys[i].index = i; 346 phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]); 347 } 348 349 platform_set_drvdata(pdev, rk_phy); 350 phy_provider = devm_of_phy_provider_register(dev, 351 rockchip_pcie_phy_of_xlate); 352 353 return PTR_ERR_OR_ZERO(phy_provider); 354 } 355 356 static struct platform_driver rockchip_pcie_driver = { 357 .probe = rockchip_pcie_phy_probe, 358 .driver = { 359 .name = "rockchip-pcie-phy", 360 .of_match_table = rockchip_pcie_phy_dt_ids, 361 }, 362 }; 363 364 module_platform_driver(rockchip_pcie_driver); 365 366 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>"); 367 MODULE_DESCRIPTION("Rockchip PCIe PHY driver"); 368 MODULE_LICENSE("GPL v2"); 369