1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip PCIe PHY driver 4 * 5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com> 6 * Copyright (C) 2016 ROCKCHIP, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/hw_bitfield.h> 12 #include <linux/io.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 22 23 #define PHY_MAX_LANE_NUM 4 24 #define PHY_CFG_DATA_MASK GENMASK(10, 7) 25 #define PHY_CFG_ADDR_MASK GENMASK(6, 1) 26 #define PHY_CFG_WR_ENABLE 1 27 #define PHY_CFG_WR_DISABLE 0 28 #define PHY_CFG_WR_MASK BIT(0) 29 #define PHY_CFG_PLL_LOCK 0x10 30 #define PHY_CFG_CLK_TEST 0x10 31 #define PHY_CFG_CLK_SCC 0x12 32 #define PHY_CFG_SEPE_RATE BIT(3) 33 #define PHY_CFG_PLL_100M BIT(3) 34 #define PHY_PLL_LOCKED BIT(9) 35 #define PHY_PLL_OUTPUT BIT(10) 36 #define PHY_LANE_A_STATUS 0x30 37 #define PHY_LANE_B_STATUS 0x31 38 #define PHY_LANE_C_STATUS 0x32 39 #define PHY_LANE_D_STATUS 0x33 40 #define PHY_LANE_RX_DET_SHIFT 11 41 #define PHY_LANE_RX_DET_TH 0x1 42 #define PHY_LANE_IDLE_OFF 0x1 43 #define PHY_LANE_IDLE_MASK BIT(3) 44 45 struct rockchip_pcie_data { 46 unsigned int pcie_conf; 47 unsigned int pcie_status; 48 unsigned int pcie_laneoff; 49 }; 50 51 struct rockchip_pcie_phy { 52 const struct rockchip_pcie_data *phy_data; 53 struct regmap *reg_base; 54 struct phy_pcie_instance { 55 struct phy *phy; 56 u32 index; 57 } phys[PHY_MAX_LANE_NUM]; 58 struct mutex pcie_mutex; 59 struct reset_control *phy_rst; 60 struct clk *clk_pciephy_ref; 61 int pwr_cnt; 62 int init_cnt; 63 }; 64 65 static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst) 66 { 67 return container_of(inst, struct rockchip_pcie_phy, 68 phys[inst->index]); 69 } 70 71 static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev, 72 const struct of_phandle_args *args) 73 { 74 struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev); 75 76 if (args->args_count == 0) 77 return rk_phy->phys[0].phy; 78 79 if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM)) 80 return ERR_PTR(-ENODEV); 81 82 return rk_phy->phys[args->args[0]].phy; 83 } 84 85 86 static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy, 87 u32 addr, u32 data) 88 { 89 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, 90 FIELD_PREP_WM16(PHY_CFG_DATA_MASK, data) | 91 FIELD_PREP_WM16(PHY_CFG_ADDR_MASK, addr)); 92 udelay(1); 93 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, 94 FIELD_PREP_WM16(PHY_CFG_WR_MASK, PHY_CFG_WR_ENABLE)); 95 udelay(1); 96 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, 97 FIELD_PREP_WM16(PHY_CFG_WR_MASK, PHY_CFG_WR_DISABLE)); 98 } 99 100 static int rockchip_pcie_phy_power_off(struct phy *phy) 101 { 102 struct phy_pcie_instance *inst = phy_get_drvdata(phy); 103 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst); 104 int err = 0; 105 106 guard(mutex)(&rk_phy->pcie_mutex); 107 108 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_laneoff, 109 FIELD_PREP_WM16(PHY_LANE_IDLE_MASK, 110 PHY_LANE_IDLE_OFF) << inst->index); 111 112 if (--rk_phy->pwr_cnt) { 113 return 0; 114 } 115 116 err = reset_control_assert(rk_phy->phy_rst); 117 if (err) { 118 dev_err(&phy->dev, "assert phy_rst err %d\n", err); 119 rk_phy->pwr_cnt++; 120 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_laneoff, 121 FIELD_PREP_WM16(PHY_LANE_IDLE_MASK, 122 !PHY_LANE_IDLE_OFF) << inst->index); 123 return err; 124 } 125 126 return err; 127 } 128 129 static int rockchip_pcie_phy_power_on(struct phy *phy) 130 { 131 struct phy_pcie_instance *inst = phy_get_drvdata(phy); 132 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst); 133 int err = 0; 134 u32 status; 135 136 guard(mutex)(&rk_phy->pcie_mutex); 137 138 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_laneoff, 139 FIELD_PREP_WM16(PHY_LANE_IDLE_MASK, 140 !PHY_LANE_IDLE_OFF) << inst->index); 141 142 if (rk_phy->pwr_cnt++) { 143 return 0; 144 } 145 146 err = reset_control_deassert(rk_phy->phy_rst); 147 if (err) { 148 dev_err(&phy->dev, "deassert phy_rst err %d\n", err); 149 rk_phy->pwr_cnt--; 150 return err; 151 } 152 153 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, 154 FIELD_PREP_WM16(PHY_CFG_ADDR_MASK, PHY_CFG_PLL_LOCK)); 155 156 /* 157 * No documented timeout value for phy operation below, 158 * so we make it large enough here. And we use loop-break 159 * method which should not be harmful. 160 */ 161 err = regmap_read_poll_timeout(rk_phy->reg_base, 162 rk_phy->phy_data->pcie_status, 163 status, 164 status & PHY_PLL_LOCKED, 165 200, 100000); 166 if (err) { 167 dev_err(&phy->dev, "pll lock timeout!\n"); 168 goto err_pll_lock; 169 } 170 171 phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE); 172 phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M); 173 174 err = regmap_read_poll_timeout(rk_phy->reg_base, 175 rk_phy->phy_data->pcie_status, 176 status, 177 !(status & PHY_PLL_OUTPUT), 178 200, 100000); 179 if (err) { 180 dev_err(&phy->dev, "pll output enable timeout!\n"); 181 goto err_pll_lock; 182 } 183 184 regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, 185 FIELD_PREP_WM16(PHY_CFG_ADDR_MASK, PHY_CFG_PLL_LOCK)); 186 187 err = regmap_read_poll_timeout(rk_phy->reg_base, 188 rk_phy->phy_data->pcie_status, 189 status, 190 status & PHY_PLL_LOCKED, 191 200, 100000); 192 if (err) { 193 dev_err(&phy->dev, "pll relock timeout!\n"); 194 goto err_pll_lock; 195 } 196 197 return err; 198 199 err_pll_lock: 200 reset_control_assert(rk_phy->phy_rst); 201 rk_phy->pwr_cnt--; 202 return err; 203 } 204 205 static int rockchip_pcie_phy_init(struct phy *phy) 206 { 207 struct phy_pcie_instance *inst = phy_get_drvdata(phy); 208 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst); 209 int err = 0; 210 211 guard(mutex)(&rk_phy->pcie_mutex); 212 213 if (rk_phy->init_cnt++) { 214 return 0; 215 } 216 217 err = reset_control_assert(rk_phy->phy_rst); 218 if (err) { 219 dev_err(&phy->dev, "assert phy_rst err %d\n", err); 220 rk_phy->init_cnt--; 221 return err; 222 } 223 224 return err; 225 } 226 227 static int rockchip_pcie_phy_exit(struct phy *phy) 228 { 229 struct phy_pcie_instance *inst = phy_get_drvdata(phy); 230 struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst); 231 232 guard(mutex)(&rk_phy->pcie_mutex); 233 234 if (--rk_phy->init_cnt) 235 goto err_init_cnt; 236 237 err_init_cnt: 238 return 0; 239 } 240 241 static const struct phy_ops ops = { 242 .init = rockchip_pcie_phy_init, 243 .exit = rockchip_pcie_phy_exit, 244 .power_on = rockchip_pcie_phy_power_on, 245 .power_off = rockchip_pcie_phy_power_off, 246 .owner = THIS_MODULE, 247 }; 248 249 static const struct rockchip_pcie_data rk3399_pcie_data = { 250 .pcie_conf = 0xe220, 251 .pcie_status = 0xe2a4, 252 .pcie_laneoff = 0xe214, 253 }; 254 255 static const struct of_device_id rockchip_pcie_phy_dt_ids[] = { 256 { 257 .compatible = "rockchip,rk3399-pcie-phy", 258 .data = &rk3399_pcie_data, 259 }, 260 {} 261 }; 262 263 MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids); 264 265 static int rockchip_pcie_phy_probe(struct platform_device *pdev) 266 { 267 struct device *dev = &pdev->dev; 268 struct rockchip_pcie_phy *rk_phy; 269 struct phy_provider *phy_provider; 270 struct regmap *grf; 271 int i; 272 u32 phy_num; 273 274 grf = syscon_node_to_regmap(dev->parent->of_node); 275 if (IS_ERR(grf)) { 276 dev_err(dev, "Cannot find GRF syscon\n"); 277 return PTR_ERR(grf); 278 } 279 280 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL); 281 if (!rk_phy) 282 return -ENOMEM; 283 284 rk_phy->phy_data = device_get_match_data(&pdev->dev); 285 if (!rk_phy->phy_data) 286 return -EINVAL; 287 288 rk_phy->reg_base = grf; 289 290 mutex_init(&rk_phy->pcie_mutex); 291 292 rk_phy->phy_rst = devm_reset_control_get(dev, "phy"); 293 if (IS_ERR(rk_phy->phy_rst)) 294 return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->phy_rst), 295 "missing phy property for reset controller\n"); 296 297 rk_phy->clk_pciephy_ref = devm_clk_get_enabled(dev, "refclk"); 298 if (IS_ERR(rk_phy->clk_pciephy_ref)) 299 return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->clk_pciephy_ref), 300 "failed to get phyclk\n"); 301 302 /* parse #phy-cells to see if it's legacy PHY model */ 303 if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num)) 304 return -ENOENT; 305 306 phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM; 307 dev_dbg(dev, "phy number is %d\n", phy_num); 308 309 for (i = 0; i < phy_num; i++) { 310 rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops); 311 if (IS_ERR(rk_phy->phys[i].phy)) { 312 dev_err(dev, "failed to create PHY%d\n", i); 313 return PTR_ERR(rk_phy->phys[i].phy); 314 } 315 rk_phy->phys[i].index = i; 316 phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]); 317 } 318 319 platform_set_drvdata(pdev, rk_phy); 320 phy_provider = devm_of_phy_provider_register(dev, 321 rockchip_pcie_phy_of_xlate); 322 323 return PTR_ERR_OR_ZERO(phy_provider); 324 } 325 326 static struct platform_driver rockchip_pcie_driver = { 327 .probe = rockchip_pcie_phy_probe, 328 .driver = { 329 .name = "rockchip-pcie-phy", 330 .of_match_table = rockchip_pcie_phy_dt_ids, 331 }, 332 }; 333 334 module_platform_driver(rockchip_pcie_driver); 335 336 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>"); 337 MODULE_DESCRIPTION("Rockchip PCIe PHY driver"); 338 MODULE_LICENSE("GPL v2"); 339