1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <dt-bindings/phy/phy.h> 9 #include <linux/clk.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/of.h> 12 #include <linux/phy/phy.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/reset.h> 16 #include <linux/units.h> 17 18 #define BIT_WRITEABLE_SHIFT 16 19 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) 20 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) 21 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) 22 23 /* RK3528 COMBO PHY REG */ 24 #define RK3528_PHYREG6 0x18 25 #define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10) 26 #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2 27 #define RK3528_PHYREG6_SSC_DIR GENMASK(5, 4) 28 #define RK3528_PHYREG6_SSC_UPWARD 0 29 #define RK3528_PHYREG6_SSC_DOWNWARD 1 30 31 #define RK3528_PHYREG40 0x100 32 #define RK3528_PHYREG40_SSC_EN BIT(20) 33 #define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0) 34 #define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d 35 36 #define RK3528_PHYREG42 0x108 37 #define RK3528_PHYREG42_CKDRV_CLK_SEL BIT(29) 38 #define RK3528_PHYREG42_CKDRV_CLK_PLL 0 39 #define RK3528_PHYREG42_CKDRV_CLK_CKRCV 1 40 #define RK3528_PHYREG42_PLL_LPF_R1_ADJ GENMASK(10, 7) 41 #define RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE 0x9 42 #define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ GENMASK(6, 4) 43 #define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7 44 #define RK3528_PHYREG42_PLL_KVCO_ADJ GENMASK(2, 0) 45 #define RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE 0x0 46 47 #define RK3528_PHYREG80 0x200 48 #define RK3528_PHYREG80_CTLE_EN BIT(17) 49 50 #define RK3528_PHYREG81 0x204 51 #define RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X BIT(5) 52 #define RK3528_PHYREG81_SLEW_RATE_CTRL GENMASK(2, 0) 53 #define RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW 0x7 54 55 #define RK3528_PHYREG83 0x20c 56 #define RK3528_PHYREG83_RX_SQUELCH GENMASK(2, 0) 57 #define RK3528_PHYREG83_RX_SQUELCH_VALUE 0x6 58 59 #define RK3528_PHYREG86 0x218 60 #define RK3528_PHYREG86_RTERM_DET_CLK_EN BIT(14) 61 62 /* RK3568 COMBO PHY REG */ 63 #define RK3568_PHYREG6 0x14 64 #define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6) 65 #define RK3568_PHYREG6_PLL_DIV_SHIFT 6 66 #define RK3568_PHYREG6_PLL_DIV_2 1 67 68 #define RK3568_PHYREG7 0x18 69 #define RK3568_PHYREG7_TX_RTERM_MASK GENMASK(7, 4) 70 #define RK3568_PHYREG7_TX_RTERM_SHIFT 4 71 #define RK3568_PHYREG7_TX_RTERM_50OHM 8 72 #define RK3568_PHYREG7_RX_RTERM_MASK GENMASK(3, 0) 73 #define RK3568_PHYREG7_RX_RTERM_SHIFT 0 74 #define RK3568_PHYREG7_RX_RTERM_44OHM 15 75 76 #define RK3568_PHYREG8 0x1C 77 #define RK3568_PHYREG8_SSC_EN BIT(4) 78 79 #define RK3568_PHYREG11 0x28 80 #define RK3568_PHYREG11_SU_TRIM_0_7 0xF0 81 82 #define RK3568_PHYREG12 0x2C 83 #define RK3568_PHYREG12_PLL_LPF_ADJ_VALUE 4 84 85 #define RK3568_PHYREG13 0x30 86 #define RK3568_PHYREG13_RESISTER_MASK GENMASK(5, 4) 87 #define RK3568_PHYREG13_RESISTER_SHIFT 0x4 88 #define RK3568_PHYREG13_RESISTER_HIGH_Z 3 89 #define RK3568_PHYREG13_CKRCV_AMP0 BIT(7) 90 91 #define RK3568_PHYREG14 0x34 92 #define RK3568_PHYREG14_CKRCV_AMP1 BIT(0) 93 94 #define RK3568_PHYREG15 0x38 95 #define RK3568_PHYREG15_CTLE_EN BIT(0) 96 #define RK3568_PHYREG15_SSC_CNT_MASK GENMASK(7, 6) 97 #define RK3568_PHYREG15_SSC_CNT_SHIFT 6 98 #define RK3568_PHYREG15_SSC_CNT_VALUE 1 99 100 #define RK3568_PHYREG16 0x3C 101 #define RK3568_PHYREG16_SSC_CNT_VALUE 0x5f 102 103 #define RK3568_PHYREG18 0x44 104 #define RK3568_PHYREG18_PLL_LOOP 0x32 105 106 #define RK3568_PHYREG32 0x7C 107 #define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4) 108 #define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4) 109 #define RK3568_PHYREG32_SSC_DIR_SHIFT 4 110 #define RK3568_PHYREG32_SSC_UPWARD 0 111 #define RK3568_PHYREG32_SSC_DOWNWARD 1 112 #define RK3568_PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6) 113 #define RK3568_PHYREG32_SSC_OFFSET_SHIFT 6 114 #define RK3568_PHYREG32_SSC_OFFSET_500PPM 1 115 116 #define RK3568_PHYREG33 0x80 117 #define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) 118 #define RK3568_PHYREG33_PLL_KVCO_SHIFT 2 119 #define RK3568_PHYREG33_PLL_KVCO_VALUE 2 120 #define RK3576_PHYREG33_PLL_KVCO_VALUE 4 121 122 /* RK3588 COMBO PHY registers */ 123 #define RK3588_PHYREG27 0x6C 124 #define RK3588_PHYREG27_RX_TRIM 0x4C 125 126 /* RK3576 COMBO PHY registers */ 127 #define RK3576_PHYREG10 0x24 128 #define RK3576_PHYREG10_SSC_PCM_MASK GENMASK(3, 0) 129 #define RK3576_PHYREG10_SSC_PCM_3500PPM 7 130 131 #define RK3576_PHYREG17 0x40 132 133 #define RK3576_PHYREG21 0x50 134 #define RK3576_PHYREG21_RX_SQUELCH_VAL 0x0D 135 136 #define RK3576_PHYREG30 0x74 137 138 struct rockchip_combphy_priv; 139 140 struct combphy_reg { 141 u16 offset; 142 u16 bitend; 143 u16 bitstart; 144 u16 disable; 145 u16 enable; 146 }; 147 148 struct rockchip_combphy_grfcfg { 149 struct combphy_reg pcie_mode_set; 150 struct combphy_reg usb_mode_set; 151 struct combphy_reg sgmii_mode_set; 152 struct combphy_reg qsgmii_mode_set; 153 struct combphy_reg pipe_rxterm_set; 154 struct combphy_reg pipe_txelec_set; 155 struct combphy_reg pipe_txcomp_set; 156 struct combphy_reg pipe_clk_24m; 157 struct combphy_reg pipe_clk_25m; 158 struct combphy_reg pipe_clk_100m; 159 struct combphy_reg pipe_phymode_sel; 160 struct combphy_reg pipe_rate_sel; 161 struct combphy_reg pipe_rxterm_sel; 162 struct combphy_reg pipe_txelec_sel; 163 struct combphy_reg pipe_txcomp_sel; 164 struct combphy_reg pipe_clk_ext; 165 struct combphy_reg pipe_sel_usb; 166 struct combphy_reg pipe_sel_qsgmii; 167 struct combphy_reg pipe_phy_status; 168 struct combphy_reg con0_for_pcie; 169 struct combphy_reg con1_for_pcie; 170 struct combphy_reg con2_for_pcie; 171 struct combphy_reg con3_for_pcie; 172 struct combphy_reg con0_for_sata; 173 struct combphy_reg con1_for_sata; 174 struct combphy_reg con2_for_sata; 175 struct combphy_reg con3_for_sata; 176 struct combphy_reg pipe_con0_for_sata; 177 struct combphy_reg pipe_con1_for_sata; 178 struct combphy_reg pipe_xpcs_phy_ready; 179 struct combphy_reg pipe_pcie1l0_sel; 180 struct combphy_reg pipe_pcie1l1_sel; 181 struct combphy_reg u3otg0_port_en; 182 struct combphy_reg u3otg1_port_en; 183 }; 184 185 struct rockchip_combphy_cfg { 186 unsigned int num_phys; 187 unsigned int phy_ids[3]; 188 const struct rockchip_combphy_grfcfg *grfcfg; 189 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 190 }; 191 192 struct rockchip_combphy_priv { 193 u8 type; 194 int id; 195 void __iomem *mmio; 196 int num_clks; 197 struct clk_bulk_data *clks; 198 struct device *dev; 199 struct regmap *pipe_grf; 200 struct regmap *phy_grf; 201 struct phy *phy; 202 struct reset_control *phy_rst; 203 const struct rockchip_combphy_cfg *cfg; 204 bool enable_ssc; 205 bool ext_refclk; 206 struct clk *refclk; 207 }; 208 209 static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, 210 int mask, int val, int reg) 211 { 212 unsigned int temp; 213 214 temp = readl(priv->mmio + reg); 215 temp = (temp & ~(mask)) | val; 216 writel(temp, priv->mmio + reg); 217 } 218 219 static int rockchip_combphy_param_write(struct regmap *base, 220 const struct combphy_reg *reg, bool en) 221 { 222 u32 val, mask, tmp; 223 224 tmp = en ? reg->enable : reg->disable; 225 mask = GENMASK(reg->bitend, reg->bitstart); 226 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 227 228 return regmap_write(base, reg->offset, val); 229 } 230 231 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 232 { 233 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 234 u32 mask, val; 235 236 mask = GENMASK(cfg->pipe_phy_status.bitend, 237 cfg->pipe_phy_status.bitstart); 238 239 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 240 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 241 242 return val; 243 } 244 245 static int rockchip_combphy_init(struct phy *phy) 246 { 247 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); 248 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 249 u32 val; 250 int ret; 251 252 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); 253 if (ret) { 254 dev_err(priv->dev, "failed to enable clks\n"); 255 return ret; 256 } 257 258 switch (priv->type) { 259 case PHY_TYPE_PCIE: 260 case PHY_TYPE_USB3: 261 case PHY_TYPE_SATA: 262 case PHY_TYPE_SGMII: 263 case PHY_TYPE_QSGMII: 264 if (priv->cfg->combphy_cfg) 265 ret = priv->cfg->combphy_cfg(priv); 266 break; 267 default: 268 dev_err(priv->dev, "incompatible PHY type\n"); 269 ret = -EINVAL; 270 break; 271 } 272 273 if (ret) { 274 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); 275 goto err_clk; 276 } 277 278 ret = reset_control_deassert(priv->phy_rst); 279 if (ret) 280 goto err_clk; 281 282 if (priv->type == PHY_TYPE_USB3) { 283 ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, 284 priv, val, 285 val == cfg->pipe_phy_status.enable, 286 10, 1000); 287 if (ret) 288 dev_warn(priv->dev, "wait phy status ready timeout\n"); 289 } 290 291 return 0; 292 293 err_clk: 294 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); 295 296 return ret; 297 } 298 299 static int rockchip_combphy_exit(struct phy *phy) 300 { 301 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); 302 303 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); 304 reset_control_assert(priv->phy_rst); 305 306 return 0; 307 } 308 309 static const struct phy_ops rockchip_combphy_ops = { 310 .init = rockchip_combphy_init, 311 .exit = rockchip_combphy_exit, 312 .owner = THIS_MODULE, 313 }; 314 315 static struct phy *rockchip_combphy_xlate(struct device *dev, const struct of_phandle_args *args) 316 { 317 struct rockchip_combphy_priv *priv = dev_get_drvdata(dev); 318 319 if (args->args_count != 1) { 320 dev_err(dev, "invalid number of arguments\n"); 321 return ERR_PTR(-EINVAL); 322 } 323 324 if (priv->type != PHY_NONE && priv->type != args->args[0]) 325 dev_warn(dev, "phy type select %d overwriting type %d\n", 326 args->args[0], priv->type); 327 328 priv->type = args->args[0]; 329 330 return priv->phy; 331 } 332 333 static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) 334 { 335 int i; 336 337 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); 338 if (priv->num_clks < 1) 339 return -EINVAL; 340 341 priv->refclk = NULL; 342 for (i = 0; i < priv->num_clks; i++) { 343 if (!strncmp(priv->clks[i].id, "ref", 3)) { 344 priv->refclk = priv->clks[i].clk; 345 break; 346 } 347 } 348 349 if (!priv->refclk) { 350 dev_err(dev, "no refclk found\n"); 351 return -EINVAL; 352 } 353 354 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); 355 if (IS_ERR(priv->pipe_grf)) { 356 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); 357 return PTR_ERR(priv->pipe_grf); 358 } 359 360 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); 361 if (IS_ERR(priv->phy_grf)) { 362 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 363 return PTR_ERR(priv->phy_grf); 364 } 365 366 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); 367 368 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); 369 370 priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy"); 371 /* fallback to old behaviour */ 372 if (PTR_ERR(priv->phy_rst) == -ENOENT) 373 priv->phy_rst = devm_reset_control_array_get_exclusive(dev); 374 if (IS_ERR(priv->phy_rst)) 375 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); 376 377 return 0; 378 } 379 380 static int rockchip_combphy_probe(struct platform_device *pdev) 381 { 382 struct phy_provider *phy_provider; 383 struct device *dev = &pdev->dev; 384 struct rockchip_combphy_priv *priv; 385 const struct rockchip_combphy_cfg *phy_cfg; 386 struct resource *res; 387 int ret, id; 388 389 phy_cfg = of_device_get_match_data(dev); 390 if (!phy_cfg) { 391 dev_err(dev, "no OF match data provided\n"); 392 return -EINVAL; 393 } 394 395 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 396 if (!priv) 397 return -ENOMEM; 398 399 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 400 if (IS_ERR(priv->mmio)) { 401 ret = PTR_ERR(priv->mmio); 402 return ret; 403 } 404 405 /* find the phy-id from the io address */ 406 priv->id = -ENODEV; 407 for (id = 0; id < phy_cfg->num_phys; id++) { 408 if (res->start == phy_cfg->phy_ids[id]) { 409 priv->id = id; 410 break; 411 } 412 } 413 414 priv->dev = dev; 415 priv->type = PHY_NONE; 416 priv->cfg = phy_cfg; 417 418 ret = rockchip_combphy_parse_dt(dev, priv); 419 if (ret) 420 return ret; 421 422 ret = reset_control_assert(priv->phy_rst); 423 if (ret) { 424 dev_err(dev, "failed to reset phy\n"); 425 return ret; 426 } 427 428 priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops); 429 if (IS_ERR(priv->phy)) { 430 dev_err(dev, "failed to create combphy\n"); 431 return PTR_ERR(priv->phy); 432 } 433 434 dev_set_drvdata(dev, priv); 435 phy_set_drvdata(priv->phy, priv); 436 437 phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate); 438 439 return PTR_ERR_OR_ZERO(phy_provider); 440 } 441 442 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 443 { 444 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 445 unsigned long rate; 446 u32 val; 447 448 /* Set SSC downward spread spectrum */ 449 val = FIELD_PREP(RK3528_PHYREG6_SSC_DIR, RK3528_PHYREG6_SSC_DOWNWARD); 450 rockchip_combphy_updatel(priv, RK3528_PHYREG6_SSC_DIR, val, RK3528_PHYREG6); 451 452 switch (priv->type) { 453 case PHY_TYPE_PCIE: 454 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 455 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 456 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 457 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 458 break; 459 case PHY_TYPE_USB3: 460 /* Enable adaptive CTLE for USB3.0 Rx */ 461 rockchip_combphy_updatel(priv, RK3528_PHYREG80_CTLE_EN, RK3528_PHYREG80_CTLE_EN, 462 RK3528_PHYREG80); 463 464 /* Set slow slew rate control for PI */ 465 val = FIELD_PREP(RK3528_PHYREG81_SLEW_RATE_CTRL, 466 RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW); 467 rockchip_combphy_updatel(priv, RK3528_PHYREG81_SLEW_RATE_CTRL, val, 468 RK3528_PHYREG81); 469 470 /* Set CDR phase path with 2x gain */ 471 rockchip_combphy_updatel(priv, RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, 472 RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, RK3528_PHYREG81); 473 474 /* Set Rx squelch input filler bandwidth */ 475 val = FIELD_PREP(RK3528_PHYREG83_RX_SQUELCH, RK3528_PHYREG83_RX_SQUELCH_VALUE); 476 rockchip_combphy_updatel(priv, RK3528_PHYREG83_RX_SQUELCH, val, RK3528_PHYREG83); 477 478 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 479 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 480 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 481 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); 482 break; 483 default: 484 dev_err(priv->dev, "incompatible PHY type\n"); 485 return -EINVAL; 486 } 487 488 rate = clk_get_rate(priv->refclk); 489 490 switch (rate) { 491 case REF_CLOCK_24MHz: 492 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); 493 if (priv->type == PHY_TYPE_USB3) { 494 /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */ 495 val = FIELD_PREP(RK3528_PHYREG40_SSC_CNT, RK3528_PHYREG40_SSC_CNT_VALUE); 496 rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_CNT, val, 497 RK3528_PHYREG40); 498 } else if (priv->type == PHY_TYPE_PCIE) { 499 /* tx_trim[14]=1, Enable the counting clock of the rterm detect */ 500 rockchip_combphy_updatel(priv, RK3528_PHYREG86_RTERM_DET_CLK_EN, 501 RK3528_PHYREG86_RTERM_DET_CLK_EN, RK3528_PHYREG86); 502 } 503 break; 504 case REF_CLOCK_100MHz: 505 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 506 if (priv->type == PHY_TYPE_PCIE) { 507 /* PLL KVCO tuning fine */ 508 val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE); 509 rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val, 510 RK3528_PHYREG6); 511 512 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */ 513 writel(0x570804f0, priv->mmio + RK3528_PHYREG42); 514 } 515 break; 516 default: 517 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); 518 return -EINVAL; 519 } 520 521 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { 522 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 523 524 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 525 val = FIELD_PREP(RK3528_PHYREG42_CKDRV_CLK_SEL, 526 RK3528_PHYREG42_CKDRV_CLK_CKRCV); 527 val |= FIELD_PREP(RK3528_PHYREG42_PLL_LPF_R1_ADJ, 528 RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE); 529 val |= FIELD_PREP(RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ, 530 RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE); 531 val |= FIELD_PREP(RK3528_PHYREG42_PLL_KVCO_ADJ, 532 RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE); 533 rockchip_combphy_updatel(priv, 534 RK3528_PHYREG42_CKDRV_CLK_SEL | 535 RK3528_PHYREG42_PLL_LPF_R1_ADJ | 536 RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ | 537 RK3528_PHYREG42_PLL_KVCO_ADJ, 538 val, RK3528_PHYREG42); 539 540 val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE); 541 rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val, 542 RK3528_PHYREG6); 543 } 544 } 545 546 if (priv->type == PHY_TYPE_PCIE) { 547 if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) 548 rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN, 549 RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40); 550 } 551 552 return 0; 553 } 554 555 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 556 /* pipe-phy-grf */ 557 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 558 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 559 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 560 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 561 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 562 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, 563 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 564 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 565 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 566 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 567 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 568 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 569 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 }, 570 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 }, 571 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 }, 572 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 573 /* pipe-grf */ 574 .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 }, 575 }; 576 577 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 578 .num_phys = 1, 579 .phy_ids = { 580 0xffdc0000, 581 }, 582 .grfcfg = &rk3528_combphy_grfcfgs, 583 .combphy_cfg = rk3528_combphy_cfg, 584 }; 585 586 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 587 { 588 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 589 unsigned long rate; 590 u32 val; 591 592 switch (priv->type) { 593 case PHY_TYPE_PCIE: 594 /* Set SSC downward spread spectrum */ 595 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 596 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 597 598 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 599 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 600 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 601 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 602 break; 603 case PHY_TYPE_USB3: 604 /* Set SSC downward spread spectrum */ 605 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 606 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, 607 RK3568_PHYREG32); 608 609 /* Enable adaptive CTLE for USB3.0 Rx */ 610 rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN, 611 RK3568_PHYREG15_CTLE_EN, RK3568_PHYREG15); 612 613 /* Set PLL KVCO fine tuning signals */ 614 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 615 BIT(3), RK3568_PHYREG33); 616 617 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 618 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 619 620 /* Set PLL input clock divider 1/2 */ 621 val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2); 622 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6); 623 624 /* Set PLL loop divider */ 625 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 626 627 /* Set PLL KVCO to min and set PLL charge pump current to max */ 628 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 629 630 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 631 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 632 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 633 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 634 break; 635 default: 636 dev_err(priv->dev, "incompatible PHY type\n"); 637 return -EINVAL; 638 } 639 640 rate = clk_get_rate(priv->refclk); 641 642 switch (rate) { 643 case REF_CLOCK_24MHz: 644 if (priv->type == PHY_TYPE_USB3) { 645 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ 646 val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK, 647 RK3568_PHYREG15_SSC_CNT_VALUE); 648 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, 649 val, RK3568_PHYREG15); 650 651 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 652 } 653 break; 654 case REF_CLOCK_25MHz: 655 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 656 break; 657 case REF_CLOCK_100MHz: 658 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 659 if (priv->type == PHY_TYPE_PCIE) { 660 /* PLL KVCO tuning fine */ 661 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, 662 RK3568_PHYREG33_PLL_KVCO_VALUE); 663 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 664 val, RK3568_PHYREG33); 665 666 /* Enable controlling random jitter, aka RMJ */ 667 writel(0x4, priv->mmio + RK3568_PHYREG12); 668 669 val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT; 670 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, 671 val, RK3568_PHYREG6); 672 673 writel(0x32, priv->mmio + RK3568_PHYREG18); 674 writel(0xf0, priv->mmio + RK3568_PHYREG11); 675 } 676 break; 677 default: 678 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); 679 return -EINVAL; 680 } 681 682 if (priv->ext_refclk) { 683 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 684 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 685 val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT; 686 val |= RK3568_PHYREG13_CKRCV_AMP0; 687 rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, 688 RK3568_PHYREG13); 689 690 val = readl(priv->mmio + RK3568_PHYREG14); 691 val |= RK3568_PHYREG14_CKRCV_AMP1; 692 writel(val, priv->mmio + RK3568_PHYREG14); 693 } 694 } 695 696 if (priv->enable_ssc) { 697 val = readl(priv->mmio + RK3568_PHYREG8); 698 val |= RK3568_PHYREG8_SSC_EN; 699 writel(val, priv->mmio + RK3568_PHYREG8); 700 } 701 702 return 0; 703 } 704 705 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 706 /* pipe-phy-grf */ 707 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 708 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 709 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 710 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 711 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 712 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 713 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 714 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 715 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 716 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 717 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 718 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 719 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 720 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 721 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 722 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 723 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 724 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 725 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 726 }; 727 728 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 729 .num_phys = 1, 730 .phy_ids = { 731 0xff750000 732 }, 733 .grfcfg = &rk3562_combphy_grfcfgs, 734 .combphy_cfg = rk3562_combphy_cfg, 735 }; 736 737 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 738 { 739 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 740 unsigned long rate; 741 u32 val; 742 743 switch (priv->type) { 744 case PHY_TYPE_PCIE: 745 /* Set SSC downward spread spectrum. */ 746 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 747 748 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 749 750 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 751 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 752 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 753 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 754 break; 755 756 case PHY_TYPE_USB3: 757 /* Set SSC downward spread spectrum. */ 758 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT, 759 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 760 761 /* Enable adaptive CTLE for USB3.0 Rx. */ 762 val = readl(priv->mmio + RK3568_PHYREG15); 763 val |= RK3568_PHYREG15_CTLE_EN; 764 writel(val, priv->mmio + RK3568_PHYREG15); 765 766 /* Set PLL KVCO fine tuning signals. */ 767 val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT; 768 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33); 769 770 /* Enable controlling random jitter. */ 771 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 772 773 /* Set PLL input clock divider 1/2. */ 774 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, 775 RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT, 776 RK3568_PHYREG6); 777 778 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 779 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 780 781 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 782 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 783 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 784 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 785 switch (priv->id) { 786 case 0: 787 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); 788 break; 789 case 1: 790 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true); 791 break; 792 } 793 break; 794 795 case PHY_TYPE_SATA: 796 /* Enable adaptive CTLE for SATA Rx. */ 797 val = readl(priv->mmio + RK3568_PHYREG15); 798 val |= RK3568_PHYREG15_CTLE_EN; 799 writel(val, priv->mmio + RK3568_PHYREG15); 800 /* 801 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. 802 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) 803 */ 804 val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; 805 val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; 806 writel(val, priv->mmio + RK3568_PHYREG7); 807 808 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); 809 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); 810 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); 811 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); 812 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 813 break; 814 815 case PHY_TYPE_SGMII: 816 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 817 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 818 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 819 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 820 break; 821 822 case PHY_TYPE_QSGMII: 823 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 824 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 825 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 826 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 827 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 828 break; 829 830 default: 831 dev_err(priv->dev, "incompatible PHY type\n"); 832 return -EINVAL; 833 } 834 835 rate = clk_get_rate(priv->refclk); 836 837 switch (rate) { 838 case REF_CLOCK_24MHz: 839 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { 840 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ 841 val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT; 842 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, 843 val, RK3568_PHYREG15); 844 845 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 846 } 847 break; 848 849 case REF_CLOCK_25MHz: 850 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 851 break; 852 853 case REF_CLOCK_100MHz: 854 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 855 if (priv->type == PHY_TYPE_PCIE) { 856 /* PLL KVCO fine tuning. */ 857 val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT; 858 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 859 val, RK3568_PHYREG33); 860 861 /* Enable controlling random jitter. */ 862 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 863 864 val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT; 865 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, 866 val, RK3568_PHYREG6); 867 868 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 869 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 870 } else if (priv->type == PHY_TYPE_SATA) { 871 /* downward spread spectrum +500ppm */ 872 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 873 val |= RK3568_PHYREG32_SSC_OFFSET_500PPM << 874 RK3568_PHYREG32_SSC_OFFSET_SHIFT; 875 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, 876 RK3568_PHYREG32); 877 } 878 break; 879 880 default: 881 dev_err(priv->dev, "unsupported rate: %lu\n", rate); 882 return -EINVAL; 883 } 884 885 if (priv->ext_refclk) { 886 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 887 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 888 val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT; 889 val |= RK3568_PHYREG13_CKRCV_AMP0; 890 rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, 891 RK3568_PHYREG13); 892 893 val = readl(priv->mmio + RK3568_PHYREG14); 894 val |= RK3568_PHYREG14_CKRCV_AMP1; 895 writel(val, priv->mmio + RK3568_PHYREG14); 896 } 897 } 898 899 if (priv->enable_ssc) { 900 val = readl(priv->mmio + RK3568_PHYREG8); 901 val |= RK3568_PHYREG8_SSC_EN; 902 writel(val, priv->mmio + RK3568_PHYREG8); 903 } 904 905 return 0; 906 } 907 908 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 909 /* pipe-phy-grf */ 910 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 911 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 912 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 913 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 914 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 915 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 916 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 917 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 918 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 919 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 920 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 921 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 922 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 923 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 924 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 925 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 926 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 927 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 928 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 929 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 930 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 931 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 932 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 933 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 934 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 935 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 936 /* pipe-grf */ 937 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 938 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 939 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 940 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 941 }; 942 943 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 944 .num_phys = 3, 945 .phy_ids = { 946 0xfe820000, 947 0xfe830000, 948 0xfe840000, 949 }, 950 .grfcfg = &rk3568_combphy_grfcfgs, 951 .combphy_cfg = rk3568_combphy_cfg, 952 }; 953 954 static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) 955 { 956 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 957 unsigned long rate; 958 u32 val; 959 960 switch (priv->type) { 961 case PHY_TYPE_PCIE: 962 /* Set SSC downward spread spectrum */ 963 val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD); 964 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 965 966 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 967 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 968 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 969 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 970 break; 971 972 case PHY_TYPE_USB3: 973 /* Set SSC downward spread spectrum */ 974 val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD); 975 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 976 977 /* Enable adaptive CTLE for USB3.0 Rx */ 978 val = readl(priv->mmio + RK3568_PHYREG15); 979 val |= RK3568_PHYREG15_CTLE_EN; 980 writel(val, priv->mmio + RK3568_PHYREG15); 981 982 /* Set PLL KVCO fine tuning signals */ 983 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, BIT(3), 984 RK3568_PHYREG33); 985 986 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 987 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 988 989 /* Set PLL input clock divider 1/2 */ 990 val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2); 991 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6); 992 993 /* Set PLL loop divider */ 994 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 995 996 /* Set PLL KVCO to min and set PLL charge pump current to max */ 997 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 998 999 /* Set Rx squelch input filler bandwidth */ 1000 writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21); 1001 1002 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 1003 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 1004 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 1005 break; 1006 1007 case PHY_TYPE_SATA: 1008 /* Enable adaptive CTLE for SATA Rx */ 1009 val = readl(priv->mmio + RK3568_PHYREG15); 1010 val |= RK3568_PHYREG15_CTLE_EN; 1011 writel(val, priv->mmio + RK3568_PHYREG15); 1012 1013 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 1014 val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; 1015 val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; 1016 writel(val, priv->mmio + RK3568_PHYREG7); 1017 1018 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); 1019 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); 1020 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); 1021 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); 1022 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 1023 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 1024 break; 1025 1026 default: 1027 dev_err(priv->dev, "incompatible PHY type\n"); 1028 return -EINVAL; 1029 } 1030 1031 rate = clk_get_rate(priv->refclk); 1032 1033 switch (rate) { 1034 case REF_CLOCK_24MHz: 1035 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); 1036 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { 1037 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ 1038 val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK, 1039 RK3568_PHYREG15_SSC_CNT_VALUE); 1040 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, 1041 val, RK3568_PHYREG15); 1042 1043 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 1044 } else if (priv->type == PHY_TYPE_PCIE) { 1045 /* PLL KVCO tuning fine */ 1046 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, 1047 RK3576_PHYREG33_PLL_KVCO_VALUE); 1048 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 1049 val, RK3568_PHYREG33); 1050 1051 /* Set up rx_pck invert and rx msb to disable */ 1052 writel(0x00, priv->mmio + RK3588_PHYREG27); 1053 1054 /* 1055 * Set up SU adjust signal: 1056 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min 1057 * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b011 1058 * su_trim[31:24], CKDRV adjust 1059 */ 1060 writel(0x90, priv->mmio + RK3568_PHYREG11); 1061 writel(0x02, priv->mmio + RK3568_PHYREG12); 1062 writel(0x57, priv->mmio + RK3568_PHYREG14); 1063 1064 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 1065 } 1066 break; 1067 1068 case REF_CLOCK_25MHz: 1069 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 1070 break; 1071 1072 case REF_CLOCK_100MHz: 1073 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 1074 if (priv->type == PHY_TYPE_PCIE) { 1075 /* gate_tx_pck_sel length select work for L1SS */ 1076 writel(0xc0, priv->mmio + RK3576_PHYREG30); 1077 1078 /* PLL KVCO tuning fine */ 1079 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, 1080 RK3576_PHYREG33_PLL_KVCO_VALUE); 1081 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 1082 val, RK3568_PHYREG33); 1083 1084 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 1085 writel(0x4c, priv->mmio + RK3588_PHYREG27); 1086 1087 /* 1088 * Set up SU adjust signal: 1089 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min 1090 * su_trim[15:8], bypass PLL loop divider code, and 1091 * PLL LPF R1 adujst bits[9:7]=3'b101 1092 * su_trim[23:16], CKRCV adjust 1093 * su_trim[31:24], CKDRV adjust 1094 */ 1095 writel(0x90, priv->mmio + RK3568_PHYREG11); 1096 writel(0x43, priv->mmio + RK3568_PHYREG12); 1097 writel(0x88, priv->mmio + RK3568_PHYREG13); 1098 writel(0x56, priv->mmio + RK3568_PHYREG14); 1099 } else if (priv->type == PHY_TYPE_SATA) { 1100 /* downward spread spectrum +500ppm */ 1101 val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK, 1102 RK3568_PHYREG32_SSC_DOWNWARD); 1103 val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK, 1104 RK3568_PHYREG32_SSC_OFFSET_500PPM); 1105 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, 1106 RK3568_PHYREG32); 1107 1108 /* ssc ppm adjust to 3500ppm */ 1109 rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK, 1110 RK3576_PHYREG10_SSC_PCM_3500PPM, 1111 RK3576_PHYREG10); 1112 } 1113 break; 1114 1115 default: 1116 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); 1117 return -EINVAL; 1118 } 1119 1120 if (priv->ext_refclk) { 1121 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 1122 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 1123 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, 1124 RK3576_PHYREG33_PLL_KVCO_VALUE); 1125 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 1126 val, RK3568_PHYREG33); 1127 1128 /* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */ 1129 writel(0x0c, priv->mmio + RK3588_PHYREG27); 1130 1131 /* 1132 * Set up SU adjust signal: 1133 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min 1134 * su_trim[15:8], bypass PLL loop divider code, and 1135 * PLL LPF R1 adujst bits[9:7]=3'b101. 1136 * su_trim[23:16], CKRCV adjust 1137 * su_trim[31:24], CKDRV adjust 1138 */ 1139 writel(0x90, priv->mmio + RK3568_PHYREG11); 1140 writel(0x43, priv->mmio + RK3568_PHYREG12); 1141 writel(0x88, priv->mmio + RK3568_PHYREG13); 1142 writel(0x56, priv->mmio + RK3568_PHYREG14); 1143 } 1144 } 1145 1146 if (priv->enable_ssc) { 1147 val = readl(priv->mmio + RK3568_PHYREG8); 1148 val |= RK3568_PHYREG8_SSC_EN; 1149 writel(val, priv->mmio + RK3568_PHYREG8); 1150 1151 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { 1152 /* Set PLL loop divider */ 1153 writel(0x00, priv->mmio + RK3576_PHYREG17); 1154 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 1155 1156 /* Set up rx_pck invert and rx msb to disable */ 1157 writel(0x00, priv->mmio + RK3588_PHYREG27); 1158 1159 /* 1160 * Set up SU adjust signal: 1161 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min 1162 * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101 1163 * su_trim[23:16], CKRCV adjust 1164 * su_trim[31:24], CKDRV adjust 1165 */ 1166 writel(0x90, priv->mmio + RK3568_PHYREG11); 1167 writel(0x02, priv->mmio + RK3568_PHYREG12); 1168 writel(0x08, priv->mmio + RK3568_PHYREG13); 1169 writel(0x57, priv->mmio + RK3568_PHYREG14); 1170 writel(0x40, priv->mmio + RK3568_PHYREG15); 1171 1172 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 1173 1174 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, 1175 RK3576_PHYREG33_PLL_KVCO_VALUE); 1176 writel(val, priv->mmio + RK3568_PHYREG33); 1177 } 1178 } 1179 1180 return 0; 1181 } 1182 1183 static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { 1184 /* pipe-phy-grf */ 1185 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 1186 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 1187 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 1188 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 1189 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 1190 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, 1191 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 1192 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 1193 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 1194 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 1195 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 1196 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 1197 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 1198 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 1199 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 1200 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 1201 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 1202 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 1203 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 1204 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 1205 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 1206 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 1207 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 1208 /* php-grf */ 1209 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, 1210 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, 1211 }; 1212 1213 static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { 1214 .num_phys = 2, 1215 .phy_ids = { 1216 0x2b050000, 1217 0x2b060000 1218 }, 1219 .grfcfg = &rk3576_combphy_grfcfgs, 1220 .combphy_cfg = rk3576_combphy_cfg, 1221 }; 1222 1223 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 1224 { 1225 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 1226 unsigned long rate; 1227 u32 val; 1228 1229 switch (priv->type) { 1230 case PHY_TYPE_PCIE: 1231 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 1232 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 1233 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 1234 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 1235 switch (priv->id) { 1236 case 1: 1237 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); 1238 break; 1239 case 2: 1240 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); 1241 break; 1242 } 1243 break; 1244 case PHY_TYPE_USB3: 1245 /* Set SSC downward spread spectrum */ 1246 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 1247 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 1248 1249 /* Enable adaptive CTLE for USB3.0 Rx. */ 1250 val = readl(priv->mmio + RK3568_PHYREG15); 1251 val |= RK3568_PHYREG15_CTLE_EN; 1252 writel(val, priv->mmio + RK3568_PHYREG15); 1253 1254 /* Set PLL KVCO fine tuning signals. */ 1255 val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT; 1256 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33); 1257 1258 /* Enable controlling random jitter. */ 1259 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 1260 1261 /* Set PLL input clock divider 1/2. */ 1262 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, 1263 RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT, 1264 RK3568_PHYREG6); 1265 1266 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 1267 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 1268 1269 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 1270 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 1271 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 1272 break; 1273 case PHY_TYPE_SATA: 1274 /* Enable adaptive CTLE for SATA Rx. */ 1275 val = readl(priv->mmio + RK3568_PHYREG15); 1276 val |= RK3568_PHYREG15_CTLE_EN; 1277 writel(val, priv->mmio + RK3568_PHYREG15); 1278 /* 1279 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. 1280 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) 1281 */ 1282 val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; 1283 val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; 1284 writel(val, priv->mmio + RK3568_PHYREG7); 1285 1286 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); 1287 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); 1288 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); 1289 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); 1290 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 1291 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 1292 break; 1293 case PHY_TYPE_SGMII: 1294 case PHY_TYPE_QSGMII: 1295 default: 1296 dev_err(priv->dev, "incompatible PHY type\n"); 1297 return -EINVAL; 1298 } 1299 1300 rate = clk_get_rate(priv->refclk); 1301 1302 switch (rate) { 1303 case REF_CLOCK_24MHz: 1304 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { 1305 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ 1306 val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT; 1307 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, 1308 val, RK3568_PHYREG15); 1309 1310 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 1311 } 1312 break; 1313 1314 case REF_CLOCK_25MHz: 1315 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 1316 break; 1317 case REF_CLOCK_100MHz: 1318 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 1319 if (priv->type == PHY_TYPE_PCIE) { 1320 /* PLL KVCO fine tuning. */ 1321 val = 4 << RK3568_PHYREG33_PLL_KVCO_SHIFT; 1322 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 1323 val, RK3568_PHYREG33); 1324 1325 /* Enable controlling random jitter. */ 1326 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 1327 1328 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 1329 writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27); 1330 1331 /* Set up su_trim: */ 1332 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 1333 } else if (priv->type == PHY_TYPE_SATA) { 1334 /* downward spread spectrum +500ppm */ 1335 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 1336 val |= RK3568_PHYREG32_SSC_OFFSET_500PPM << 1337 RK3568_PHYREG32_SSC_OFFSET_SHIFT; 1338 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, 1339 RK3568_PHYREG32); 1340 } 1341 break; 1342 default: 1343 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); 1344 return -EINVAL; 1345 } 1346 1347 if (priv->ext_refclk) { 1348 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 1349 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 1350 val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT; 1351 val |= RK3568_PHYREG13_CKRCV_AMP0; 1352 rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, 1353 RK3568_PHYREG13); 1354 1355 val = readl(priv->mmio + RK3568_PHYREG14); 1356 val |= RK3568_PHYREG14_CKRCV_AMP1; 1357 writel(val, priv->mmio + RK3568_PHYREG14); 1358 } 1359 } 1360 1361 if (priv->enable_ssc) { 1362 val = readl(priv->mmio + RK3568_PHYREG8); 1363 val |= RK3568_PHYREG8_SSC_EN; 1364 writel(val, priv->mmio + RK3568_PHYREG8); 1365 } 1366 1367 return 0; 1368 } 1369 1370 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 1371 /* pipe-phy-grf */ 1372 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 1373 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 1374 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 1375 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 1376 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 1377 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 1378 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 1379 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 1380 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 1381 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 1382 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 1383 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 1384 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 1385 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 1386 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 1387 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 1388 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 1389 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 1390 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 1391 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 1392 /* pipe-grf */ 1393 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 1394 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 1395 .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 }, 1396 .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 }, 1397 }; 1398 1399 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 1400 .num_phys = 3, 1401 .phy_ids = { 1402 0xfee00000, 1403 0xfee10000, 1404 0xfee20000, 1405 }, 1406 .grfcfg = &rk3588_combphy_grfcfgs, 1407 .combphy_cfg = rk3588_combphy_cfg, 1408 }; 1409 1410 static const struct of_device_id rockchip_combphy_of_match[] = { 1411 { 1412 .compatible = "rockchip,rk3528-naneng-combphy", 1413 .data = &rk3528_combphy_cfgs, 1414 }, 1415 { 1416 .compatible = "rockchip,rk3562-naneng-combphy", 1417 .data = &rk3562_combphy_cfgs, 1418 }, 1419 { 1420 .compatible = "rockchip,rk3568-naneng-combphy", 1421 .data = &rk3568_combphy_cfgs, 1422 }, 1423 { 1424 .compatible = "rockchip,rk3576-naneng-combphy", 1425 .data = &rk3576_combphy_cfgs, 1426 }, 1427 { 1428 .compatible = "rockchip,rk3588-naneng-combphy", 1429 .data = &rk3588_combphy_cfgs, 1430 }, 1431 { }, 1432 }; 1433 MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); 1434 1435 static struct platform_driver rockchip_combphy_driver = { 1436 .probe = rockchip_combphy_probe, 1437 .driver = { 1438 .name = "rockchip-naneng-combphy", 1439 .of_match_table = rockchip_combphy_of_match, 1440 }, 1441 }; 1442 module_platform_driver(rockchip_combphy_driver); 1443 1444 MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver"); 1445 MODULE_LICENSE("GPL v2"); 1446