1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <dt-bindings/phy/phy.h> 9 #include <linux/clk.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/of.h> 12 #include <linux/phy/phy.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/reset.h> 16 #include <linux/units.h> 17 18 #define BIT_WRITEABLE_SHIFT 16 19 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) 20 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) 21 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) 22 23 /* RK3528 COMBO PHY REG */ 24 #define RK3528_PHYREG5 0x14 25 #define RK3528_PHYREG5_GATE_TX_PCK_SEL BIT(3) 26 #define RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF BIT(3) 27 #define RK3528_PHYREG6 0x18 28 #define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10) 29 #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2 30 #define RK3528_PHYREG6_SSC_DIR GENMASK(5, 4) 31 #define RK3528_PHYREG6_SSC_UPWARD 0 32 #define RK3528_PHYREG6_SSC_DOWNWARD 1 33 34 #define RK3528_PHYREG40 0x100 35 #define RK3528_PHYREG40_SSC_EN BIT(20) 36 #define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0) 37 #define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d 38 39 #define RK3528_PHYREG42 0x108 40 #define RK3528_PHYREG42_CKDRV_CLK_SEL BIT(29) 41 #define RK3528_PHYREG42_CKDRV_CLK_PLL 0 42 #define RK3528_PHYREG42_CKDRV_CLK_CKRCV 1 43 #define RK3528_PHYREG42_PLL_LPF_R1_ADJ GENMASK(10, 7) 44 #define RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE 0x9 45 #define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ GENMASK(6, 4) 46 #define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7 47 #define RK3528_PHYREG42_PLL_KVCO_ADJ GENMASK(2, 0) 48 #define RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE 0x0 49 50 #define RK3528_PHYREG80 0x200 51 #define RK3528_PHYREG80_CTLE_EN BIT(17) 52 53 #define RK3528_PHYREG81 0x204 54 #define RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X BIT(5) 55 #define RK3528_PHYREG81_SLEW_RATE_CTRL GENMASK(2, 0) 56 #define RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW 0x7 57 58 #define RK3528_PHYREG83 0x20c 59 #define RK3528_PHYREG83_RX_SQUELCH GENMASK(2, 0) 60 #define RK3528_PHYREG83_RX_SQUELCH_VALUE 0x6 61 62 #define RK3528_PHYREG86 0x218 63 #define RK3528_PHYREG86_RTERM_DET_CLK_EN BIT(14) 64 65 /* RK3568 COMBO PHY REG */ 66 #define RK3568_PHYREG6 0x14 67 #define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6) 68 #define RK3568_PHYREG6_PLL_DIV_SHIFT 6 69 #define RK3568_PHYREG6_PLL_DIV_2 1 70 71 #define RK3568_PHYREG7 0x18 72 #define RK3568_PHYREG7_TX_RTERM_MASK GENMASK(7, 4) 73 #define RK3568_PHYREG7_TX_RTERM_SHIFT 4 74 #define RK3568_PHYREG7_TX_RTERM_50OHM 8 75 #define RK3568_PHYREG7_RX_RTERM_MASK GENMASK(3, 0) 76 #define RK3568_PHYREG7_RX_RTERM_SHIFT 0 77 #define RK3568_PHYREG7_RX_RTERM_44OHM 15 78 79 #define RK3568_PHYREG8 0x1C 80 #define RK3568_PHYREG8_SSC_EN BIT(4) 81 82 #define RK3568_PHYREG11 0x28 83 #define RK3568_PHYREG11_SU_TRIM_0_7 0xF0 84 85 #define RK3568_PHYREG12 0x2C 86 #define RK3568_PHYREG12_PLL_LPF_ADJ_VALUE 4 87 88 #define RK3568_PHYREG13 0x30 89 #define RK3568_PHYREG13_RESISTER_MASK GENMASK(5, 4) 90 #define RK3568_PHYREG13_RESISTER_SHIFT 0x4 91 #define RK3568_PHYREG13_RESISTER_HIGH_Z 3 92 #define RK3568_PHYREG13_CKRCV_AMP0 BIT(7) 93 94 #define RK3568_PHYREG14 0x34 95 #define RK3568_PHYREG14_CKRCV_AMP1 BIT(0) 96 97 #define RK3568_PHYREG15 0x38 98 #define RK3568_PHYREG15_CTLE_EN BIT(0) 99 #define RK3568_PHYREG15_SSC_CNT_MASK GENMASK(7, 6) 100 #define RK3568_PHYREG15_SSC_CNT_SHIFT 6 101 #define RK3568_PHYREG15_SSC_CNT_VALUE 1 102 103 #define RK3568_PHYREG16 0x3C 104 #define RK3568_PHYREG16_SSC_CNT_VALUE 0x5f 105 106 #define RK3568_PHYREG18 0x44 107 #define RK3568_PHYREG18_PLL_LOOP 0x32 108 109 #define RK3568_PHYREG30 0x74 110 #define RK3568_PHYREG30_GATE_TX_PCK_SEL BIT(7) 111 #define RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF BIT(7) 112 113 #define RK3568_PHYREG32 0x7C 114 #define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4) 115 #define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4) 116 #define RK3568_PHYREG32_SSC_DIR_SHIFT 4 117 #define RK3568_PHYREG32_SSC_UPWARD 0 118 #define RK3568_PHYREG32_SSC_DOWNWARD 1 119 #define RK3568_PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6) 120 #define RK3568_PHYREG32_SSC_OFFSET_SHIFT 6 121 #define RK3568_PHYREG32_SSC_OFFSET_500PPM 1 122 123 #define RK3568_PHYREG33 0x80 124 #define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) 125 #define RK3568_PHYREG33_PLL_KVCO_SHIFT 2 126 #define RK3568_PHYREG33_PLL_KVCO_VALUE 2 127 #define RK3576_PHYREG33_PLL_KVCO_VALUE 4 128 129 /* RK3588 COMBO PHY registers */ 130 #define RK3588_PHYREG27 0x6C 131 #define RK3588_PHYREG27_RX_TRIM 0x4C 132 133 /* RK3576 COMBO PHY registers */ 134 #define RK3576_PHYREG10 0x24 135 #define RK3576_PHYREG10_SSC_PCM_MASK GENMASK(3, 0) 136 #define RK3576_PHYREG10_SSC_PCM_3500PPM 7 137 138 #define RK3576_PHYREG17 0x40 139 140 #define RK3576_PHYREG21 0x50 141 #define RK3576_PHYREG21_RX_SQUELCH_VAL 0x0D 142 143 #define RK3576_PHYREG30 0x74 144 145 struct rockchip_combphy_priv; 146 147 struct combphy_reg { 148 u16 offset; 149 u16 bitend; 150 u16 bitstart; 151 u16 disable; 152 u16 enable; 153 }; 154 155 struct rockchip_combphy_grfcfg { 156 struct combphy_reg pcie_mode_set; 157 struct combphy_reg usb_mode_set; 158 struct combphy_reg sgmii_mode_set; 159 struct combphy_reg qsgmii_mode_set; 160 struct combphy_reg pipe_rxterm_set; 161 struct combphy_reg pipe_txelec_set; 162 struct combphy_reg pipe_txcomp_set; 163 struct combphy_reg pipe_clk_24m; 164 struct combphy_reg pipe_clk_25m; 165 struct combphy_reg pipe_clk_100m; 166 struct combphy_reg pipe_phymode_sel; 167 struct combphy_reg pipe_rate_sel; 168 struct combphy_reg pipe_rxterm_sel; 169 struct combphy_reg pipe_txelec_sel; 170 struct combphy_reg pipe_txcomp_sel; 171 struct combphy_reg pipe_clk_ext; 172 struct combphy_reg pipe_sel_usb; 173 struct combphy_reg pipe_sel_qsgmii; 174 struct combphy_reg pipe_phy_status; 175 struct combphy_reg con0_for_pcie; 176 struct combphy_reg con1_for_pcie; 177 struct combphy_reg con2_for_pcie; 178 struct combphy_reg con3_for_pcie; 179 struct combphy_reg con0_for_sata; 180 struct combphy_reg con1_for_sata; 181 struct combphy_reg con2_for_sata; 182 struct combphy_reg con3_for_sata; 183 struct combphy_reg pipe_con0_for_sata; 184 struct combphy_reg pipe_con1_for_sata; 185 struct combphy_reg pipe_xpcs_phy_ready; 186 struct combphy_reg pipe_pcie1l0_sel; 187 struct combphy_reg pipe_pcie1l1_sel; 188 struct combphy_reg u3otg0_port_en; 189 struct combphy_reg u3otg1_port_en; 190 }; 191 192 struct rockchip_combphy_cfg { 193 unsigned int num_phys; 194 unsigned int phy_ids[3]; 195 const struct rockchip_combphy_grfcfg *grfcfg; 196 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 197 }; 198 199 struct rockchip_combphy_priv { 200 u8 type; 201 int id; 202 void __iomem *mmio; 203 int num_clks; 204 struct clk_bulk_data *clks; 205 struct device *dev; 206 struct regmap *pipe_grf; 207 struct regmap *phy_grf; 208 struct phy *phy; 209 struct reset_control *phy_rst; 210 const struct rockchip_combphy_cfg *cfg; 211 bool enable_ssc; 212 bool ext_refclk; 213 struct clk *refclk; 214 }; 215 216 static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, 217 int mask, int val, int reg) 218 { 219 unsigned int temp; 220 221 temp = readl(priv->mmio + reg); 222 temp = (temp & ~(mask)) | val; 223 writel(temp, priv->mmio + reg); 224 } 225 226 static int rockchip_combphy_param_write(struct regmap *base, 227 const struct combphy_reg *reg, bool en) 228 { 229 u32 val, mask, tmp; 230 231 tmp = en ? reg->enable : reg->disable; 232 mask = GENMASK(reg->bitend, reg->bitstart); 233 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 234 235 return regmap_write(base, reg->offset, val); 236 } 237 238 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 239 { 240 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 241 u32 mask, val; 242 243 mask = GENMASK(cfg->pipe_phy_status.bitend, 244 cfg->pipe_phy_status.bitstart); 245 246 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 247 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 248 249 return val; 250 } 251 252 static int rockchip_combphy_init(struct phy *phy) 253 { 254 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); 255 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 256 u32 val; 257 int ret; 258 259 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); 260 if (ret) { 261 dev_err(priv->dev, "failed to enable clks\n"); 262 return ret; 263 } 264 265 switch (priv->type) { 266 case PHY_TYPE_PCIE: 267 case PHY_TYPE_USB3: 268 case PHY_TYPE_SATA: 269 case PHY_TYPE_SGMII: 270 case PHY_TYPE_QSGMII: 271 if (priv->cfg->combphy_cfg) 272 ret = priv->cfg->combphy_cfg(priv); 273 break; 274 default: 275 dev_err(priv->dev, "incompatible PHY type\n"); 276 ret = -EINVAL; 277 break; 278 } 279 280 if (ret) { 281 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); 282 goto err_clk; 283 } 284 285 ret = reset_control_deassert(priv->phy_rst); 286 if (ret) 287 goto err_clk; 288 289 if (priv->type == PHY_TYPE_USB3) { 290 ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, 291 priv, val, 292 val == cfg->pipe_phy_status.enable, 293 10, 1000); 294 if (ret) 295 dev_warn(priv->dev, "wait phy status ready timeout\n"); 296 } 297 298 return 0; 299 300 err_clk: 301 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); 302 303 return ret; 304 } 305 306 static int rockchip_combphy_exit(struct phy *phy) 307 { 308 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); 309 310 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); 311 reset_control_assert(priv->phy_rst); 312 313 return 0; 314 } 315 316 static const struct phy_ops rockchip_combphy_ops = { 317 .init = rockchip_combphy_init, 318 .exit = rockchip_combphy_exit, 319 .owner = THIS_MODULE, 320 }; 321 322 static struct phy *rockchip_combphy_xlate(struct device *dev, const struct of_phandle_args *args) 323 { 324 struct rockchip_combphy_priv *priv = dev_get_drvdata(dev); 325 326 if (args->args_count != 1) { 327 dev_err(dev, "invalid number of arguments\n"); 328 return ERR_PTR(-EINVAL); 329 } 330 331 if (priv->type != PHY_NONE && priv->type != args->args[0]) 332 dev_warn(dev, "phy type select %d overwriting type %d\n", 333 args->args[0], priv->type); 334 335 priv->type = args->args[0]; 336 337 return priv->phy; 338 } 339 340 static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) 341 { 342 int i; 343 344 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); 345 if (priv->num_clks < 1) 346 return -EINVAL; 347 348 priv->refclk = NULL; 349 for (i = 0; i < priv->num_clks; i++) { 350 if (!strncmp(priv->clks[i].id, "ref", 3)) { 351 priv->refclk = priv->clks[i].clk; 352 break; 353 } 354 } 355 356 if (!priv->refclk) { 357 dev_err(dev, "no refclk found\n"); 358 return -EINVAL; 359 } 360 361 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); 362 if (IS_ERR(priv->pipe_grf)) { 363 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); 364 return PTR_ERR(priv->pipe_grf); 365 } 366 367 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); 368 if (IS_ERR(priv->phy_grf)) { 369 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 370 return PTR_ERR(priv->phy_grf); 371 } 372 373 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); 374 375 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); 376 377 priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy"); 378 /* fallback to old behaviour */ 379 if (PTR_ERR(priv->phy_rst) == -ENOENT) 380 priv->phy_rst = devm_reset_control_array_get_exclusive(dev); 381 if (IS_ERR(priv->phy_rst)) 382 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); 383 384 return 0; 385 } 386 387 static int rockchip_combphy_probe(struct platform_device *pdev) 388 { 389 struct phy_provider *phy_provider; 390 struct device *dev = &pdev->dev; 391 struct rockchip_combphy_priv *priv; 392 const struct rockchip_combphy_cfg *phy_cfg; 393 struct resource *res; 394 int ret, id; 395 396 phy_cfg = of_device_get_match_data(dev); 397 if (!phy_cfg) { 398 dev_err(dev, "no OF match data provided\n"); 399 return -EINVAL; 400 } 401 402 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 403 if (!priv) 404 return -ENOMEM; 405 406 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 407 if (IS_ERR(priv->mmio)) { 408 ret = PTR_ERR(priv->mmio); 409 return ret; 410 } 411 412 /* find the phy-id from the io address */ 413 priv->id = -ENODEV; 414 for (id = 0; id < phy_cfg->num_phys; id++) { 415 if (res->start == phy_cfg->phy_ids[id]) { 416 priv->id = id; 417 break; 418 } 419 } 420 421 priv->dev = dev; 422 priv->type = PHY_NONE; 423 priv->cfg = phy_cfg; 424 425 ret = rockchip_combphy_parse_dt(dev, priv); 426 if (ret) 427 return ret; 428 429 ret = reset_control_assert(priv->phy_rst); 430 if (ret) { 431 dev_err(dev, "failed to reset phy\n"); 432 return ret; 433 } 434 435 priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops); 436 if (IS_ERR(priv->phy)) { 437 dev_err(dev, "failed to create combphy\n"); 438 return PTR_ERR(priv->phy); 439 } 440 441 dev_set_drvdata(dev, priv); 442 phy_set_drvdata(priv->phy, priv); 443 444 phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate); 445 446 return PTR_ERR_OR_ZERO(phy_provider); 447 } 448 449 static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) 450 { 451 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 452 unsigned long rate; 453 u32 val; 454 455 /* Set SSC downward spread spectrum */ 456 val = FIELD_PREP(RK3528_PHYREG6_SSC_DIR, RK3528_PHYREG6_SSC_DOWNWARD); 457 rockchip_combphy_updatel(priv, RK3528_PHYREG6_SSC_DIR, val, RK3528_PHYREG6); 458 459 switch (priv->type) { 460 case PHY_TYPE_PCIE: 461 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 462 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 463 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 464 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 465 break; 466 case PHY_TYPE_USB3: 467 /* Enable adaptive CTLE for USB3.0 Rx */ 468 rockchip_combphy_updatel(priv, RK3528_PHYREG80_CTLE_EN, RK3528_PHYREG80_CTLE_EN, 469 RK3528_PHYREG80); 470 471 /* Set slow slew rate control for PI */ 472 val = FIELD_PREP(RK3528_PHYREG81_SLEW_RATE_CTRL, 473 RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW); 474 rockchip_combphy_updatel(priv, RK3528_PHYREG81_SLEW_RATE_CTRL, val, 475 RK3528_PHYREG81); 476 477 /* Set CDR phase path with 2x gain */ 478 rockchip_combphy_updatel(priv, RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, 479 RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, RK3528_PHYREG81); 480 481 /* Set Rx squelch input filler bandwidth */ 482 val = FIELD_PREP(RK3528_PHYREG83_RX_SQUELCH, RK3528_PHYREG83_RX_SQUELCH_VALUE); 483 rockchip_combphy_updatel(priv, RK3528_PHYREG83_RX_SQUELCH, val, RK3528_PHYREG83); 484 485 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 486 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 487 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 488 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); 489 break; 490 default: 491 dev_err(priv->dev, "incompatible PHY type\n"); 492 return -EINVAL; 493 } 494 495 rate = clk_get_rate(priv->refclk); 496 497 switch (rate) { 498 case REF_CLOCK_24MHz: 499 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); 500 if (priv->type == PHY_TYPE_USB3) { 501 /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */ 502 val = FIELD_PREP(RK3528_PHYREG40_SSC_CNT, RK3528_PHYREG40_SSC_CNT_VALUE); 503 rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_CNT, val, 504 RK3528_PHYREG40); 505 } else if (priv->type == PHY_TYPE_PCIE) { 506 /* tx_trim[14]=1, Enable the counting clock of the rterm detect */ 507 rockchip_combphy_updatel(priv, RK3528_PHYREG86_RTERM_DET_CLK_EN, 508 RK3528_PHYREG86_RTERM_DET_CLK_EN, RK3528_PHYREG86); 509 } 510 break; 511 case REF_CLOCK_100MHz: 512 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 513 if (priv->type == PHY_TYPE_PCIE) { 514 /* Gate_tx_pck_sel length select for L1ss support */ 515 rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL, 516 RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF, RK3528_PHYREG5); 517 518 /* PLL KVCO tuning fine */ 519 val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE); 520 rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val, 521 RK3528_PHYREG6); 522 523 /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */ 524 writel(0x570804f0, priv->mmio + RK3528_PHYREG42); 525 } 526 break; 527 default: 528 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); 529 return -EINVAL; 530 } 531 532 if (priv->ext_refclk) { 533 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 534 535 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 536 val = FIELD_PREP(RK3528_PHYREG42_CKDRV_CLK_SEL, 537 RK3528_PHYREG42_CKDRV_CLK_CKRCV); 538 val |= FIELD_PREP(RK3528_PHYREG42_PLL_LPF_R1_ADJ, 539 RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE); 540 val |= FIELD_PREP(RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ, 541 RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE); 542 val |= FIELD_PREP(RK3528_PHYREG42_PLL_KVCO_ADJ, 543 RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE); 544 rockchip_combphy_updatel(priv, 545 RK3528_PHYREG42_CKDRV_CLK_SEL | 546 RK3528_PHYREG42_PLL_LPF_R1_ADJ | 547 RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ | 548 RK3528_PHYREG42_PLL_KVCO_ADJ, 549 val, RK3528_PHYREG42); 550 551 val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE); 552 rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val, 553 RK3528_PHYREG6); 554 } 555 } 556 557 if (priv->type == PHY_TYPE_PCIE && priv->enable_ssc) 558 rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN, 559 RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40); 560 561 return 0; 562 } 563 564 static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { 565 /* pipe-phy-grf */ 566 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 567 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 568 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 569 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 570 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 571 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, 572 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 573 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 574 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 575 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 576 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 577 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 578 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 }, 579 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 }, 580 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 }, 581 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 582 /* pipe-grf */ 583 .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 }, 584 }; 585 586 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { 587 .num_phys = 1, 588 .phy_ids = { 589 0xffdc0000, 590 }, 591 .grfcfg = &rk3528_combphy_grfcfgs, 592 .combphy_cfg = rk3528_combphy_cfg, 593 }; 594 595 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv) 596 { 597 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 598 unsigned long rate; 599 u32 val; 600 601 switch (priv->type) { 602 case PHY_TYPE_PCIE: 603 /* Set SSC downward spread spectrum */ 604 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 605 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 606 607 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 608 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 609 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 610 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 611 break; 612 case PHY_TYPE_USB3: 613 /* Set SSC downward spread spectrum */ 614 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 615 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, 616 RK3568_PHYREG32); 617 618 /* Enable adaptive CTLE for USB3.0 Rx */ 619 rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN, 620 RK3568_PHYREG15_CTLE_EN, RK3568_PHYREG15); 621 622 /* Set PLL KVCO fine tuning signals */ 623 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 624 BIT(3), RK3568_PHYREG33); 625 626 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 627 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 628 629 /* Set PLL input clock divider 1/2 */ 630 val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2); 631 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6); 632 633 /* Set PLL loop divider */ 634 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 635 636 /* Set PLL KVCO to min and set PLL charge pump current to max */ 637 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 638 639 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 640 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 641 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 642 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 643 break; 644 default: 645 dev_err(priv->dev, "incompatible PHY type\n"); 646 return -EINVAL; 647 } 648 649 rate = clk_get_rate(priv->refclk); 650 651 switch (rate) { 652 case REF_CLOCK_24MHz: 653 if (priv->type == PHY_TYPE_USB3) { 654 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ 655 val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK, 656 RK3568_PHYREG15_SSC_CNT_VALUE); 657 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, 658 val, RK3568_PHYREG15); 659 660 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 661 } 662 break; 663 case REF_CLOCK_25MHz: 664 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 665 break; 666 case REF_CLOCK_100MHz: 667 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 668 if (priv->type == PHY_TYPE_PCIE) { 669 /* Gate_tx_pck_sel length select for L1ss support */ 670 rockchip_combphy_updatel(priv, RK3568_PHYREG30_GATE_TX_PCK_SEL, 671 RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF, 672 RK3568_PHYREG30); 673 /* PLL KVCO tuning fine */ 674 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, 675 RK3568_PHYREG33_PLL_KVCO_VALUE); 676 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 677 val, RK3568_PHYREG33); 678 679 /* Enable controlling random jitter, aka RMJ */ 680 writel(0x4, priv->mmio + RK3568_PHYREG12); 681 682 val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT; 683 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, 684 val, RK3568_PHYREG6); 685 686 writel(0x32, priv->mmio + RK3568_PHYREG18); 687 writel(0xf0, priv->mmio + RK3568_PHYREG11); 688 } 689 break; 690 default: 691 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); 692 return -EINVAL; 693 } 694 695 if (priv->ext_refclk) { 696 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 697 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 698 val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT; 699 val |= RK3568_PHYREG13_CKRCV_AMP0; 700 rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, 701 RK3568_PHYREG13); 702 703 val = readl(priv->mmio + RK3568_PHYREG14); 704 val |= RK3568_PHYREG14_CKRCV_AMP1; 705 writel(val, priv->mmio + RK3568_PHYREG14); 706 } 707 } 708 709 if (priv->enable_ssc) { 710 val = readl(priv->mmio + RK3568_PHYREG8); 711 val |= RK3568_PHYREG8_SSC_EN; 712 writel(val, priv->mmio + RK3568_PHYREG8); 713 } 714 715 return 0; 716 } 717 718 static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = { 719 /* pipe-phy-grf */ 720 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 721 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 722 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 723 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 724 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 725 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 726 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 727 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 728 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 729 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 730 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 731 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 732 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 733 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 734 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 735 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 736 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 737 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 738 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 739 }; 740 741 static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { 742 .num_phys = 1, 743 .phy_ids = { 744 0xff750000 745 }, 746 .grfcfg = &rk3562_combphy_grfcfgs, 747 .combphy_cfg = rk3562_combphy_cfg, 748 }; 749 750 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 751 { 752 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 753 unsigned long rate; 754 u32 val; 755 756 switch (priv->type) { 757 case PHY_TYPE_PCIE: 758 /* Set SSC downward spread spectrum. */ 759 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 760 761 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 762 763 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 764 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 765 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 766 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 767 break; 768 769 case PHY_TYPE_USB3: 770 /* Set SSC downward spread spectrum. */ 771 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT, 772 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 773 774 /* Enable adaptive CTLE for USB3.0 Rx. */ 775 val = readl(priv->mmio + RK3568_PHYREG15); 776 val |= RK3568_PHYREG15_CTLE_EN; 777 writel(val, priv->mmio + RK3568_PHYREG15); 778 779 /* Set PLL KVCO fine tuning signals. */ 780 val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT; 781 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33); 782 783 /* Enable controlling random jitter. */ 784 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 785 786 /* Set PLL input clock divider 1/2. */ 787 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, 788 RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT, 789 RK3568_PHYREG6); 790 791 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 792 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 793 794 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 795 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 796 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 797 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 798 switch (priv->id) { 799 case 0: 800 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); 801 break; 802 case 1: 803 rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true); 804 break; 805 } 806 break; 807 808 case PHY_TYPE_SATA: 809 /* Enable adaptive CTLE for SATA Rx. */ 810 val = readl(priv->mmio + RK3568_PHYREG15); 811 val |= RK3568_PHYREG15_CTLE_EN; 812 writel(val, priv->mmio + RK3568_PHYREG15); 813 /* 814 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. 815 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) 816 */ 817 val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; 818 val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; 819 writel(val, priv->mmio + RK3568_PHYREG7); 820 821 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); 822 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); 823 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); 824 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); 825 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 826 break; 827 828 case PHY_TYPE_SGMII: 829 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 830 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 831 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 832 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 833 break; 834 835 case PHY_TYPE_QSGMII: 836 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 837 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 838 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 839 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 840 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 841 break; 842 843 default: 844 dev_err(priv->dev, "incompatible PHY type\n"); 845 return -EINVAL; 846 } 847 848 rate = clk_get_rate(priv->refclk); 849 850 switch (rate) { 851 case REF_CLOCK_24MHz: 852 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { 853 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ 854 val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT; 855 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, 856 val, RK3568_PHYREG15); 857 858 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 859 } 860 break; 861 862 case REF_CLOCK_25MHz: 863 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 864 break; 865 866 case REF_CLOCK_100MHz: 867 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 868 if (priv->type == PHY_TYPE_PCIE) { 869 /* PLL KVCO fine tuning. */ 870 val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT; 871 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 872 val, RK3568_PHYREG33); 873 874 /* Enable controlling random jitter. */ 875 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 876 877 val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT; 878 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, 879 val, RK3568_PHYREG6); 880 881 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 882 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 883 } else if (priv->type == PHY_TYPE_SATA) { 884 /* downward spread spectrum +500ppm */ 885 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 886 val |= RK3568_PHYREG32_SSC_OFFSET_500PPM << 887 RK3568_PHYREG32_SSC_OFFSET_SHIFT; 888 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, 889 RK3568_PHYREG32); 890 } 891 break; 892 893 default: 894 dev_err(priv->dev, "unsupported rate: %lu\n", rate); 895 return -EINVAL; 896 } 897 898 if (priv->ext_refclk) { 899 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 900 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 901 val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT; 902 val |= RK3568_PHYREG13_CKRCV_AMP0; 903 rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, 904 RK3568_PHYREG13); 905 906 val = readl(priv->mmio + RK3568_PHYREG14); 907 val |= RK3568_PHYREG14_CKRCV_AMP1; 908 writel(val, priv->mmio + RK3568_PHYREG14); 909 } 910 } 911 912 if (priv->enable_ssc) { 913 val = readl(priv->mmio + RK3568_PHYREG8); 914 val |= RK3568_PHYREG8_SSC_EN; 915 writel(val, priv->mmio + RK3568_PHYREG8); 916 } 917 918 return 0; 919 } 920 921 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 922 /* pipe-phy-grf */ 923 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 924 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 925 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 926 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 927 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 928 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 929 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 930 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 931 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 932 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 933 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 934 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 935 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 936 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 937 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 938 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 939 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 940 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 941 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 942 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 943 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 944 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 945 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 946 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 947 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 948 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 949 /* pipe-grf */ 950 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 951 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 952 .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, 953 .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, 954 }; 955 956 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 957 .num_phys = 3, 958 .phy_ids = { 959 0xfe820000, 960 0xfe830000, 961 0xfe840000, 962 }, 963 .grfcfg = &rk3568_combphy_grfcfgs, 964 .combphy_cfg = rk3568_combphy_cfg, 965 }; 966 967 static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) 968 { 969 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 970 unsigned long rate; 971 u32 val; 972 973 switch (priv->type) { 974 case PHY_TYPE_PCIE: 975 /* Set SSC downward spread spectrum */ 976 val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD); 977 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 978 979 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 980 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 981 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 982 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 983 break; 984 985 case PHY_TYPE_USB3: 986 /* Set SSC downward spread spectrum */ 987 val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD); 988 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 989 990 /* Enable adaptive CTLE for USB3.0 Rx */ 991 val = readl(priv->mmio + RK3568_PHYREG15); 992 val |= RK3568_PHYREG15_CTLE_EN; 993 writel(val, priv->mmio + RK3568_PHYREG15); 994 995 /* Set PLL KVCO fine tuning signals */ 996 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, BIT(3), 997 RK3568_PHYREG33); 998 999 /* Set PLL LPF R1 to su_trim[10:7]=1001 */ 1000 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 1001 1002 /* Set PLL input clock divider 1/2 */ 1003 val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2); 1004 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6); 1005 1006 /* Set PLL loop divider */ 1007 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 1008 1009 /* Set PLL KVCO to min and set PLL charge pump current to max */ 1010 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 1011 1012 /* Set Rx squelch input filler bandwidth */ 1013 writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21); 1014 1015 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 1016 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 1017 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 1018 break; 1019 1020 case PHY_TYPE_SATA: 1021 /* Enable adaptive CTLE for SATA Rx */ 1022 val = readl(priv->mmio + RK3568_PHYREG15); 1023 val |= RK3568_PHYREG15_CTLE_EN; 1024 writel(val, priv->mmio + RK3568_PHYREG15); 1025 1026 /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ 1027 val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; 1028 val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; 1029 writel(val, priv->mmio + RK3568_PHYREG7); 1030 1031 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); 1032 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); 1033 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); 1034 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); 1035 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 1036 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 1037 break; 1038 1039 default: 1040 dev_err(priv->dev, "incompatible PHY type\n"); 1041 return -EINVAL; 1042 } 1043 1044 rate = clk_get_rate(priv->refclk); 1045 1046 switch (rate) { 1047 case REF_CLOCK_24MHz: 1048 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true); 1049 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { 1050 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ 1051 val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK, 1052 RK3568_PHYREG15_SSC_CNT_VALUE); 1053 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, 1054 val, RK3568_PHYREG15); 1055 1056 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 1057 } else if (priv->type == PHY_TYPE_PCIE) { 1058 /* PLL KVCO tuning fine */ 1059 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, 1060 RK3576_PHYREG33_PLL_KVCO_VALUE); 1061 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 1062 val, RK3568_PHYREG33); 1063 1064 /* Set up rx_pck invert and rx msb to disable */ 1065 writel(0x00, priv->mmio + RK3588_PHYREG27); 1066 1067 /* 1068 * Set up SU adjust signal: 1069 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min 1070 * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b011 1071 * su_trim[31:24], CKDRV adjust 1072 */ 1073 writel(0x90, priv->mmio + RK3568_PHYREG11); 1074 writel(0x02, priv->mmio + RK3568_PHYREG12); 1075 writel(0x57, priv->mmio + RK3568_PHYREG14); 1076 1077 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 1078 } 1079 break; 1080 1081 case REF_CLOCK_25MHz: 1082 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 1083 break; 1084 1085 case REF_CLOCK_100MHz: 1086 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 1087 if (priv->type == PHY_TYPE_PCIE) { 1088 /* gate_tx_pck_sel length select work for L1SS */ 1089 writel(0xc0, priv->mmio + RK3576_PHYREG30); 1090 1091 /* PLL KVCO tuning fine */ 1092 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, 1093 RK3576_PHYREG33_PLL_KVCO_VALUE); 1094 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 1095 val, RK3568_PHYREG33); 1096 1097 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 1098 writel(0x4c, priv->mmio + RK3588_PHYREG27); 1099 1100 /* 1101 * Set up SU adjust signal: 1102 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min 1103 * su_trim[15:8], bypass PLL loop divider code, and 1104 * PLL LPF R1 adujst bits[9:7]=3'b101 1105 * su_trim[23:16], CKRCV adjust 1106 * su_trim[31:24], CKDRV adjust 1107 */ 1108 writel(0x90, priv->mmio + RK3568_PHYREG11); 1109 writel(0x43, priv->mmio + RK3568_PHYREG12); 1110 writel(0x88, priv->mmio + RK3568_PHYREG13); 1111 writel(0x56, priv->mmio + RK3568_PHYREG14); 1112 } else if (priv->type == PHY_TYPE_SATA) { 1113 /* downward spread spectrum +500ppm */ 1114 val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK, 1115 RK3568_PHYREG32_SSC_DOWNWARD); 1116 val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK, 1117 RK3568_PHYREG32_SSC_OFFSET_500PPM); 1118 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, 1119 RK3568_PHYREG32); 1120 1121 /* ssc ppm adjust to 3500ppm */ 1122 rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK, 1123 RK3576_PHYREG10_SSC_PCM_3500PPM, 1124 RK3576_PHYREG10); 1125 } 1126 break; 1127 1128 default: 1129 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); 1130 return -EINVAL; 1131 } 1132 1133 if (priv->ext_refclk) { 1134 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 1135 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 1136 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, 1137 RK3576_PHYREG33_PLL_KVCO_VALUE); 1138 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 1139 val, RK3568_PHYREG33); 1140 1141 /* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */ 1142 writel(0x0c, priv->mmio + RK3588_PHYREG27); 1143 1144 /* 1145 * Set up SU adjust signal: 1146 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min 1147 * su_trim[15:8], bypass PLL loop divider code, and 1148 * PLL LPF R1 adujst bits[9:7]=3'b101. 1149 * su_trim[23:16], CKRCV adjust 1150 * su_trim[31:24], CKDRV adjust 1151 */ 1152 writel(0x90, priv->mmio + RK3568_PHYREG11); 1153 writel(0x43, priv->mmio + RK3568_PHYREG12); 1154 writel(0x88, priv->mmio + RK3568_PHYREG13); 1155 writel(0x56, priv->mmio + RK3568_PHYREG14); 1156 } 1157 } 1158 1159 if (priv->enable_ssc) { 1160 val = readl(priv->mmio + RK3568_PHYREG8); 1161 val |= RK3568_PHYREG8_SSC_EN; 1162 writel(val, priv->mmio + RK3568_PHYREG8); 1163 1164 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) { 1165 /* Set PLL loop divider */ 1166 writel(0x00, priv->mmio + RK3576_PHYREG17); 1167 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 1168 1169 /* Set up rx_pck invert and rx msb to disable */ 1170 writel(0x00, priv->mmio + RK3588_PHYREG27); 1171 1172 /* 1173 * Set up SU adjust signal: 1174 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min 1175 * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101 1176 * su_trim[23:16], CKRCV adjust 1177 * su_trim[31:24], CKDRV adjust 1178 */ 1179 writel(0x90, priv->mmio + RK3568_PHYREG11); 1180 writel(0x02, priv->mmio + RK3568_PHYREG12); 1181 writel(0x08, priv->mmio + RK3568_PHYREG13); 1182 writel(0x57, priv->mmio + RK3568_PHYREG14); 1183 writel(0x40, priv->mmio + RK3568_PHYREG15); 1184 1185 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 1186 1187 val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK, 1188 RK3576_PHYREG33_PLL_KVCO_VALUE); 1189 writel(val, priv->mmio + RK3568_PHYREG33); 1190 } 1191 } 1192 1193 return 0; 1194 } 1195 1196 static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { 1197 /* pipe-phy-grf */ 1198 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 1199 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 1200 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 1201 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 1202 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 1203 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, 1204 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 1205 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 1206 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 1207 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 1208 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 1209 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 1210 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 1211 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 1212 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 1213 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 1214 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 1215 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 1216 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 1217 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 1218 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 1219 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 1220 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 1221 /* php-grf */ 1222 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, 1223 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, 1224 }; 1225 1226 static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { 1227 .num_phys = 2, 1228 .phy_ids = { 1229 0x2b050000, 1230 0x2b060000 1231 }, 1232 .grfcfg = &rk3576_combphy_grfcfgs, 1233 .combphy_cfg = rk3576_combphy_cfg, 1234 }; 1235 1236 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 1237 { 1238 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 1239 unsigned long rate; 1240 u32 val; 1241 1242 switch (priv->type) { 1243 case PHY_TYPE_PCIE: 1244 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 1245 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 1246 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 1247 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 1248 switch (priv->id) { 1249 case 1: 1250 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); 1251 break; 1252 case 2: 1253 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); 1254 break; 1255 } 1256 break; 1257 case PHY_TYPE_USB3: 1258 /* Set SSC downward spread spectrum */ 1259 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 1260 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32); 1261 1262 /* Enable adaptive CTLE for USB3.0 Rx. */ 1263 val = readl(priv->mmio + RK3568_PHYREG15); 1264 val |= RK3568_PHYREG15_CTLE_EN; 1265 writel(val, priv->mmio + RK3568_PHYREG15); 1266 1267 /* Set PLL KVCO fine tuning signals. */ 1268 val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT; 1269 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33); 1270 1271 /* Enable controlling random jitter. */ 1272 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 1273 1274 /* Set PLL input clock divider 1/2. */ 1275 rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, 1276 RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT, 1277 RK3568_PHYREG6); 1278 1279 writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18); 1280 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 1281 1282 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 1283 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 1284 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 1285 break; 1286 case PHY_TYPE_SATA: 1287 /* Enable adaptive CTLE for SATA Rx. */ 1288 val = readl(priv->mmio + RK3568_PHYREG15); 1289 val |= RK3568_PHYREG15_CTLE_EN; 1290 writel(val, priv->mmio + RK3568_PHYREG15); 1291 /* 1292 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. 1293 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) 1294 */ 1295 val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT; 1296 val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT; 1297 writel(val, priv->mmio + RK3568_PHYREG7); 1298 1299 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); 1300 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); 1301 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); 1302 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); 1303 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 1304 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 1305 break; 1306 case PHY_TYPE_SGMII: 1307 case PHY_TYPE_QSGMII: 1308 default: 1309 dev_err(priv->dev, "incompatible PHY type\n"); 1310 return -EINVAL; 1311 } 1312 1313 rate = clk_get_rate(priv->refclk); 1314 1315 switch (rate) { 1316 case REF_CLOCK_24MHz: 1317 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { 1318 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ 1319 val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT; 1320 rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK, 1321 val, RK3568_PHYREG15); 1322 1323 writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16); 1324 } 1325 break; 1326 1327 case REF_CLOCK_25MHz: 1328 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 1329 break; 1330 case REF_CLOCK_100MHz: 1331 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 1332 if (priv->type == PHY_TYPE_PCIE) { 1333 /* PLL KVCO fine tuning. */ 1334 val = 4 << RK3568_PHYREG33_PLL_KVCO_SHIFT; 1335 rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, 1336 val, RK3568_PHYREG33); 1337 1338 /* Enable controlling random jitter. */ 1339 writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12); 1340 1341 /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 1342 writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27); 1343 1344 /* Set up su_trim: */ 1345 writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11); 1346 } else if (priv->type == PHY_TYPE_SATA) { 1347 /* downward spread spectrum +500ppm */ 1348 val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT; 1349 val |= RK3568_PHYREG32_SSC_OFFSET_500PPM << 1350 RK3568_PHYREG32_SSC_OFFSET_SHIFT; 1351 rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, 1352 RK3568_PHYREG32); 1353 } 1354 break; 1355 default: 1356 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); 1357 return -EINVAL; 1358 } 1359 1360 if (priv->ext_refclk) { 1361 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 1362 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 1363 val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT; 1364 val |= RK3568_PHYREG13_CKRCV_AMP0; 1365 rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val, 1366 RK3568_PHYREG13); 1367 1368 val = readl(priv->mmio + RK3568_PHYREG14); 1369 val |= RK3568_PHYREG14_CKRCV_AMP1; 1370 writel(val, priv->mmio + RK3568_PHYREG14); 1371 } 1372 } 1373 1374 if (priv->enable_ssc) { 1375 val = readl(priv->mmio + RK3568_PHYREG8); 1376 val |= RK3568_PHYREG8_SSC_EN; 1377 writel(val, priv->mmio + RK3568_PHYREG8); 1378 } 1379 1380 return 0; 1381 } 1382 1383 static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 1384 /* pipe-phy-grf */ 1385 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 1386 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 1387 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 1388 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 1389 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 1390 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 1391 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 1392 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 1393 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 1394 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 1395 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 1396 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 1397 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 1398 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 1399 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 1400 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 1401 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 1402 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 1403 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 1404 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 1405 /* pipe-grf */ 1406 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 1407 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 1408 .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 }, 1409 .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 }, 1410 }; 1411 1412 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 1413 .num_phys = 3, 1414 .phy_ids = { 1415 0xfee00000, 1416 0xfee10000, 1417 0xfee20000, 1418 }, 1419 .grfcfg = &rk3588_combphy_grfcfgs, 1420 .combphy_cfg = rk3588_combphy_cfg, 1421 }; 1422 1423 static const struct of_device_id rockchip_combphy_of_match[] = { 1424 { 1425 .compatible = "rockchip,rk3528-naneng-combphy", 1426 .data = &rk3528_combphy_cfgs, 1427 }, 1428 { 1429 .compatible = "rockchip,rk3562-naneng-combphy", 1430 .data = &rk3562_combphy_cfgs, 1431 }, 1432 { 1433 .compatible = "rockchip,rk3568-naneng-combphy", 1434 .data = &rk3568_combphy_cfgs, 1435 }, 1436 { 1437 .compatible = "rockchip,rk3576-naneng-combphy", 1438 .data = &rk3576_combphy_cfgs, 1439 }, 1440 { 1441 .compatible = "rockchip,rk3588-naneng-combphy", 1442 .data = &rk3588_combphy_cfgs, 1443 }, 1444 { }, 1445 }; 1446 MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); 1447 1448 static struct platform_driver rockchip_combphy_driver = { 1449 .probe = rockchip_combphy_probe, 1450 .driver = { 1451 .name = "rockchip-naneng-combphy", 1452 .of_match_table = rockchip_combphy_of_match, 1453 }, 1454 }; 1455 module_platform_driver(rockchip_combphy_driver); 1456 1457 MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver"); 1458 MODULE_LICENSE("GPL v2"); 1459