1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USB2.0 PHY with Innosilicon IP block driver 4 * 5 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/extcon-provider.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/jiffies.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/of.h> 20 #include <linux/of_irq.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/power_supply.h> 24 #include <linux/regmap.h> 25 #include <linux/reset.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/usb/of.h> 28 #include <linux/usb/otg.h> 29 30 #define BIT_WRITEABLE_SHIFT 16 31 #define SCHEDULE_DELAY (60 * HZ) 32 #define OTG_SCHEDULE_DELAY (2 * HZ) 33 34 struct rockchip_usb2phy; 35 36 enum rockchip_usb2phy_port_id { 37 USB2PHY_PORT_OTG, 38 USB2PHY_PORT_HOST, 39 USB2PHY_NUM_PORTS, 40 }; 41 42 enum rockchip_usb2phy_host_state { 43 PHY_STATE_HS_ONLINE = 0, 44 PHY_STATE_DISCONNECT = 1, 45 PHY_STATE_CONNECT = 2, 46 PHY_STATE_FS_LS_ONLINE = 4, 47 }; 48 49 /** 50 * enum usb_chg_state - Different states involved in USB charger detection. 51 * @USB_CHG_STATE_UNDEFINED: USB charger is not connected or detection 52 * process is not yet started. 53 * @USB_CHG_STATE_WAIT_FOR_DCD: Waiting for Data pins contact. 54 * @USB_CHG_STATE_DCD_DONE: Data pin contact is detected. 55 * @USB_CHG_STATE_PRIMARY_DONE: Primary detection is completed (Detects 56 * between SDP and DCP/CDP). 57 * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects 58 * between DCP and CDP). 59 * @USB_CHG_STATE_DETECTED: USB charger type is determined. 60 */ 61 enum usb_chg_state { 62 USB_CHG_STATE_UNDEFINED = 0, 63 USB_CHG_STATE_WAIT_FOR_DCD, 64 USB_CHG_STATE_DCD_DONE, 65 USB_CHG_STATE_PRIMARY_DONE, 66 USB_CHG_STATE_SECONDARY_DONE, 67 USB_CHG_STATE_DETECTED, 68 }; 69 70 static const unsigned int rockchip_usb2phy_extcon_cable[] = { 71 EXTCON_USB, 72 EXTCON_USB_HOST, 73 EXTCON_CHG_USB_SDP, 74 EXTCON_CHG_USB_CDP, 75 EXTCON_CHG_USB_DCP, 76 EXTCON_CHG_USB_SLOW, 77 EXTCON_NONE, 78 }; 79 80 struct usb2phy_reg { 81 unsigned int offset; 82 unsigned int bitend; 83 unsigned int bitstart; 84 unsigned int disable; 85 unsigned int enable; 86 }; 87 88 /** 89 * struct rockchip_chg_det_reg - usb charger detect registers 90 * @cp_det: charging port detected successfully. 91 * @dcp_det: dedicated charging port detected successfully. 92 * @dp_det: assert data pin connect successfully. 93 * @idm_sink_en: open dm sink curren. 94 * @idp_sink_en: open dp sink current. 95 * @idp_src_en: open dm source current. 96 * @rdm_pdwn_en: open dm pull down resistor. 97 * @vdm_src_en: open dm voltage source. 98 * @vdp_src_en: open dp voltage source. 99 * @opmode: utmi operational mode. 100 */ 101 struct rockchip_chg_det_reg { 102 struct usb2phy_reg cp_det; 103 struct usb2phy_reg dcp_det; 104 struct usb2phy_reg dp_det; 105 struct usb2phy_reg idm_sink_en; 106 struct usb2phy_reg idp_sink_en; 107 struct usb2phy_reg idp_src_en; 108 struct usb2phy_reg rdm_pdwn_en; 109 struct usb2phy_reg vdm_src_en; 110 struct usb2phy_reg vdp_src_en; 111 struct usb2phy_reg opmode; 112 }; 113 114 /** 115 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration. 116 * @phy_sus: phy suspend register. 117 * @bvalid_det_en: vbus valid rise detection enable register. 118 * @bvalid_det_st: vbus valid rise detection status register. 119 * @bvalid_det_clr: vbus valid rise detection clear register. 120 * @disfall_en: host disconnect fall edge detection enable. 121 * @disfall_st: host disconnect fall edge detection state. 122 * @disfall_clr: host disconnect fall edge detection clear. 123 * @disrise_en: host disconnect rise edge detection enable. 124 * @disrise_st: host disconnect rise edge detection state. 125 * @disrise_clr: host disconnect rise edge detection clear. 126 * @id_det_en: id detection enable register. 127 * @id_det_st: id detection state register. 128 * @id_det_clr: id detection clear register. 129 * @ls_det_en: linestate detection enable register. 130 * @ls_det_st: linestate detection state register. 131 * @ls_det_clr: linestate detection clear register. 132 * @utmi_avalid: utmi vbus avalid status register. 133 * @utmi_bvalid: utmi vbus bvalid status register. 134 * @utmi_id: utmi id state register. 135 * @utmi_ls: utmi linestate state register. 136 * @utmi_hstdet: utmi host disconnect register. 137 */ 138 struct rockchip_usb2phy_port_cfg { 139 struct usb2phy_reg phy_sus; 140 struct usb2phy_reg bvalid_det_en; 141 struct usb2phy_reg bvalid_det_st; 142 struct usb2phy_reg bvalid_det_clr; 143 struct usb2phy_reg disfall_en; 144 struct usb2phy_reg disfall_st; 145 struct usb2phy_reg disfall_clr; 146 struct usb2phy_reg disrise_en; 147 struct usb2phy_reg disrise_st; 148 struct usb2phy_reg disrise_clr; 149 struct usb2phy_reg id_det_en; 150 struct usb2phy_reg id_det_st; 151 struct usb2phy_reg id_det_clr; 152 struct usb2phy_reg ls_det_en; 153 struct usb2phy_reg ls_det_st; 154 struct usb2phy_reg ls_det_clr; 155 struct usb2phy_reg utmi_avalid; 156 struct usb2phy_reg utmi_bvalid; 157 struct usb2phy_reg utmi_id; 158 struct usb2phy_reg utmi_ls; 159 struct usb2phy_reg utmi_hstdet; 160 }; 161 162 /** 163 * struct rockchip_usb2phy_cfg - usb-phy configuration. 164 * @reg: the address offset of grf for usb-phy config. 165 * @num_ports: specify how many ports that the phy has. 166 * @phy_tuning: phy default parameters tuning. 167 * @clkout_ctl: keep on/turn off output clk of phy. 168 * @port_cfgs: usb-phy port configurations. 169 * @chg_det: charger detection registers. 170 */ 171 struct rockchip_usb2phy_cfg { 172 unsigned int reg; 173 unsigned int num_ports; 174 int (*phy_tuning)(struct rockchip_usb2phy *rphy); 175 struct usb2phy_reg clkout_ctl; 176 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 177 const struct rockchip_chg_det_reg chg_det; 178 }; 179 180 /** 181 * struct rockchip_usb2phy_port - usb-phy port data. 182 * @phy: generic phy. 183 * @port_id: flag for otg port or host port. 184 * @suspended: phy suspended flag. 185 * @vbus_attached: otg device vbus status. 186 * @host_disconnect: usb host disconnect status. 187 * @bvalid_irq: IRQ number assigned for vbus valid rise detection. 188 * @id_irq: IRQ number assigned for ID pin detection. 189 * @ls_irq: IRQ number assigned for linestate detection. 190 * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate 191 * irqs to one irq in otg-port. 192 * @mutex: for register updating in sm_work. 193 * @chg_work: charge detect work. 194 * @otg_sm_work: OTG state machine work. 195 * @sm_work: HOST state machine work. 196 * @port_cfg: port register configuration, assigned by driver data. 197 * @event_nb: hold event notification callback. 198 * @state: define OTG enumeration states before device reset. 199 * @mode: the dr_mode of the controller. 200 */ 201 struct rockchip_usb2phy_port { 202 struct phy *phy; 203 unsigned int port_id; 204 bool suspended; 205 bool vbus_attached; 206 bool host_disconnect; 207 int bvalid_irq; 208 int id_irq; 209 int ls_irq; 210 int otg_mux_irq; 211 struct mutex mutex; 212 struct delayed_work chg_work; 213 struct delayed_work otg_sm_work; 214 struct delayed_work sm_work; 215 const struct rockchip_usb2phy_port_cfg *port_cfg; 216 struct notifier_block event_nb; 217 enum usb_otg_state state; 218 enum usb_dr_mode mode; 219 }; 220 221 /** 222 * struct rockchip_usb2phy - usb2.0 phy driver data. 223 * @dev: pointer to device. 224 * @grf: General Register Files regmap. 225 * @usbgrf: USB General Register Files regmap. 226 * @clk: clock struct of phy input clk. 227 * @clk480m: clock struct of phy output clk. 228 * @clk480m_hw: clock struct of phy output clk management. 229 * @phy_reset: phy reset control. 230 * @chg_state: states involved in USB charger detection. 231 * @chg_type: USB charger types. 232 * @dcd_retries: The retry count used to track Data contact 233 * detection process. 234 * @edev: extcon device for notification registration 235 * @irq: muxed interrupt for single irq configuration 236 * @phy_cfg: phy register configuration, assigned by driver data. 237 * @ports: phy port instance. 238 */ 239 struct rockchip_usb2phy { 240 struct device *dev; 241 struct regmap *grf; 242 struct regmap *usbgrf; 243 struct clk *clk; 244 struct clk *clk480m; 245 struct clk_hw clk480m_hw; 246 struct reset_control *phy_reset; 247 enum usb_chg_state chg_state; 248 enum power_supply_type chg_type; 249 u8 dcd_retries; 250 struct extcon_dev *edev; 251 int irq; 252 const struct rockchip_usb2phy_cfg *phy_cfg; 253 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS]; 254 }; 255 256 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 257 { 258 return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf; 259 } 260 261 static inline int property_enable(struct regmap *base, 262 const struct usb2phy_reg *reg, bool en) 263 { 264 unsigned int val, mask, tmp; 265 266 tmp = en ? reg->enable : reg->disable; 267 mask = GENMASK(reg->bitend, reg->bitstart); 268 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 269 270 return regmap_write(base, reg->offset, val); 271 } 272 273 static inline bool property_enabled(struct regmap *base, 274 const struct usb2phy_reg *reg) 275 { 276 int ret; 277 unsigned int tmp, orig; 278 unsigned int mask = GENMASK(reg->bitend, reg->bitstart); 279 280 ret = regmap_read(base, reg->offset, &orig); 281 if (ret) 282 return false; 283 284 tmp = (orig & mask) >> reg->bitstart; 285 return tmp != reg->disable; 286 } 287 288 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy) 289 { 290 int ret; 291 292 ret = reset_control_assert(rphy->phy_reset); 293 if (ret) 294 return ret; 295 296 udelay(10); 297 298 ret = reset_control_deassert(rphy->phy_reset); 299 if (ret) 300 return ret; 301 302 usleep_range(100, 200); 303 304 return 0; 305 } 306 307 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) 308 { 309 struct rockchip_usb2phy *rphy = 310 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 311 struct regmap *base = get_reg_base(rphy); 312 int ret; 313 314 /* turn on 480m clk output if it is off */ 315 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) { 316 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true); 317 if (ret) 318 return ret; 319 320 /* waiting for the clk become stable */ 321 usleep_range(1200, 1300); 322 } 323 324 return 0; 325 } 326 327 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw) 328 { 329 struct rockchip_usb2phy *rphy = 330 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 331 struct regmap *base = get_reg_base(rphy); 332 333 /* turn off 480m clk output */ 334 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 335 } 336 337 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw) 338 { 339 struct rockchip_usb2phy *rphy = 340 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 341 struct regmap *base = get_reg_base(rphy); 342 343 return property_enabled(base, &rphy->phy_cfg->clkout_ctl); 344 } 345 346 static unsigned long 347 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw, 348 unsigned long parent_rate) 349 { 350 return 480000000; 351 } 352 353 static const struct clk_ops rockchip_usb2phy_clkout_ops = { 354 .prepare = rockchip_usb2phy_clk480m_prepare, 355 .unprepare = rockchip_usb2phy_clk480m_unprepare, 356 .is_prepared = rockchip_usb2phy_clk480m_prepared, 357 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate, 358 }; 359 360 static void rockchip_usb2phy_clk480m_unregister(void *data) 361 { 362 struct rockchip_usb2phy *rphy = data; 363 364 of_clk_del_provider(rphy->dev->of_node); 365 clk_unregister(rphy->clk480m); 366 } 367 368 static int 369 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy) 370 { 371 struct device_node *node = rphy->dev->of_node; 372 struct clk_init_data init; 373 const char *clk_name; 374 int ret = 0; 375 376 init.flags = 0; 377 init.name = "clk_usbphy_480m"; 378 init.ops = &rockchip_usb2phy_clkout_ops; 379 380 /* optional override of the clockname */ 381 of_property_read_string(node, "clock-output-names", &init.name); 382 383 if (rphy->clk) { 384 clk_name = __clk_get_name(rphy->clk); 385 init.parent_names = &clk_name; 386 init.num_parents = 1; 387 } else { 388 init.parent_names = NULL; 389 init.num_parents = 0; 390 } 391 392 rphy->clk480m_hw.init = &init; 393 394 /* register the clock */ 395 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw); 396 if (IS_ERR(rphy->clk480m)) { 397 ret = PTR_ERR(rphy->clk480m); 398 goto err_ret; 399 } 400 401 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m); 402 if (ret < 0) 403 goto err_clk_provider; 404 405 return devm_add_action_or_reset(rphy->dev, rockchip_usb2phy_clk480m_unregister, rphy); 406 407 err_clk_provider: 408 clk_unregister(rphy->clk480m); 409 err_ret: 410 return ret; 411 } 412 413 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy) 414 { 415 int ret; 416 struct device_node *node = rphy->dev->of_node; 417 struct extcon_dev *edev; 418 419 if (of_property_read_bool(node, "extcon")) { 420 edev = extcon_get_edev_by_phandle(rphy->dev, 0); 421 if (IS_ERR(edev)) { 422 if (PTR_ERR(edev) != -EPROBE_DEFER) 423 dev_err(rphy->dev, "Invalid or missing extcon\n"); 424 return PTR_ERR(edev); 425 } 426 } else { 427 /* Initialize extcon device */ 428 edev = devm_extcon_dev_allocate(rphy->dev, 429 rockchip_usb2phy_extcon_cable); 430 431 if (IS_ERR(edev)) 432 return -ENOMEM; 433 434 ret = devm_extcon_dev_register(rphy->dev, edev); 435 if (ret) { 436 dev_err(rphy->dev, "failed to register extcon device\n"); 437 return ret; 438 } 439 } 440 441 rphy->edev = edev; 442 443 return 0; 444 } 445 446 static int rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy *rphy, 447 struct rockchip_usb2phy_port *rport, 448 bool en) 449 { 450 int ret; 451 452 ret = property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true); 453 if (ret) 454 return ret; 455 456 ret = property_enable(rphy->grf, &rport->port_cfg->disfall_en, en); 457 if (ret) 458 return ret; 459 460 ret = property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true); 461 if (ret) 462 return ret; 463 464 return property_enable(rphy->grf, &rport->port_cfg->disrise_en, en); 465 } 466 467 static int rockchip_usb2phy_init(struct phy *phy) 468 { 469 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 470 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 471 int ret = 0; 472 473 mutex_lock(&rport->mutex); 474 475 if (rport->port_id == USB2PHY_PORT_OTG) { 476 if (rport->mode != USB_DR_MODE_HOST && 477 rport->mode != USB_DR_MODE_UNKNOWN) { 478 /* clear bvalid status and enable bvalid detect irq */ 479 ret = property_enable(rphy->grf, 480 &rport->port_cfg->bvalid_det_clr, 481 true); 482 if (ret) 483 goto out; 484 485 ret = property_enable(rphy->grf, 486 &rport->port_cfg->bvalid_det_en, 487 true); 488 if (ret) 489 goto out; 490 491 /* clear id status and enable id detect irq */ 492 ret = property_enable(rphy->grf, 493 &rport->port_cfg->id_det_clr, 494 true); 495 if (ret) 496 goto out; 497 498 ret = property_enable(rphy->grf, 499 &rport->port_cfg->id_det_en, 500 true); 501 if (ret) 502 goto out; 503 504 schedule_delayed_work(&rport->otg_sm_work, 505 OTG_SCHEDULE_DELAY * 3); 506 } else { 507 /* If OTG works in host only mode, do nothing. */ 508 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode); 509 } 510 } else if (rport->port_id == USB2PHY_PORT_HOST) { 511 if (rport->port_cfg->disfall_en.offset) { 512 rport->host_disconnect = true; 513 ret = rockchip_usb2phy_enable_host_disc_irq(rphy, rport, true); 514 if (ret) { 515 dev_err(rphy->dev, "failed to enable disconnect irq\n"); 516 goto out; 517 } 518 } 519 520 /* clear linestate and enable linestate detect irq */ 521 ret = property_enable(rphy->grf, 522 &rport->port_cfg->ls_det_clr, true); 523 if (ret) 524 goto out; 525 526 ret = property_enable(rphy->grf, 527 &rport->port_cfg->ls_det_en, true); 528 if (ret) 529 goto out; 530 531 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY); 532 } 533 534 out: 535 mutex_unlock(&rport->mutex); 536 return ret; 537 } 538 539 static int rockchip_usb2phy_power_on(struct phy *phy) 540 { 541 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 542 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 543 struct regmap *base = get_reg_base(rphy); 544 int ret; 545 546 dev_dbg(&rport->phy->dev, "port power on\n"); 547 548 if (!rport->suspended) 549 return 0; 550 551 ret = clk_prepare_enable(rphy->clk480m); 552 if (ret) 553 return ret; 554 555 ret = property_enable(base, &rport->port_cfg->phy_sus, false); 556 if (ret) { 557 clk_disable_unprepare(rphy->clk480m); 558 return ret; 559 } 560 561 /* 562 * For rk3588, it needs to reset phy when exit from 563 * suspend mode with common_on_n 1'b1(aka REFCLK_LOGIC, 564 * Bias, and PLL blocks are powered down) for lower 565 * power consumption. If you don't want to reset phy, 566 * please keep the common_on_n 1'b0 to set these blocks 567 * remain powered. 568 */ 569 ret = rockchip_usb2phy_reset(rphy); 570 if (ret) 571 return ret; 572 573 /* waiting for the utmi_clk to become stable */ 574 usleep_range(1500, 2000); 575 576 rport->suspended = false; 577 return 0; 578 } 579 580 static int rockchip_usb2phy_power_off(struct phy *phy) 581 { 582 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 583 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 584 struct regmap *base = get_reg_base(rphy); 585 int ret; 586 587 dev_dbg(&rport->phy->dev, "port power off\n"); 588 589 if (rport->suspended) 590 return 0; 591 592 ret = property_enable(base, &rport->port_cfg->phy_sus, true); 593 if (ret) 594 return ret; 595 596 rport->suspended = true; 597 clk_disable_unprepare(rphy->clk480m); 598 599 return 0; 600 } 601 602 static int rockchip_usb2phy_exit(struct phy *phy) 603 { 604 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 605 606 if (rport->port_id == USB2PHY_PORT_OTG && 607 rport->mode != USB_DR_MODE_HOST && 608 rport->mode != USB_DR_MODE_UNKNOWN) { 609 cancel_delayed_work_sync(&rport->otg_sm_work); 610 cancel_delayed_work_sync(&rport->chg_work); 611 } else if (rport->port_id == USB2PHY_PORT_HOST) 612 cancel_delayed_work_sync(&rport->sm_work); 613 614 return 0; 615 } 616 617 static const struct phy_ops rockchip_usb2phy_ops = { 618 .init = rockchip_usb2phy_init, 619 .exit = rockchip_usb2phy_exit, 620 .power_on = rockchip_usb2phy_power_on, 621 .power_off = rockchip_usb2phy_power_off, 622 .owner = THIS_MODULE, 623 }; 624 625 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) 626 { 627 struct rockchip_usb2phy_port *rport = 628 container_of(work, struct rockchip_usb2phy_port, 629 otg_sm_work.work); 630 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 631 static unsigned int cable; 632 unsigned long delay; 633 bool vbus_attach, sch_work, notify_charger; 634 635 vbus_attach = property_enabled(rphy->grf, 636 &rport->port_cfg->utmi_bvalid); 637 638 sch_work = false; 639 notify_charger = false; 640 delay = OTG_SCHEDULE_DELAY; 641 dev_dbg(&rport->phy->dev, "%s otg sm work\n", 642 usb_otg_state_string(rport->state)); 643 644 switch (rport->state) { 645 case OTG_STATE_UNDEFINED: 646 rport->state = OTG_STATE_B_IDLE; 647 if (!vbus_attach) 648 rockchip_usb2phy_power_off(rport->phy); 649 fallthrough; 650 case OTG_STATE_B_IDLE: 651 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) { 652 dev_dbg(&rport->phy->dev, "usb otg host connect\n"); 653 rport->state = OTG_STATE_A_HOST; 654 rockchip_usb2phy_power_on(rport->phy); 655 return; 656 } else if (vbus_attach) { 657 dev_dbg(&rport->phy->dev, "vbus_attach\n"); 658 switch (rphy->chg_state) { 659 case USB_CHG_STATE_UNDEFINED: 660 schedule_delayed_work(&rport->chg_work, 0); 661 return; 662 case USB_CHG_STATE_DETECTED: 663 switch (rphy->chg_type) { 664 case POWER_SUPPLY_TYPE_USB: 665 dev_dbg(&rport->phy->dev, "sdp cable is connected\n"); 666 rockchip_usb2phy_power_on(rport->phy); 667 rport->state = OTG_STATE_B_PERIPHERAL; 668 notify_charger = true; 669 sch_work = true; 670 cable = EXTCON_CHG_USB_SDP; 671 break; 672 case POWER_SUPPLY_TYPE_USB_DCP: 673 dev_dbg(&rport->phy->dev, "dcp cable is connected\n"); 674 rockchip_usb2phy_power_off(rport->phy); 675 notify_charger = true; 676 sch_work = true; 677 cable = EXTCON_CHG_USB_DCP; 678 break; 679 case POWER_SUPPLY_TYPE_USB_CDP: 680 dev_dbg(&rport->phy->dev, "cdp cable is connected\n"); 681 rockchip_usb2phy_power_on(rport->phy); 682 rport->state = OTG_STATE_B_PERIPHERAL; 683 notify_charger = true; 684 sch_work = true; 685 cable = EXTCON_CHG_USB_CDP; 686 break; 687 default: 688 break; 689 } 690 break; 691 default: 692 break; 693 } 694 } else { 695 notify_charger = true; 696 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 697 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 698 } 699 700 if (rport->vbus_attached != vbus_attach) { 701 rport->vbus_attached = vbus_attach; 702 703 if (notify_charger && rphy->edev) { 704 extcon_set_state_sync(rphy->edev, 705 cable, vbus_attach); 706 if (cable == EXTCON_CHG_USB_SDP) 707 extcon_set_state_sync(rphy->edev, 708 EXTCON_USB, 709 vbus_attach); 710 } 711 } 712 break; 713 case OTG_STATE_B_PERIPHERAL: 714 if (!vbus_attach) { 715 dev_dbg(&rport->phy->dev, "usb disconnect\n"); 716 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 717 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 718 rport->state = OTG_STATE_B_IDLE; 719 delay = 0; 720 rockchip_usb2phy_power_off(rport->phy); 721 } 722 sch_work = true; 723 break; 724 case OTG_STATE_A_HOST: 725 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) { 726 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n"); 727 rport->state = OTG_STATE_B_IDLE; 728 rockchip_usb2phy_power_off(rport->phy); 729 } 730 break; 731 default: 732 break; 733 } 734 735 if (sch_work) 736 schedule_delayed_work(&rport->otg_sm_work, delay); 737 } 738 739 static const char *chg_to_string(enum power_supply_type chg_type) 740 { 741 switch (chg_type) { 742 case POWER_SUPPLY_TYPE_USB: 743 return "USB_SDP_CHARGER"; 744 case POWER_SUPPLY_TYPE_USB_DCP: 745 return "USB_DCP_CHARGER"; 746 case POWER_SUPPLY_TYPE_USB_CDP: 747 return "USB_CDP_CHARGER"; 748 default: 749 return "INVALID_CHARGER"; 750 } 751 } 752 753 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 754 bool en) 755 { 756 struct regmap *base = get_reg_base(rphy); 757 758 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 759 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 760 } 761 762 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 763 bool en) 764 { 765 struct regmap *base = get_reg_base(rphy); 766 767 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 768 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 769 } 770 771 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 772 bool en) 773 { 774 struct regmap *base = get_reg_base(rphy); 775 776 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 777 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 778 } 779 780 #define CHG_DCD_POLL_TIME (100 * HZ / 1000) 781 #define CHG_DCD_MAX_RETRIES 6 782 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000) 783 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000) 784 static void rockchip_chg_detect_work(struct work_struct *work) 785 { 786 struct rockchip_usb2phy_port *rport = 787 container_of(work, struct rockchip_usb2phy_port, chg_work.work); 788 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 789 struct regmap *base = get_reg_base(rphy); 790 bool is_dcd, tmout, vout; 791 unsigned long delay; 792 793 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n", 794 rphy->chg_state); 795 switch (rphy->chg_state) { 796 case USB_CHG_STATE_UNDEFINED: 797 if (!rport->suspended) 798 rockchip_usb2phy_power_off(rport->phy); 799 /* put the controller in non-driving mode */ 800 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 801 /* Start DCD processing stage 1 */ 802 rockchip_chg_enable_dcd(rphy, true); 803 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; 804 rphy->dcd_retries = 0; 805 delay = CHG_DCD_POLL_TIME; 806 break; 807 case USB_CHG_STATE_WAIT_FOR_DCD: 808 /* get data contact detection status */ 809 is_dcd = property_enabled(rphy->grf, 810 &rphy->phy_cfg->chg_det.dp_det); 811 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES; 812 /* stage 2 */ 813 if (is_dcd || tmout) { 814 /* stage 4 */ 815 /* Turn off DCD circuitry */ 816 rockchip_chg_enable_dcd(rphy, false); 817 /* Voltage Source on DP, Probe on DM */ 818 rockchip_chg_enable_primary_det(rphy, true); 819 delay = CHG_PRIMARY_DET_TIME; 820 rphy->chg_state = USB_CHG_STATE_DCD_DONE; 821 } else { 822 /* stage 3 */ 823 delay = CHG_DCD_POLL_TIME; 824 } 825 break; 826 case USB_CHG_STATE_DCD_DONE: 827 vout = property_enabled(rphy->grf, 828 &rphy->phy_cfg->chg_det.cp_det); 829 rockchip_chg_enable_primary_det(rphy, false); 830 if (vout) { 831 /* Voltage Source on DM, Probe on DP */ 832 rockchip_chg_enable_secondary_det(rphy, true); 833 delay = CHG_SECONDARY_DET_TIME; 834 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE; 835 } else { 836 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) { 837 /* floating charger found */ 838 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP; 839 rphy->chg_state = USB_CHG_STATE_DETECTED; 840 delay = 0; 841 } else { 842 rphy->chg_type = POWER_SUPPLY_TYPE_USB; 843 rphy->chg_state = USB_CHG_STATE_DETECTED; 844 delay = 0; 845 } 846 } 847 break; 848 case USB_CHG_STATE_PRIMARY_DONE: 849 vout = property_enabled(rphy->grf, 850 &rphy->phy_cfg->chg_det.dcp_det); 851 /* Turn off voltage source */ 852 rockchip_chg_enable_secondary_det(rphy, false); 853 if (vout) 854 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP; 855 else 856 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP; 857 fallthrough; 858 case USB_CHG_STATE_SECONDARY_DONE: 859 rphy->chg_state = USB_CHG_STATE_DETECTED; 860 fallthrough; 861 case USB_CHG_STATE_DETECTED: 862 /* put the controller in normal mode */ 863 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 864 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); 865 dev_dbg(&rport->phy->dev, "charger = %s\n", 866 chg_to_string(rphy->chg_type)); 867 return; 868 default: 869 return; 870 } 871 872 schedule_delayed_work(&rport->chg_work, delay); 873 } 874 875 /* 876 * The function manage host-phy port state and suspend/resume phy port 877 * to save power. 878 * 879 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether 880 * devices is disconnect or not. Besides, we do not need care it is FS/LS 881 * disconnected or HS disconnected, actually, we just only need get the 882 * device is disconnected at last through rearm the delayed work, 883 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case. 884 * 885 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke 886 * some clk related APIs, so do not invoke it from interrupt context directly. 887 */ 888 static void rockchip_usb2phy_sm_work(struct work_struct *work) 889 { 890 struct rockchip_usb2phy_port *rport = 891 container_of(work, struct rockchip_usb2phy_port, sm_work.work); 892 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 893 unsigned int sh, ul, uhd, state; 894 unsigned int ul_mask, uhd_mask; 895 int ret; 896 897 mutex_lock(&rport->mutex); 898 899 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul); 900 if (ret < 0) 901 goto next_schedule; 902 903 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend, 904 rport->port_cfg->utmi_ls.bitstart); 905 906 if (rport->port_cfg->utmi_hstdet.offset) { 907 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd); 908 if (ret < 0) 909 goto next_schedule; 910 911 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend, 912 rport->port_cfg->utmi_hstdet.bitstart); 913 914 sh = rport->port_cfg->utmi_hstdet.bitend - 915 rport->port_cfg->utmi_hstdet.bitstart + 1; 916 /* stitch on utmi_ls and utmi_hstdet as phy state */ 917 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) | 918 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh); 919 } else { 920 state = ((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << 1 | 921 rport->host_disconnect; 922 } 923 924 switch (state) { 925 case PHY_STATE_HS_ONLINE: 926 dev_dbg(&rport->phy->dev, "HS online\n"); 927 break; 928 case PHY_STATE_FS_LS_ONLINE: 929 /* 930 * For FS/LS device, the online state share with connect state 931 * from utmi_ls and utmi_hstdet register, so we distinguish 932 * them via suspended flag. 933 * 934 * Plus, there are two cases, one is D- Line pull-up, and D+ 935 * line pull-down, the state is 4; another is D+ line pull-up, 936 * and D- line pull-down, the state is 2. 937 */ 938 if (!rport->suspended) { 939 /* D- line pull-up, D+ line pull-down */ 940 dev_dbg(&rport->phy->dev, "FS/LS online\n"); 941 break; 942 } 943 fallthrough; 944 case PHY_STATE_CONNECT: 945 if (rport->suspended) { 946 dev_dbg(&rport->phy->dev, "Connected\n"); 947 rockchip_usb2phy_power_on(rport->phy); 948 rport->suspended = false; 949 } else { 950 /* D+ line pull-up, D- line pull-down */ 951 dev_dbg(&rport->phy->dev, "FS/LS online\n"); 952 } 953 break; 954 case PHY_STATE_DISCONNECT: 955 if (!rport->suspended) { 956 dev_dbg(&rport->phy->dev, "Disconnected\n"); 957 rockchip_usb2phy_power_off(rport->phy); 958 rport->suspended = true; 959 } 960 961 /* 962 * activate the linestate detection to get the next device 963 * plug-in irq. 964 */ 965 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true); 966 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true); 967 968 /* 969 * we don't need to rearm the delayed work when the phy port 970 * is suspended. 971 */ 972 mutex_unlock(&rport->mutex); 973 return; 974 default: 975 dev_dbg(&rport->phy->dev, "unknown phy state\n"); 976 break; 977 } 978 979 next_schedule: 980 mutex_unlock(&rport->mutex); 981 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY); 982 } 983 984 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data) 985 { 986 struct rockchip_usb2phy_port *rport = data; 987 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 988 989 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st)) 990 return IRQ_NONE; 991 992 mutex_lock(&rport->mutex); 993 994 /* disable linestate detect irq and clear its status */ 995 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false); 996 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true); 997 998 mutex_unlock(&rport->mutex); 999 1000 /* 1001 * In this case for host phy port, a new device is plugged in, 1002 * meanwhile, if the phy port is suspended, we need rearm the work to 1003 * resume it and mange its states; otherwise, we do nothing about that. 1004 */ 1005 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST) 1006 rockchip_usb2phy_sm_work(&rport->sm_work.work); 1007 1008 return IRQ_HANDLED; 1009 } 1010 1011 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data) 1012 { 1013 struct rockchip_usb2phy_port *rport = data; 1014 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 1015 1016 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) 1017 return IRQ_NONE; 1018 1019 /* clear bvalid detect irq pending status */ 1020 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true); 1021 1022 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); 1023 1024 return IRQ_HANDLED; 1025 } 1026 1027 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data) 1028 { 1029 struct rockchip_usb2phy_port *rport = data; 1030 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 1031 bool id; 1032 1033 if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st)) 1034 return IRQ_NONE; 1035 1036 /* clear id detect irq pending status */ 1037 property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true); 1038 1039 id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); 1040 extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id); 1041 1042 return IRQ_HANDLED; 1043 } 1044 1045 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data) 1046 { 1047 irqreturn_t ret = IRQ_NONE; 1048 1049 ret |= rockchip_usb2phy_bvalid_irq(irq, data); 1050 ret |= rockchip_usb2phy_id_irq(irq, data); 1051 1052 return ret; 1053 } 1054 1055 static irqreturn_t rockchip_usb2phy_host_disc_irq(int irq, void *data) 1056 { 1057 struct rockchip_usb2phy_port *rport = data; 1058 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 1059 1060 if (!property_enabled(rphy->grf, &rport->port_cfg->disfall_st) && 1061 !property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) 1062 return IRQ_NONE; 1063 1064 mutex_lock(&rport->mutex); 1065 1066 /* clear disconnect fall or rise detect irq pending status */ 1067 if (property_enabled(rphy->grf, &rport->port_cfg->disfall_st)) { 1068 property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true); 1069 rport->host_disconnect = false; 1070 } else if (property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) { 1071 property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true); 1072 rport->host_disconnect = true; 1073 } 1074 1075 mutex_unlock(&rport->mutex); 1076 1077 return IRQ_HANDLED; 1078 } 1079 1080 static irqreturn_t rockchip_usb2phy_irq(int irq, void *data) 1081 { 1082 struct rockchip_usb2phy *rphy = data; 1083 struct rockchip_usb2phy_port *rport; 1084 irqreturn_t ret = IRQ_NONE; 1085 unsigned int index; 1086 1087 for (index = 0; index < rphy->phy_cfg->num_ports; index++) { 1088 rport = &rphy->ports[index]; 1089 if (!rport->phy) 1090 continue; 1091 1092 if (rport->port_id == USB2PHY_PORT_HOST && 1093 rport->port_cfg->disfall_en.offset) 1094 ret |= rockchip_usb2phy_host_disc_irq(irq, rport); 1095 1096 switch (rport->port_id) { 1097 case USB2PHY_PORT_OTG: 1098 if (rport->mode != USB_DR_MODE_HOST && 1099 rport->mode != USB_DR_MODE_UNKNOWN) 1100 ret |= rockchip_usb2phy_otg_mux_irq(irq, rport); 1101 break; 1102 case USB2PHY_PORT_HOST: 1103 ret |= rockchip_usb2phy_linestate_irq(irq, rport); 1104 break; 1105 } 1106 } 1107 1108 return ret; 1109 } 1110 1111 static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy, 1112 struct rockchip_usb2phy_port *rport, 1113 struct device_node *child_np) 1114 { 1115 int ret; 1116 1117 /* 1118 * If the usb2 phy used combined irq for otg and host port, 1119 * don't need to init otg and host port irq separately. 1120 */ 1121 if (rphy->irq > 0) 1122 return 0; 1123 1124 switch (rport->port_id) { 1125 case USB2PHY_PORT_HOST: 1126 rport->ls_irq = of_irq_get_byname(child_np, "linestate"); 1127 if (rport->ls_irq < 0) { 1128 dev_err(rphy->dev, "no linestate irq provided\n"); 1129 return rport->ls_irq; 1130 } 1131 1132 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, 1133 rockchip_usb2phy_linestate_irq, 1134 IRQF_ONESHOT, 1135 "rockchip_usb2phy", rport); 1136 if (ret) { 1137 dev_err(rphy->dev, "failed to request linestate irq handle\n"); 1138 return ret; 1139 } 1140 break; 1141 case USB2PHY_PORT_OTG: 1142 /* 1143 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate 1144 * interrupts muxed together, so probe the otg-mux interrupt first, 1145 * if not found, then look for the regular interrupts one by one. 1146 */ 1147 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux"); 1148 if (rport->otg_mux_irq > 0) { 1149 ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, 1150 NULL, 1151 rockchip_usb2phy_otg_mux_irq, 1152 IRQF_ONESHOT, 1153 "rockchip_usb2phy_otg", 1154 rport); 1155 if (ret) { 1156 dev_err(rphy->dev, 1157 "failed to request otg-mux irq handle\n"); 1158 return ret; 1159 } 1160 } else { 1161 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); 1162 if (rport->bvalid_irq < 0) { 1163 dev_err(rphy->dev, "no vbus valid irq provided\n"); 1164 ret = rport->bvalid_irq; 1165 return ret; 1166 } 1167 1168 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, 1169 NULL, 1170 rockchip_usb2phy_bvalid_irq, 1171 IRQF_ONESHOT, 1172 "rockchip_usb2phy_bvalid", 1173 rport); 1174 if (ret) { 1175 dev_err(rphy->dev, 1176 "failed to request otg-bvalid irq handle\n"); 1177 return ret; 1178 } 1179 1180 rport->id_irq = of_irq_get_byname(child_np, "otg-id"); 1181 if (rport->id_irq < 0) { 1182 dev_err(rphy->dev, "no otg-id irq provided\n"); 1183 ret = rport->id_irq; 1184 return ret; 1185 } 1186 1187 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, 1188 NULL, 1189 rockchip_usb2phy_id_irq, 1190 IRQF_ONESHOT, 1191 "rockchip_usb2phy_id", 1192 rport); 1193 if (ret) { 1194 dev_err(rphy->dev, 1195 "failed to request otg-id irq handle\n"); 1196 return ret; 1197 } 1198 } 1199 break; 1200 default: 1201 return -EINVAL; 1202 } 1203 1204 return 0; 1205 } 1206 1207 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, 1208 struct rockchip_usb2phy_port *rport, 1209 struct device_node *child_np) 1210 { 1211 int ret; 1212 1213 rport->port_id = USB2PHY_PORT_HOST; 1214 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 1215 rport->suspended = true; 1216 1217 mutex_init(&rport->mutex); 1218 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work); 1219 1220 ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np); 1221 if (ret) { 1222 dev_err(rphy->dev, "failed to setup host irq\n"); 1223 return ret; 1224 } 1225 1226 return 0; 1227 } 1228 1229 static int rockchip_otg_event(struct notifier_block *nb, 1230 unsigned long event, void *ptr) 1231 { 1232 struct rockchip_usb2phy_port *rport = 1233 container_of(nb, struct rockchip_usb2phy_port, event_nb); 1234 1235 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY); 1236 1237 return NOTIFY_DONE; 1238 } 1239 1240 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, 1241 struct rockchip_usb2phy_port *rport, 1242 struct device_node *child_np) 1243 { 1244 int ret, id; 1245 1246 rport->port_id = USB2PHY_PORT_OTG; 1247 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 1248 rport->state = OTG_STATE_UNDEFINED; 1249 1250 /* 1251 * set suspended flag to true, but actually don't 1252 * put phy in suspend mode, it aims to enable usb 1253 * phy and clock in power_on() called by usb controller 1254 * driver during probe. 1255 */ 1256 rport->suspended = true; 1257 rport->vbus_attached = false; 1258 1259 mutex_init(&rport->mutex); 1260 1261 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1); 1262 if (rport->mode == USB_DR_MODE_HOST || 1263 rport->mode == USB_DR_MODE_UNKNOWN) { 1264 ret = 0; 1265 goto out; 1266 } 1267 1268 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work); 1269 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work); 1270 1271 ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np); 1272 if (ret) { 1273 dev_err(rphy->dev, "failed to init irq for host port\n"); 1274 goto out; 1275 } 1276 1277 if (!IS_ERR(rphy->edev)) { 1278 rport->event_nb.notifier_call = rockchip_otg_event; 1279 1280 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev, 1281 EXTCON_USB_HOST, &rport->event_nb); 1282 if (ret) { 1283 dev_err(rphy->dev, "register USB HOST notifier failed\n"); 1284 goto out; 1285 } 1286 1287 if (!of_property_read_bool(rphy->dev->of_node, "extcon")) { 1288 /* do initial sync of usb state */ 1289 id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id); 1290 extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id); 1291 } 1292 } 1293 1294 out: 1295 return ret; 1296 } 1297 1298 static int rockchip_usb2phy_probe(struct platform_device *pdev) 1299 { 1300 struct device *dev = &pdev->dev; 1301 struct device_node *np = dev->of_node; 1302 struct device_node *child_np; 1303 struct phy_provider *provider; 1304 struct rockchip_usb2phy *rphy; 1305 const struct rockchip_usb2phy_cfg *phy_cfgs; 1306 unsigned int reg; 1307 int index, ret; 1308 1309 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL); 1310 if (!rphy) 1311 return -ENOMEM; 1312 1313 if (!dev->parent || !dev->parent->of_node) { 1314 rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf"); 1315 if (IS_ERR(rphy->grf)) { 1316 dev_err(dev, "failed to locate usbgrf\n"); 1317 return PTR_ERR(rphy->grf); 1318 } 1319 } 1320 1321 else { 1322 rphy->grf = syscon_node_to_regmap(dev->parent->of_node); 1323 if (IS_ERR(rphy->grf)) 1324 return PTR_ERR(rphy->grf); 1325 } 1326 1327 if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) { 1328 rphy->usbgrf = 1329 syscon_regmap_lookup_by_phandle(dev->of_node, 1330 "rockchip,usbgrf"); 1331 if (IS_ERR(rphy->usbgrf)) 1332 return PTR_ERR(rphy->usbgrf); 1333 } else { 1334 rphy->usbgrf = NULL; 1335 } 1336 1337 if (of_property_read_u32_index(np, "reg", 0, ®)) { 1338 dev_err(dev, "the reg property is not assigned in %pOFn node\n", 1339 np); 1340 return -EINVAL; 1341 } 1342 1343 /* support address_cells=2 */ 1344 if (of_property_count_u32_elems(np, "reg") > 2 && reg == 0) { 1345 if (of_property_read_u32_index(np, "reg", 1, ®)) { 1346 dev_err(dev, "the reg property is not assigned in %pOFn node\n", 1347 np); 1348 return -EINVAL; 1349 } 1350 } 1351 1352 rphy->dev = dev; 1353 phy_cfgs = device_get_match_data(dev); 1354 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 1355 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 1356 rphy->irq = platform_get_irq_optional(pdev, 0); 1357 platform_set_drvdata(pdev, rphy); 1358 1359 if (!phy_cfgs) 1360 return dev_err_probe(dev, -EINVAL, "phy configs are not assigned!\n"); 1361 1362 ret = rockchip_usb2phy_extcon_register(rphy); 1363 if (ret) 1364 return ret; 1365 1366 /* find out a proper config which can be matched with dt. */ 1367 index = 0; 1368 do { 1369 if (phy_cfgs[index].reg == reg) { 1370 rphy->phy_cfg = &phy_cfgs[index]; 1371 break; 1372 } 1373 1374 ++index; 1375 } while (phy_cfgs[index].reg); 1376 1377 if (!rphy->phy_cfg) { 1378 dev_err(dev, "could not find phy config for reg=0x%08x\n", reg); 1379 return -EINVAL; 1380 } 1381 1382 rphy->phy_reset = devm_reset_control_get_optional(dev, "phy"); 1383 if (IS_ERR(rphy->phy_reset)) 1384 return PTR_ERR(rphy->phy_reset); 1385 1386 rphy->clk = devm_clk_get_optional_enabled(dev, "phyclk"); 1387 if (IS_ERR(rphy->clk)) { 1388 return dev_err_probe(&pdev->dev, PTR_ERR(rphy->clk), 1389 "failed to get phyclk\n"); 1390 } 1391 1392 ret = rockchip_usb2phy_clk480m_register(rphy); 1393 if (ret) { 1394 dev_err(dev, "failed to register 480m output clock\n"); 1395 return ret; 1396 } 1397 1398 if (rphy->phy_cfg->phy_tuning) { 1399 ret = rphy->phy_cfg->phy_tuning(rphy); 1400 if (ret) 1401 return ret; 1402 } 1403 1404 index = 0; 1405 for_each_available_child_of_node(np, child_np) { 1406 struct rockchip_usb2phy_port *rport = &rphy->ports[index]; 1407 struct phy *phy; 1408 1409 /* This driver aims to support both otg-port and host-port */ 1410 if (!of_node_name_eq(child_np, "host-port") && 1411 !of_node_name_eq(child_np, "otg-port")) 1412 goto next_child; 1413 1414 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops); 1415 if (IS_ERR(phy)) { 1416 dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n"); 1417 ret = PTR_ERR(phy); 1418 goto put_child; 1419 } 1420 1421 rport->phy = phy; 1422 phy_set_drvdata(rport->phy, rport); 1423 1424 /* initialize otg/host port separately */ 1425 if (of_node_name_eq(child_np, "host-port")) { 1426 ret = rockchip_usb2phy_host_port_init(rphy, rport, 1427 child_np); 1428 if (ret) 1429 goto put_child; 1430 } else { 1431 ret = rockchip_usb2phy_otg_port_init(rphy, rport, 1432 child_np); 1433 if (ret) 1434 goto put_child; 1435 } 1436 1437 next_child: 1438 /* to prevent out of boundary */ 1439 if (++index >= rphy->phy_cfg->num_ports) { 1440 of_node_put(child_np); 1441 break; 1442 } 1443 } 1444 1445 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1446 1447 if (rphy->irq > 0) { 1448 ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL, 1449 rockchip_usb2phy_irq, 1450 IRQF_ONESHOT, 1451 "rockchip_usb2phy", 1452 rphy); 1453 if (ret) { 1454 dev_err(rphy->dev, 1455 "failed to request usb2phy irq handle\n"); 1456 goto put_child; 1457 } 1458 } 1459 1460 return PTR_ERR_OR_ZERO(provider); 1461 1462 put_child: 1463 of_node_put(child_np); 1464 return ret; 1465 } 1466 1467 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) 1468 { 1469 int ret; 1470 bool usb3otg = false; 1471 /* 1472 * utmi_termselect = 1'b1 (en FS terminations) 1473 * utmi_xcvrselect = 2'b01 (FS transceiver) 1474 */ 1475 int suspend_cfg = 0x14; 1476 1477 if (rphy->phy_cfg->reg == 0x0000 || rphy->phy_cfg->reg == 0x4000) { 1478 /* USB2 config for USB3_0 and USB3_1 */ 1479 suspend_cfg |= 0x01; /* utmi_opmode = 2'b01 (no-driving) */ 1480 usb3otg = true; 1481 } else if (rphy->phy_cfg->reg == 0x8000 || rphy->phy_cfg->reg == 0xc000) { 1482 /* USB2 config for USB2_0 and USB2_1 */ 1483 suspend_cfg |= 0x00; /* utmi_opmode = 2'b00 (normal) */ 1484 } else { 1485 return -EINVAL; 1486 } 1487 1488 /* Deassert SIDDQ to power on analog block */ 1489 ret = regmap_write(rphy->grf, 0x0008, GENMASK(29, 29) | 0x0000); 1490 if (ret) 1491 return ret; 1492 1493 /* Do reset after exit IDDQ mode */ 1494 ret = rockchip_usb2phy_reset(rphy); 1495 if (ret) 1496 return ret; 1497 1498 /* suspend configuration */ 1499 ret |= regmap_write(rphy->grf, 0x000c, GENMASK(20, 16) | suspend_cfg); 1500 1501 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */ 1502 ret |= regmap_write(rphy->grf, 0x0004, GENMASK(27, 24) | 0x0900); 1503 1504 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ 1505 ret |= regmap_write(rphy->grf, 0x0008, GENMASK(20, 19) | 0x0010); 1506 1507 if (!usb3otg) 1508 return ret; 1509 1510 /* Pullup iddig pin for USB3_0 OTG mode */ 1511 ret |= regmap_write(rphy->grf, 0x0010, GENMASK(17, 16) | 0x0003); 1512 1513 return ret; 1514 } 1515 1516 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = { 1517 { 1518 .reg = 0x760, 1519 .num_ports = 2, 1520 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 1521 .port_cfgs = { 1522 [USB2PHY_PORT_OTG] = { 1523 .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 }, 1524 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1525 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1526 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1527 .id_det_en = { 0x0680, 6, 5, 0, 3 }, 1528 .id_det_st = { 0x0690, 6, 5, 0, 3 }, 1529 .id_det_clr = { 0x06a0, 6, 5, 0, 3 }, 1530 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1531 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1532 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1533 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 1534 .utmi_id = { 0x0480, 1, 1, 0, 1 }, 1535 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 1536 }, 1537 [USB2PHY_PORT_HOST] = { 1538 .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 }, 1539 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1540 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1541 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1542 } 1543 }, 1544 .chg_det = { 1545 .opmode = { 0x0760, 3, 0, 5, 1 }, 1546 .cp_det = { 0x0884, 4, 4, 0, 1 }, 1547 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 1548 .dp_det = { 0x0884, 5, 5, 0, 1 }, 1549 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 1550 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 1551 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 1552 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 1553 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 1554 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 1555 }, 1556 }, 1557 { 1558 .reg = 0x800, 1559 .num_ports = 2, 1560 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1561 .port_cfgs = { 1562 [USB2PHY_PORT_OTG] = { 1563 .phy_sus = { 0x800, 15, 0, 0, 0x1d1 }, 1564 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1565 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1566 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1567 }, 1568 [USB2PHY_PORT_HOST] = { 1569 .phy_sus = { 0x804, 15, 0, 0, 0x1d1 }, 1570 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1571 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1572 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1573 } 1574 }, 1575 }, 1576 { /* sentinel */ } 1577 }; 1578 1579 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 1580 { 1581 .reg = 0x100, 1582 .num_ports = 2, 1583 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1584 .port_cfgs = { 1585 [USB2PHY_PORT_OTG] = { 1586 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1587 .bvalid_det_en = { 0x3020, 3, 2, 0, 3 }, 1588 .bvalid_det_st = { 0x3024, 3, 2, 0, 3 }, 1589 .bvalid_det_clr = { 0x3028, 3, 2, 0, 3 }, 1590 .id_det_en = { 0x3020, 5, 4, 0, 3 }, 1591 .id_det_st = { 0x3024, 5, 4, 0, 3 }, 1592 .id_det_clr = { 0x3028, 5, 4, 0, 3 }, 1593 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1594 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1595 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 1596 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1597 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1598 .utmi_id = { 0x0120, 6, 6, 0, 1 }, 1599 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1600 }, 1601 [USB2PHY_PORT_HOST] = { 1602 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 1603 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 1604 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 1605 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 1606 .utmi_ls = { 0x0120, 17, 16, 0, 1 }, 1607 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 } 1608 } 1609 }, 1610 .chg_det = { 1611 .opmode = { 0x0100, 3, 0, 5, 1 }, 1612 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1613 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1614 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1615 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1616 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1617 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1618 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1619 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1620 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1621 }, 1622 }, 1623 { /* sentinel */ } 1624 }; 1625 1626 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1627 { 1628 .reg = 0x100, 1629 .num_ports = 2, 1630 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1631 .port_cfgs = { 1632 [USB2PHY_PORT_OTG] = { 1633 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, 1634 .bvalid_det_en = { 0x0110, 3, 2, 0, 3 }, 1635 .bvalid_det_st = { 0x0114, 3, 2, 0, 3 }, 1636 .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 }, 1637 .id_det_en = { 0x0110, 5, 4, 0, 3 }, 1638 .id_det_st = { 0x0114, 5, 4, 0, 3 }, 1639 .id_det_clr = { 0x0118, 5, 4, 0, 3 }, 1640 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1641 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1642 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1643 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1644 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1645 .utmi_id = { 0x0120, 6, 6, 0, 1 }, 1646 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1647 }, 1648 [USB2PHY_PORT_HOST] = { 1649 .phy_sus = { 0x104, 15, 0, 0, 0x1d1 }, 1650 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1651 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1652 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1653 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1654 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1655 } 1656 }, 1657 .chg_det = { 1658 .opmode = { 0x0100, 3, 0, 5, 1 }, 1659 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1660 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1661 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1662 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1663 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1664 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1665 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1666 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1667 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1668 }, 1669 }, 1670 { /* sentinel */ } 1671 }; 1672 1673 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = { 1674 { 1675 .reg = 0x700, 1676 .num_ports = 2, 1677 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1678 .port_cfgs = { 1679 [USB2PHY_PORT_HOST] = { 1680 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 }, 1681 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1682 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1683 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1684 .utmi_ls = { 0x049c, 14, 13, 0, 1 }, 1685 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 } 1686 } 1687 }, 1688 }, 1689 { /* sentinel */ } 1690 }; 1691 1692 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1693 { 1694 .reg = 0xe450, 1695 .num_ports = 2, 1696 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1697 .port_cfgs = { 1698 [USB2PHY_PORT_OTG] = { 1699 .phy_sus = { 0xe454, 1, 0, 2, 1 }, 1700 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1701 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1702 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1703 .id_det_en = { 0xe3c0, 5, 4, 0, 3 }, 1704 .id_det_st = { 0xe3e0, 5, 4, 0, 3 }, 1705 .id_det_clr = { 0xe3d0, 5, 4, 0, 3 }, 1706 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1707 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1708 .utmi_id = { 0xe2ac, 8, 8, 0, 1 }, 1709 }, 1710 [USB2PHY_PORT_HOST] = { 1711 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1712 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1713 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1714 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1715 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1716 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1717 } 1718 }, 1719 .chg_det = { 1720 .opmode = { 0xe454, 3, 0, 5, 1 }, 1721 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1722 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1723 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1724 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1725 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1726 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1727 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1728 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1729 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1730 }, 1731 }, 1732 { 1733 .reg = 0xe460, 1734 .num_ports = 2, 1735 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1736 .port_cfgs = { 1737 [USB2PHY_PORT_OTG] = { 1738 .phy_sus = { 0xe464, 1, 0, 2, 1 }, 1739 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1740 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1741 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1742 .id_det_en = { 0xe3c0, 10, 9, 0, 3 }, 1743 .id_det_st = { 0xe3e0, 10, 9, 0, 3 }, 1744 .id_det_clr = { 0xe3d0, 10, 9, 0, 3 }, 1745 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1746 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1747 .utmi_id = { 0xe2ac, 11, 11, 0, 1 }, 1748 }, 1749 [USB2PHY_PORT_HOST] = { 1750 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1751 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1752 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1753 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1754 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1755 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1756 } 1757 }, 1758 }, 1759 { /* sentinel */ } 1760 }; 1761 1762 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { 1763 { 1764 .reg = 0xfe8a0000, 1765 .num_ports = 2, 1766 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1767 .port_cfgs = { 1768 [USB2PHY_PORT_OTG] = { 1769 .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 }, 1770 .bvalid_det_en = { 0x0080, 3, 2, 0, 3 }, 1771 .bvalid_det_st = { 0x0084, 3, 2, 0, 3 }, 1772 .bvalid_det_clr = { 0x0088, 3, 2, 0, 3 }, 1773 .id_det_en = { 0x0080, 5, 4, 0, 3 }, 1774 .id_det_st = { 0x0084, 5, 4, 0, 3 }, 1775 .id_det_clr = { 0x0088, 5, 4, 0, 3 }, 1776 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, 1777 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, 1778 .utmi_id = { 0x00c0, 6, 6, 0, 1 }, 1779 }, 1780 [USB2PHY_PORT_HOST] = { 1781 /* Select suspend control from controller */ 1782 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d2 }, 1783 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1784 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1785 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1786 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1787 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1788 } 1789 }, 1790 .chg_det = { 1791 .opmode = { 0x0000, 3, 0, 5, 1 }, 1792 .cp_det = { 0x00c0, 24, 24, 0, 1 }, 1793 .dcp_det = { 0x00c0, 23, 23, 0, 1 }, 1794 .dp_det = { 0x00c0, 25, 25, 0, 1 }, 1795 .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, 1796 .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, 1797 .idp_src_en = { 0x0008, 9, 9, 0, 1 }, 1798 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, 1799 .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, 1800 .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, 1801 }, 1802 }, 1803 { 1804 .reg = 0xfe8b0000, 1805 .num_ports = 2, 1806 .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, 1807 .port_cfgs = { 1808 [USB2PHY_PORT_OTG] = { 1809 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, 1810 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1811 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1812 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1813 .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, 1814 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } 1815 }, 1816 [USB2PHY_PORT_HOST] = { 1817 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, 1818 .ls_det_en = { 0x0080, 1, 1, 0, 1 }, 1819 .ls_det_st = { 0x0084, 1, 1, 0, 1 }, 1820 .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, 1821 .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, 1822 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } 1823 } 1824 }, 1825 }, 1826 { /* sentinel */ } 1827 }; 1828 1829 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { 1830 { 1831 .reg = 0x0000, 1832 .num_ports = 1, 1833 .phy_tuning = rk3588_usb2phy_tuning, 1834 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1835 .port_cfgs = { 1836 [USB2PHY_PORT_OTG] = { 1837 .phy_sus = { 0x000c, 11, 11, 0, 1 }, 1838 .bvalid_det_en = { 0x0080, 1, 1, 0, 1 }, 1839 .bvalid_det_st = { 0x0084, 1, 1, 0, 1 }, 1840 .bvalid_det_clr = { 0x0088, 1, 1, 0, 1 }, 1841 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1842 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1843 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1844 .disfall_en = { 0x0080, 6, 6, 0, 1 }, 1845 .disfall_st = { 0x0084, 6, 6, 0, 1 }, 1846 .disfall_clr = { 0x0088, 6, 6, 0, 1 }, 1847 .disrise_en = { 0x0080, 5, 5, 0, 1 }, 1848 .disrise_st = { 0x0084, 5, 5, 0, 1 }, 1849 .disrise_clr = { 0x0088, 5, 5, 0, 1 }, 1850 .utmi_avalid = { 0x00c0, 7, 7, 0, 1 }, 1851 .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 }, 1852 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1853 } 1854 }, 1855 .chg_det = { 1856 .cp_det = { 0x00c0, 0, 0, 0, 1 }, 1857 .dcp_det = { 0x00c0, 0, 0, 0, 1 }, 1858 .dp_det = { 0x00c0, 1, 1, 1, 0 }, 1859 .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, 1860 .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, 1861 .idp_src_en = { 0x0008, 14, 14, 0, 1 }, 1862 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, 1863 .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, 1864 .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, 1865 }, 1866 }, 1867 { 1868 .reg = 0x4000, 1869 .num_ports = 1, 1870 .phy_tuning = rk3588_usb2phy_tuning, 1871 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1872 .port_cfgs = { 1873 [USB2PHY_PORT_OTG] = { 1874 .phy_sus = { 0x000c, 11, 11, 0, 1 }, 1875 .bvalid_det_en = { 0x0080, 1, 1, 0, 1 }, 1876 .bvalid_det_st = { 0x0084, 1, 1, 0, 1 }, 1877 .bvalid_det_clr = { 0x0088, 1, 1, 0, 1 }, 1878 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1879 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1880 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1881 .disfall_en = { 0x0080, 6, 6, 0, 1 }, 1882 .disfall_st = { 0x0084, 6, 6, 0, 1 }, 1883 .disfall_clr = { 0x0088, 6, 6, 0, 1 }, 1884 .disrise_en = { 0x0080, 5, 5, 0, 1 }, 1885 .disrise_st = { 0x0084, 5, 5, 0, 1 }, 1886 .disrise_clr = { 0x0088, 5, 5, 0, 1 }, 1887 .utmi_avalid = { 0x00c0, 7, 7, 0, 1 }, 1888 .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 }, 1889 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1890 } 1891 }, 1892 .chg_det = { 1893 .cp_det = { 0x00c0, 0, 0, 0, 1 }, 1894 .dcp_det = { 0x00c0, 0, 0, 0, 1 }, 1895 .dp_det = { 0x00c0, 1, 1, 1, 0 }, 1896 .idm_sink_en = { 0x0008, 5, 5, 1, 0 }, 1897 .idp_sink_en = { 0x0008, 5, 5, 0, 1 }, 1898 .idp_src_en = { 0x0008, 14, 14, 0, 1 }, 1899 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 }, 1900 .vdm_src_en = { 0x0008, 7, 6, 0, 3 }, 1901 .vdp_src_en = { 0x0008, 7, 6, 0, 3 }, 1902 }, 1903 }, 1904 { 1905 .reg = 0x8000, 1906 .num_ports = 1, 1907 .phy_tuning = rk3588_usb2phy_tuning, 1908 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1909 .port_cfgs = { 1910 [USB2PHY_PORT_HOST] = { 1911 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1912 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1913 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1914 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1915 .disfall_en = { 0x0080, 6, 6, 0, 1 }, 1916 .disfall_st = { 0x0084, 6, 6, 0, 1 }, 1917 .disfall_clr = { 0x0088, 6, 6, 0, 1 }, 1918 .disrise_en = { 0x0080, 5, 5, 0, 1 }, 1919 .disrise_st = { 0x0084, 5, 5, 0, 1 }, 1920 .disrise_clr = { 0x0088, 5, 5, 0, 1 }, 1921 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1922 } 1923 }, 1924 }, 1925 { 1926 .reg = 0xc000, 1927 .num_ports = 1, 1928 .phy_tuning = rk3588_usb2phy_tuning, 1929 .clkout_ctl = { 0x0000, 0, 0, 1, 0 }, 1930 .port_cfgs = { 1931 [USB2PHY_PORT_HOST] = { 1932 .phy_sus = { 0x0008, 2, 2, 0, 1 }, 1933 .ls_det_en = { 0x0080, 0, 0, 0, 1 }, 1934 .ls_det_st = { 0x0084, 0, 0, 0, 1 }, 1935 .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, 1936 .disfall_en = { 0x0080, 6, 6, 0, 1 }, 1937 .disfall_st = { 0x0084, 6, 6, 0, 1 }, 1938 .disfall_clr = { 0x0088, 6, 6, 0, 1 }, 1939 .disrise_en = { 0x0080, 5, 5, 0, 1 }, 1940 .disrise_st = { 0x0084, 5, 5, 0, 1 }, 1941 .disrise_clr = { 0x0088, 5, 5, 0, 1 }, 1942 .utmi_ls = { 0x00c0, 10, 9, 0, 1 }, 1943 } 1944 }, 1945 }, 1946 { /* sentinel */ } 1947 }; 1948 1949 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1950 { 1951 .reg = 0x100, 1952 .num_ports = 2, 1953 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1954 .port_cfgs = { 1955 [USB2PHY_PORT_OTG] = { 1956 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, 1957 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1958 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1959 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1960 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1961 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1962 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1963 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1964 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1965 }, 1966 [USB2PHY_PORT_HOST] = { 1967 .phy_sus = { 0x0104, 15, 0, 0, 0x1d1 }, 1968 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1969 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1970 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1971 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1972 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1973 } 1974 }, 1975 .chg_det = { 1976 .opmode = { 0x0100, 3, 0, 5, 1 }, 1977 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1978 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1979 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1980 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1981 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1982 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1983 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1984 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1985 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1986 }, 1987 }, 1988 { /* sentinel */ } 1989 }; 1990 1991 static const struct of_device_id rockchip_usb2phy_dt_match[] = { 1992 { .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs }, 1993 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs }, 1994 { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs }, 1995 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, 1996 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, 1997 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, 1998 { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, 1999 { .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs }, 2000 { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, 2001 {} 2002 }; 2003 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match); 2004 2005 static struct platform_driver rockchip_usb2phy_driver = { 2006 .probe = rockchip_usb2phy_probe, 2007 .driver = { 2008 .name = "rockchip-usb2phy", 2009 .of_match_table = rockchip_usb2phy_dt_match, 2010 }, 2011 }; 2012 module_platform_driver(rockchip_usb2phy_driver); 2013 2014 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>"); 2015 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver"); 2016 MODULE_LICENSE("GPL v2"); 2017