1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip emmc PHY driver 4 * 5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com> 6 * Copyright (C) 2016 ROCKCHIP, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/hw_bitfield.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 20 /* 21 * The higher 16-bit of this register is used for write protection 22 * only if BIT(x + 16) set to 1 the BIT(x) can be written. 23 */ 24 #define HIWORD_UPDATE(val, mask, shift) \ 25 (FIELD_PREP_WM16((mask) << (shift), (val))) 26 27 /* Register definition */ 28 #define GRF_EMMCPHY_CON0 0x0 29 #define GRF_EMMCPHY_CON1 0x4 30 #define GRF_EMMCPHY_CON2 0x8 31 #define GRF_EMMCPHY_CON3 0xc 32 #define GRF_EMMCPHY_CON4 0x10 33 #define GRF_EMMCPHY_CON5 0x14 34 #define GRF_EMMCPHY_CON6 0x18 35 #define GRF_EMMCPHY_STATUS 0x20 36 37 #define PHYCTRL_PDB_MASK 0x1 38 #define PHYCTRL_PDB_SHIFT 0x0 39 #define PHYCTRL_PDB_PWR_ON 0x1 40 #define PHYCTRL_PDB_PWR_OFF 0x0 41 #define PHYCTRL_ENDLL_MASK 0x1 42 #define PHYCTRL_ENDLL_SHIFT 0x1 43 #define PHYCTRL_ENDLL_ENABLE 0x1 44 #define PHYCTRL_ENDLL_DISABLE 0x0 45 #define PHYCTRL_CALDONE_MASK 0x1 46 #define PHYCTRL_CALDONE_SHIFT 0x6 47 #define PHYCTRL_CALDONE_DONE 0x1 48 #define PHYCTRL_CALDONE_GOING 0x0 49 #define PHYCTRL_DLLRDY_MASK 0x1 50 #define PHYCTRL_DLLRDY_SHIFT 0x5 51 #define PHYCTRL_DLLRDY_DONE 0x1 52 #define PHYCTRL_DLLRDY_GOING 0x0 53 #define PHYCTRL_FREQSEL_200M 0x0 54 #define PHYCTRL_FREQSEL_50M 0x1 55 #define PHYCTRL_FREQSEL_100M 0x2 56 #define PHYCTRL_FREQSEL_150M 0x3 57 #define PHYCTRL_FREQSEL_MASK 0x3 58 #define PHYCTRL_FREQSEL_SHIFT 0xc 59 #define PHYCTRL_DR_MASK 0x7 60 #define PHYCTRL_DR_SHIFT 0x4 61 #define PHYCTRL_DR_50OHM 0x0 62 #define PHYCTRL_DR_33OHM 0x1 63 #define PHYCTRL_DR_66OHM 0x2 64 #define PHYCTRL_DR_100OHM 0x3 65 #define PHYCTRL_DR_40OHM 0x4 66 #define PHYCTRL_OTAPDLYENA 0x1 67 #define PHYCTRL_OTAPDLYENA_MASK 0x1 68 #define PHYCTRL_OTAPDLYENA_SHIFT 0xb 69 #define PHYCTRL_OTAPDLYSEL_DEFAULT 0x4 70 #define PHYCTRL_OTAPDLYSEL_MAXVALUE 0xf 71 #define PHYCTRL_OTAPDLYSEL_MASK 0xf 72 #define PHYCTRL_OTAPDLYSEL_SHIFT 0x7 73 #define PHYCTRL_REN_STRB_DISABLE 0x0 74 #define PHYCTRL_REN_STRB_ENABLE 0x1 75 #define PHYCTRL_REN_STRB_MASK 0x1 76 #define PHYCTRL_REN_STRB_SHIFT 0x9 77 78 #define PHYCTRL_IS_CALDONE(x) \ 79 ((((x) >> PHYCTRL_CALDONE_SHIFT) & \ 80 PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE) 81 #define PHYCTRL_IS_DLLRDY(x) \ 82 ((((x) >> PHYCTRL_DLLRDY_SHIFT) & \ 83 PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE) 84 85 struct rockchip_emmc_phy { 86 unsigned int reg_offset; 87 struct regmap *reg_base; 88 struct clk *emmcclk; 89 unsigned int drive_impedance; 90 unsigned int enable_strobe_pulldown; 91 unsigned int output_tapdelay_select; 92 }; 93 94 static int rockchip_emmc_phy_power(struct phy *phy, bool on_off) 95 { 96 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); 97 unsigned int caldone; 98 unsigned int dllrdy; 99 unsigned int freqsel = PHYCTRL_FREQSEL_200M; 100 unsigned long rate; 101 int ret; 102 103 /* 104 * Keep phyctrl_pdb and phyctrl_endll low to allow 105 * initialization of CALIO state M/C DFFs 106 */ 107 regmap_write(rk_phy->reg_base, 108 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 109 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, 110 PHYCTRL_PDB_MASK, 111 PHYCTRL_PDB_SHIFT)); 112 regmap_write(rk_phy->reg_base, 113 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 114 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, 115 PHYCTRL_ENDLL_MASK, 116 PHYCTRL_ENDLL_SHIFT)); 117 118 /* Already finish power_off above */ 119 if (on_off == PHYCTRL_PDB_PWR_OFF) 120 return 0; 121 122 rate = clk_get_rate(rk_phy->emmcclk); 123 124 if (rate != 0) { 125 unsigned long ideal_rate; 126 unsigned long diff; 127 128 switch (rate) { 129 case 1 ... 74999999: 130 ideal_rate = 50000000; 131 freqsel = PHYCTRL_FREQSEL_50M; 132 break; 133 case 75000000 ... 124999999: 134 ideal_rate = 100000000; 135 freqsel = PHYCTRL_FREQSEL_100M; 136 break; 137 case 125000000 ... 174999999: 138 ideal_rate = 150000000; 139 freqsel = PHYCTRL_FREQSEL_150M; 140 break; 141 default: 142 ideal_rate = 200000000; 143 break; 144 } 145 146 diff = (rate > ideal_rate) ? 147 rate - ideal_rate : ideal_rate - rate; 148 149 /* 150 * In order for tuning delays to be accurate we need to be 151 * pretty spot on for the DLL range, so warn if we're too 152 * far off. Also warn if we're above the 200 MHz max. Don't 153 * warn for really slow rates since we won't be tuning then. 154 */ 155 if ((rate > 50000000 && diff > 15000000) || (rate > 200000000)) 156 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); 157 } 158 159 /* 160 * According to the user manual, calpad calibration 161 * cycle takes more than 2us without the minimal recommended 162 * value, so we may need a little margin here 163 */ 164 udelay(3); 165 regmap_write(rk_phy->reg_base, 166 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 167 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, 168 PHYCTRL_PDB_MASK, 169 PHYCTRL_PDB_SHIFT)); 170 171 /* 172 * According to the user manual, it asks driver to wait 5us for 173 * calpad busy trimming. However it is documented that this value is 174 * PVT(A.K.A process,voltage and temperature) relevant, so some 175 * failure cases are found which indicates we should be more tolerant 176 * to calpad busy trimming. 177 */ 178 ret = regmap_read_poll_timeout(rk_phy->reg_base, 179 rk_phy->reg_offset + GRF_EMMCPHY_STATUS, 180 caldone, PHYCTRL_IS_CALDONE(caldone), 181 0, 50); 182 if (ret) { 183 pr_err("%s: caldone failed, ret=%d\n", __func__, ret); 184 return ret; 185 } 186 187 /* Set the frequency of the DLL operation */ 188 regmap_write(rk_phy->reg_base, 189 rk_phy->reg_offset + GRF_EMMCPHY_CON0, 190 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK, 191 PHYCTRL_FREQSEL_SHIFT)); 192 193 /* Turn on the DLL */ 194 regmap_write(rk_phy->reg_base, 195 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 196 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, 197 PHYCTRL_ENDLL_MASK, 198 PHYCTRL_ENDLL_SHIFT)); 199 200 /* 201 * We turned on the DLL even though the rate was 0 because we the 202 * clock might be turned on later. ...but we can't wait for the DLL 203 * to lock when the rate is 0 because it will never lock with no 204 * input clock. 205 * 206 * Technically we should be checking the lock later when the clock 207 * is turned on, but for now we won't. 208 */ 209 if (rate == 0) 210 return 0; 211 212 /* 213 * After enabling analog DLL circuits docs say that we need 10.2 us if 214 * our source clock is at 50 MHz and that lock time scales linearly 215 * with clock speed. If we are powering on the PHY and the card clock 216 * is super slow (like 100 kHZ) this could take as long as 5.1 ms as 217 * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms 218 * Hopefully we won't be running at 100 kHz, but we should still make 219 * sure we wait long enough. 220 * 221 * NOTE: There appear to be corner cases where the DLL seems to take 222 * extra long to lock for reasons that aren't understood. In some 223 * extreme cases we've seen it take up to over 10ms (!). We'll be 224 * generous and give it 50ms. 225 */ 226 ret = regmap_read_poll_timeout(rk_phy->reg_base, 227 rk_phy->reg_offset + GRF_EMMCPHY_STATUS, 228 dllrdy, PHYCTRL_IS_DLLRDY(dllrdy), 229 0, 50 * USEC_PER_MSEC); 230 if (ret) { 231 pr_err("%s: dllrdy failed. ret=%d\n", __func__, ret); 232 return ret; 233 } 234 235 return 0; 236 } 237 238 static int rockchip_emmc_phy_init(struct phy *phy) 239 { 240 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); 241 int ret = 0; 242 243 /* 244 * We purposely get the clock here and not in probe to avoid the 245 * circular dependency problem. We expect: 246 * - PHY driver to probe 247 * - SDHCI driver to start probe 248 * - SDHCI driver to register it's clock 249 * - SDHCI driver to get the PHY 250 * - SDHCI driver to init the PHY 251 * 252 * The clock is optional, using clk_get_optional() to get the clock 253 * and do error processing if the return value != NULL 254 * 255 * NOTE: we don't do anything special for EPROBE_DEFER here. Given the 256 * above expected use case, EPROBE_DEFER isn't sensible to expect, so 257 * it's just like any other error. 258 */ 259 rk_phy->emmcclk = clk_get_optional(&phy->dev, "emmcclk"); 260 if (IS_ERR(rk_phy->emmcclk)) { 261 ret = PTR_ERR(rk_phy->emmcclk); 262 dev_err(&phy->dev, "Error getting emmcclk: %d\n", ret); 263 rk_phy->emmcclk = NULL; 264 } 265 266 return ret; 267 } 268 269 static int rockchip_emmc_phy_exit(struct phy *phy) 270 { 271 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); 272 273 clk_put(rk_phy->emmcclk); 274 275 return 0; 276 } 277 278 static int rockchip_emmc_phy_power_off(struct phy *phy) 279 { 280 /* Power down emmc phy analog blocks */ 281 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF); 282 } 283 284 static int rockchip_emmc_phy_power_on(struct phy *phy) 285 { 286 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); 287 288 /* Drive impedance: from DTS */ 289 regmap_write(rk_phy->reg_base, 290 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 291 HIWORD_UPDATE(rk_phy->drive_impedance, 292 PHYCTRL_DR_MASK, 293 PHYCTRL_DR_SHIFT)); 294 295 /* Output tap delay: enable */ 296 regmap_write(rk_phy->reg_base, 297 rk_phy->reg_offset + GRF_EMMCPHY_CON0, 298 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, 299 PHYCTRL_OTAPDLYENA_MASK, 300 PHYCTRL_OTAPDLYENA_SHIFT)); 301 302 /* Output tap delay */ 303 regmap_write(rk_phy->reg_base, 304 rk_phy->reg_offset + GRF_EMMCPHY_CON0, 305 HIWORD_UPDATE(rk_phy->output_tapdelay_select, 306 PHYCTRL_OTAPDLYSEL_MASK, 307 PHYCTRL_OTAPDLYSEL_SHIFT)); 308 309 /* Internal pull-down for strobe line */ 310 regmap_write(rk_phy->reg_base, 311 rk_phy->reg_offset + GRF_EMMCPHY_CON2, 312 HIWORD_UPDATE(rk_phy->enable_strobe_pulldown, 313 PHYCTRL_REN_STRB_MASK, 314 PHYCTRL_REN_STRB_SHIFT)); 315 316 /* Power up emmc phy analog blocks */ 317 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON); 318 } 319 320 static const struct phy_ops ops = { 321 .init = rockchip_emmc_phy_init, 322 .exit = rockchip_emmc_phy_exit, 323 .power_on = rockchip_emmc_phy_power_on, 324 .power_off = rockchip_emmc_phy_power_off, 325 .owner = THIS_MODULE, 326 }; 327 328 static u32 convert_drive_impedance_ohm(struct platform_device *pdev, u32 dr_ohm) 329 { 330 switch (dr_ohm) { 331 case 100: 332 return PHYCTRL_DR_100OHM; 333 case 66: 334 return PHYCTRL_DR_66OHM; 335 case 50: 336 return PHYCTRL_DR_50OHM; 337 case 40: 338 return PHYCTRL_DR_40OHM; 339 case 33: 340 return PHYCTRL_DR_33OHM; 341 } 342 343 dev_warn(&pdev->dev, "Invalid value %u for drive-impedance-ohm.\n", 344 dr_ohm); 345 return PHYCTRL_DR_50OHM; 346 } 347 348 static int rockchip_emmc_phy_probe(struct platform_device *pdev) 349 { 350 struct device *dev = &pdev->dev; 351 struct rockchip_emmc_phy *rk_phy; 352 struct phy *generic_phy; 353 struct phy_provider *phy_provider; 354 struct regmap *grf; 355 unsigned int reg_offset; 356 u32 val; 357 358 if (!dev->parent || !dev->parent->of_node) 359 return -ENODEV; 360 361 grf = syscon_node_to_regmap(dev->parent->of_node); 362 if (IS_ERR(grf)) { 363 dev_err(dev, "Missing rockchip,grf property\n"); 364 return PTR_ERR(grf); 365 } 366 367 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL); 368 if (!rk_phy) 369 return -ENOMEM; 370 371 if (of_property_read_u32(dev->of_node, "reg", ®_offset)) { 372 dev_err(dev, "missing reg property in node %pOFn\n", 373 dev->of_node); 374 return -EINVAL; 375 } 376 377 rk_phy->reg_offset = reg_offset; 378 rk_phy->reg_base = grf; 379 rk_phy->drive_impedance = PHYCTRL_DR_50OHM; 380 rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_DISABLE; 381 rk_phy->output_tapdelay_select = PHYCTRL_OTAPDLYSEL_DEFAULT; 382 383 if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm", &val)) 384 rk_phy->drive_impedance = convert_drive_impedance_ohm(pdev, val); 385 386 if (of_property_read_bool(dev->of_node, "rockchip,enable-strobe-pulldown")) 387 rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_ENABLE; 388 389 if (!of_property_read_u32(dev->of_node, "rockchip,output-tapdelay-select", &val)) { 390 if (val <= PHYCTRL_OTAPDLYSEL_MAXVALUE) 391 rk_phy->output_tapdelay_select = val; 392 else 393 dev_err(dev, "output-tapdelay-select exceeds limit, apply default\n"); 394 } 395 396 generic_phy = devm_phy_create(dev, dev->of_node, &ops); 397 if (IS_ERR(generic_phy)) { 398 dev_err(dev, "failed to create PHY\n"); 399 return PTR_ERR(generic_phy); 400 } 401 402 phy_set_drvdata(generic_phy, rk_phy); 403 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 404 405 return PTR_ERR_OR_ZERO(phy_provider); 406 } 407 408 static const struct of_device_id rockchip_emmc_phy_dt_ids[] = { 409 { .compatible = "rockchip,rk3399-emmc-phy" }, 410 {} 411 }; 412 413 MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids); 414 415 static struct platform_driver rockchip_emmc_driver = { 416 .probe = rockchip_emmc_phy_probe, 417 .driver = { 418 .name = "rockchip-emmc-phy", 419 .of_match_table = rockchip_emmc_phy_dt_ids, 420 }, 421 }; 422 423 module_platform_driver(rockchip_emmc_driver); 424 425 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>"); 426 MODULE_DESCRIPTION("Rockchip EMMC PHY driver"); 427 MODULE_LICENSE("GPL v2"); 428