1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * phy-rtk-usb2.c RTK usb2.0 PHY driver 4 * 5 * Copyright (C) 2023 Realtek Semiconductor Corporation 6 * 7 */ 8 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/of_address.h> 13 #include <linux/uaccess.h> 14 #include <linux/debugfs.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/regmap.h> 17 #include <linux/sys_soc.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/phy/phy.h> 20 #include <linux/usb.h> 21 #include <linux/usb/phy.h> 22 #include <linux/usb/hcd.h> 23 24 /* GUSB2PHYACCn register */ 25 #define PHY_NEW_REG_REQ BIT(25) 26 #define PHY_VSTS_BUSY BIT(23) 27 #define PHY_VCTRL_SHIFT 8 28 #define PHY_REG_DATA_MASK 0xff 29 30 #define GET_LOW_NIBBLE(addr) ((addr) & 0x0f) 31 #define GET_HIGH_NIBBLE(addr) (((addr) & 0xf0) >> 4) 32 33 #define EFUS_USB_DC_CAL_RATE 2 34 #define EFUS_USB_DC_CAL_MAX 7 35 36 #define EFUS_USB_DC_DIS_RATE 1 37 #define EFUS_USB_DC_DIS_MAX 7 38 39 #define MAX_PHY_DATA_SIZE 20 40 #define OFFEST_PHY_READ 0x20 41 42 #define MAX_USB_PHY_NUM 4 43 #define MAX_USB_PHY_PAGE0_DATA_SIZE 16 44 #define MAX_USB_PHY_PAGE1_DATA_SIZE 16 45 #define MAX_USB_PHY_PAGE2_DATA_SIZE 8 46 47 #define SET_PAGE_OFFSET 0xf4 48 #define SET_PAGE_0 0x9b 49 #define SET_PAGE_1 0xbb 50 #define SET_PAGE_2 0xdb 51 52 #define PAGE_START 0xe0 53 #define PAGE0_0XE4 0xe4 54 #define PAGE0_0XE6 0xe6 55 #define PAGE0_0XE7 0xe7 56 #define PAGE1_0XE0 0xe0 57 #define PAGE1_0XE2 0xe2 58 59 #define SENSITIVITY_CTRL (BIT(4) | BIT(5) | BIT(6)) 60 #define ENABLE_AUTO_SENSITIVITY_CALIBRATION BIT(2) 61 #define DEFAULT_DC_DRIVING_VALUE (0x8) 62 #define DEFAULT_DC_DISCONNECTION_VALUE (0x6) 63 #define HS_CLK_SELECT BIT(6) 64 65 struct phy_reg { 66 void __iomem *reg_wrap_vstatus; 67 void __iomem *reg_gusb2phyacc0; 68 int vstatus_index; 69 }; 70 71 struct phy_data { 72 u8 addr; 73 u8 data; 74 }; 75 76 struct phy_cfg { 77 int page0_size; 78 struct phy_data page0[MAX_USB_PHY_PAGE0_DATA_SIZE]; 79 int page1_size; 80 struct phy_data page1[MAX_USB_PHY_PAGE1_DATA_SIZE]; 81 int page2_size; 82 struct phy_data page2[MAX_USB_PHY_PAGE2_DATA_SIZE]; 83 84 int num_phy; 85 86 bool check_efuse; 87 int check_efuse_version; 88 #define CHECK_EFUSE_V1 1 89 #define CHECK_EFUSE_V2 2 90 int efuse_dc_driving_rate; 91 int efuse_dc_disconnect_rate; 92 int dc_driving_mask; 93 int dc_disconnect_mask; 94 bool usb_dc_disconnect_at_page0; 95 int driving_updated_for_dev_dis; 96 97 bool do_toggle; 98 bool do_toggle_driving; 99 bool use_default_parameter; 100 bool is_double_sensitivity_mode; 101 }; 102 103 struct phy_parameter { 104 struct phy_reg phy_reg; 105 106 /* Get from efuse */ 107 s8 efuse_usb_dc_cal; 108 s8 efuse_usb_dc_dis; 109 110 /* Get from dts */ 111 bool inverse_hstx_sync_clock; 112 u32 driving_level; 113 s32 driving_level_compensate; 114 s32 disconnection_compensate; 115 }; 116 117 struct rtk_phy { 118 struct usb_phy phy; 119 struct device *dev; 120 121 struct phy_cfg *phy_cfg; 122 int num_phy; 123 struct phy_parameter *phy_parameter; 124 125 struct dentry *debug_dir; 126 }; 127 128 /* mapping 0xE0 to 0 ... 0xE7 to 7, 0xF0 to 8 ,,, 0xF7 to 15 */ 129 static inline int page_addr_to_array_index(u8 addr) 130 { 131 return (int)((((addr) - PAGE_START) & 0x7) + 132 ((((addr) - PAGE_START) & 0x10) >> 1)); 133 } 134 135 static inline u8 array_index_to_page_addr(int index) 136 { 137 return ((((index) + PAGE_START) & 0x7) + 138 ((((index) & 0x8) << 1) + PAGE_START)); 139 } 140 141 #define PHY_IO_TIMEOUT_USEC (50000) 142 #define PHY_IO_DELAY_US (100) 143 144 static inline int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) 145 { 146 int ret; 147 unsigned int val; 148 149 ret = read_poll_timeout(readl, val, ((val & mask) == result), 150 PHY_IO_DELAY_US, PHY_IO_TIMEOUT_USEC, false, reg); 151 if (ret) { 152 pr_err("%s can't program USB phy\n", __func__); 153 return -ETIMEDOUT; 154 } 155 156 return 0; 157 } 158 159 static char rtk_phy_read(struct phy_reg *phy_reg, char addr) 160 { 161 void __iomem *reg_gusb2phyacc0 = phy_reg->reg_gusb2phyacc0; 162 unsigned int val; 163 int ret = 0; 164 165 addr -= OFFEST_PHY_READ; 166 167 /* polling until VBusy == 0 */ 168 ret = utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); 169 if (ret) 170 return (char)ret; 171 172 /* VCtrl = low nibble of addr, and set PHY_NEW_REG_REQ */ 173 val = PHY_NEW_REG_REQ | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); 174 writel(val, reg_gusb2phyacc0); 175 ret = utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); 176 if (ret) 177 return (char)ret; 178 179 /* VCtrl = high nibble of addr, and set PHY_NEW_REG_REQ */ 180 val = PHY_NEW_REG_REQ | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); 181 writel(val, reg_gusb2phyacc0); 182 ret = utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); 183 if (ret) 184 return (char)ret; 185 186 val = readl(reg_gusb2phyacc0); 187 188 return (char)(val & PHY_REG_DATA_MASK); 189 } 190 191 static int rtk_phy_write(struct phy_reg *phy_reg, char addr, char data) 192 { 193 unsigned int val; 194 void __iomem *reg_wrap_vstatus = phy_reg->reg_wrap_vstatus; 195 void __iomem *reg_gusb2phyacc0 = phy_reg->reg_gusb2phyacc0; 196 int shift_bits = phy_reg->vstatus_index * 8; 197 int ret = 0; 198 199 /* write data to VStatusOut2 (data output to phy) */ 200 writel((u32)data << shift_bits, reg_wrap_vstatus); 201 202 ret = utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); 203 if (ret) 204 return ret; 205 206 /* VCtrl = low nibble of addr, set PHY_NEW_REG_REQ */ 207 val = PHY_NEW_REG_REQ | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); 208 209 writel(val, reg_gusb2phyacc0); 210 ret = utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); 211 if (ret) 212 return ret; 213 214 /* VCtrl = high nibble of addr, set PHY_NEW_REG_REQ */ 215 val = PHY_NEW_REG_REQ | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); 216 217 writel(val, reg_gusb2phyacc0); 218 ret = utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); 219 if (ret) 220 return ret; 221 222 return 0; 223 } 224 225 static int rtk_phy_set_page(struct phy_reg *phy_reg, int page) 226 { 227 switch (page) { 228 case 0: 229 return rtk_phy_write(phy_reg, SET_PAGE_OFFSET, SET_PAGE_0); 230 case 1: 231 return rtk_phy_write(phy_reg, SET_PAGE_OFFSET, SET_PAGE_1); 232 case 2: 233 return rtk_phy_write(phy_reg, SET_PAGE_OFFSET, SET_PAGE_2); 234 default: 235 pr_err("%s error page=%d\n", __func__, page); 236 } 237 238 return -EINVAL; 239 } 240 241 static u8 __updated_dc_disconnect_level_page0_0xe4(struct phy_cfg *phy_cfg, 242 struct phy_parameter *phy_parameter, u8 data) 243 { 244 u8 ret; 245 s32 val; 246 s32 dc_disconnect_mask = phy_cfg->dc_disconnect_mask; 247 int offset = 4; 248 249 val = (s32)((data >> offset) & dc_disconnect_mask) 250 + phy_parameter->efuse_usb_dc_dis 251 + phy_parameter->disconnection_compensate; 252 253 if (val > dc_disconnect_mask) 254 val = dc_disconnect_mask; 255 else if (val < 0) 256 val = 0; 257 258 ret = (data & (~(dc_disconnect_mask << offset))) | 259 (val & dc_disconnect_mask) << offset; 260 261 return ret; 262 } 263 264 /* updated disconnect level at page0 */ 265 static void update_dc_disconnect_level_at_page0(struct rtk_phy *rtk_phy, 266 struct phy_parameter *phy_parameter, bool update) 267 { 268 struct phy_cfg *phy_cfg; 269 struct phy_reg *phy_reg; 270 struct phy_data *phy_data_page; 271 struct phy_data *phy_data; 272 u8 addr, data; 273 int offset = 4; 274 s32 dc_disconnect_mask; 275 int i; 276 277 phy_cfg = rtk_phy->phy_cfg; 278 phy_reg = &phy_parameter->phy_reg; 279 280 /* Set page 0 */ 281 phy_data_page = phy_cfg->page0; 282 rtk_phy_set_page(phy_reg, 0); 283 284 i = page_addr_to_array_index(PAGE0_0XE4); 285 phy_data = phy_data_page + i; 286 if (!phy_data->addr) { 287 phy_data->addr = PAGE0_0XE4; 288 phy_data->data = rtk_phy_read(phy_reg, PAGE0_0XE4); 289 } 290 291 addr = phy_data->addr; 292 data = phy_data->data; 293 dc_disconnect_mask = phy_cfg->dc_disconnect_mask; 294 295 if (update) 296 data = __updated_dc_disconnect_level_page0_0xe4(phy_cfg, phy_parameter, data); 297 else 298 data = (data & ~(dc_disconnect_mask << offset)) | 299 (DEFAULT_DC_DISCONNECTION_VALUE << offset); 300 301 if (rtk_phy_write(phy_reg, addr, data)) 302 dev_err(rtk_phy->dev, 303 "%s: Error to set page1 parameter addr=0x%x value=0x%x\n", 304 __func__, addr, data); 305 } 306 307 static u8 __updated_dc_disconnect_level_page1_0xe2(struct phy_cfg *phy_cfg, 308 struct phy_parameter *phy_parameter, u8 data) 309 { 310 u8 ret; 311 s32 val; 312 s32 dc_disconnect_mask = phy_cfg->dc_disconnect_mask; 313 314 if (phy_cfg->check_efuse_version == CHECK_EFUSE_V1) { 315 val = (s32)(data & dc_disconnect_mask) 316 + phy_parameter->efuse_usb_dc_dis 317 + phy_parameter->disconnection_compensate; 318 } else { /* for CHECK_EFUSE_V2 or no efuse */ 319 if (phy_parameter->efuse_usb_dc_dis) 320 val = (s32)(phy_parameter->efuse_usb_dc_dis + 321 phy_parameter->disconnection_compensate); 322 else 323 val = (s32)((data & dc_disconnect_mask) + 324 phy_parameter->disconnection_compensate); 325 } 326 327 if (val > dc_disconnect_mask) 328 val = dc_disconnect_mask; 329 else if (val < 0) 330 val = 0; 331 332 ret = (data & (~dc_disconnect_mask)) | (val & dc_disconnect_mask); 333 334 return ret; 335 } 336 337 /* updated disconnect level at page1 */ 338 static void update_dc_disconnect_level_at_page1(struct rtk_phy *rtk_phy, 339 struct phy_parameter *phy_parameter, bool update) 340 { 341 struct phy_cfg *phy_cfg; 342 struct phy_data *phy_data_page; 343 struct phy_data *phy_data; 344 struct phy_reg *phy_reg; 345 u8 addr, data; 346 s32 dc_disconnect_mask; 347 int i; 348 349 phy_cfg = rtk_phy->phy_cfg; 350 phy_reg = &phy_parameter->phy_reg; 351 352 /* Set page 1 */ 353 phy_data_page = phy_cfg->page1; 354 rtk_phy_set_page(phy_reg, 1); 355 356 i = page_addr_to_array_index(PAGE1_0XE2); 357 phy_data = phy_data_page + i; 358 if (!phy_data->addr) { 359 phy_data->addr = PAGE1_0XE2; 360 phy_data->data = rtk_phy_read(phy_reg, PAGE1_0XE2); 361 } 362 363 addr = phy_data->addr; 364 data = phy_data->data; 365 dc_disconnect_mask = phy_cfg->dc_disconnect_mask; 366 367 if (update) 368 data = __updated_dc_disconnect_level_page1_0xe2(phy_cfg, phy_parameter, data); 369 else 370 data = (data & ~dc_disconnect_mask) | DEFAULT_DC_DISCONNECTION_VALUE; 371 372 if (rtk_phy_write(phy_reg, addr, data)) 373 dev_err(rtk_phy->dev, 374 "%s: Error to set page1 parameter addr=0x%x value=0x%x\n", 375 __func__, addr, data); 376 } 377 378 static void update_dc_disconnect_level(struct rtk_phy *rtk_phy, 379 struct phy_parameter *phy_parameter, bool update) 380 { 381 struct phy_cfg *phy_cfg = rtk_phy->phy_cfg; 382 383 if (phy_cfg->usb_dc_disconnect_at_page0) 384 update_dc_disconnect_level_at_page0(rtk_phy, phy_parameter, update); 385 else 386 update_dc_disconnect_level_at_page1(rtk_phy, phy_parameter, update); 387 } 388 389 static u8 __update_dc_driving_page0_0xe4(struct phy_cfg *phy_cfg, 390 struct phy_parameter *phy_parameter, u8 data) 391 { 392 s32 driving_level_compensate = phy_parameter->driving_level_compensate; 393 s32 dc_driving_mask = phy_cfg->dc_driving_mask; 394 s32 val; 395 u8 ret; 396 397 if (phy_cfg->check_efuse_version == CHECK_EFUSE_V1) { 398 val = (s32)(data & dc_driving_mask) + driving_level_compensate 399 + phy_parameter->efuse_usb_dc_cal; 400 } else { /* for CHECK_EFUSE_V2 or no efuse */ 401 if (phy_parameter->efuse_usb_dc_cal) 402 val = (s32)((phy_parameter->efuse_usb_dc_cal & dc_driving_mask) 403 + driving_level_compensate); 404 else 405 val = (s32)(data & dc_driving_mask); 406 } 407 408 if (val > dc_driving_mask) 409 val = dc_driving_mask; 410 else if (val < 0) 411 val = 0; 412 413 ret = (data & (~dc_driving_mask)) | (val & dc_driving_mask); 414 415 return ret; 416 } 417 418 static void update_dc_driving_level(struct rtk_phy *rtk_phy, 419 struct phy_parameter *phy_parameter) 420 { 421 struct phy_cfg *phy_cfg; 422 struct phy_reg *phy_reg; 423 424 phy_reg = &phy_parameter->phy_reg; 425 phy_cfg = rtk_phy->phy_cfg; 426 if (!phy_cfg->page0[4].addr) { 427 rtk_phy_set_page(phy_reg, 0); 428 phy_cfg->page0[4].addr = PAGE0_0XE4; 429 phy_cfg->page0[4].data = rtk_phy_read(phy_reg, PAGE0_0XE4); 430 } 431 432 if (phy_parameter->driving_level != DEFAULT_DC_DRIVING_VALUE) { 433 u32 dc_driving_mask; 434 u8 driving_level; 435 u8 data; 436 437 data = phy_cfg->page0[4].data; 438 dc_driving_mask = phy_cfg->dc_driving_mask; 439 driving_level = data & dc_driving_mask; 440 441 dev_dbg(rtk_phy->dev, "%s driving_level=%d => dts driving_level=%d\n", 442 __func__, driving_level, phy_parameter->driving_level); 443 444 phy_cfg->page0[4].data = (data & (~dc_driving_mask)) | 445 (phy_parameter->driving_level & dc_driving_mask); 446 } 447 448 phy_cfg->page0[4].data = __update_dc_driving_page0_0xe4(phy_cfg, 449 phy_parameter, 450 phy_cfg->page0[4].data); 451 } 452 453 static void update_hs_clk_select(struct rtk_phy *rtk_phy, 454 struct phy_parameter *phy_parameter) 455 { 456 struct phy_cfg *phy_cfg; 457 struct phy_reg *phy_reg; 458 459 phy_cfg = rtk_phy->phy_cfg; 460 phy_reg = &phy_parameter->phy_reg; 461 462 if (phy_parameter->inverse_hstx_sync_clock) { 463 if (!phy_cfg->page0[6].addr) { 464 rtk_phy_set_page(phy_reg, 0); 465 phy_cfg->page0[6].addr = PAGE0_0XE6; 466 phy_cfg->page0[6].data = rtk_phy_read(phy_reg, PAGE0_0XE6); 467 } 468 469 phy_cfg->page0[6].data = phy_cfg->page0[6].data | HS_CLK_SELECT; 470 } 471 } 472 473 static void do_rtk_phy_toggle(struct rtk_phy *rtk_phy, 474 int index, bool connect) 475 { 476 struct phy_parameter *phy_parameter; 477 struct phy_cfg *phy_cfg; 478 struct phy_reg *phy_reg; 479 struct phy_data *phy_data_page; 480 u8 addr, data; 481 int i; 482 483 phy_cfg = rtk_phy->phy_cfg; 484 phy_parameter = &((struct phy_parameter *)rtk_phy->phy_parameter)[index]; 485 phy_reg = &phy_parameter->phy_reg; 486 487 if (!phy_cfg->do_toggle) 488 goto out; 489 490 if (phy_cfg->is_double_sensitivity_mode) 491 goto do_toggle_driving; 492 493 /* Set page 0 */ 494 rtk_phy_set_page(phy_reg, 0); 495 496 addr = PAGE0_0XE7; 497 data = rtk_phy_read(phy_reg, addr); 498 499 if (connect) 500 rtk_phy_write(phy_reg, addr, data & (~SENSITIVITY_CTRL)); 501 else 502 rtk_phy_write(phy_reg, addr, data | (SENSITIVITY_CTRL)); 503 504 do_toggle_driving: 505 506 if (!phy_cfg->do_toggle_driving) 507 goto do_toggle; 508 509 /* Page 0 addr 0xE4 driving capability */ 510 511 /* Set page 0 */ 512 phy_data_page = phy_cfg->page0; 513 rtk_phy_set_page(phy_reg, 0); 514 515 i = page_addr_to_array_index(PAGE0_0XE4); 516 addr = phy_data_page[i].addr; 517 data = phy_data_page[i].data; 518 519 if (connect) { 520 rtk_phy_write(phy_reg, addr, data); 521 } else { 522 u8 value; 523 s32 tmp; 524 s32 driving_updated = 525 phy_cfg->driving_updated_for_dev_dis; 526 s32 dc_driving_mask = phy_cfg->dc_driving_mask; 527 528 tmp = (s32)(data & dc_driving_mask) + driving_updated; 529 530 if (tmp > dc_driving_mask) 531 tmp = dc_driving_mask; 532 else if (tmp < 0) 533 tmp = 0; 534 535 value = (data & (~dc_driving_mask)) | (tmp & dc_driving_mask); 536 537 rtk_phy_write(phy_reg, addr, value); 538 } 539 540 do_toggle: 541 /* restore dc disconnect level before toggle */ 542 update_dc_disconnect_level(rtk_phy, phy_parameter, false); 543 544 /* Set page 1 */ 545 rtk_phy_set_page(phy_reg, 1); 546 547 addr = PAGE1_0XE0; 548 data = rtk_phy_read(phy_reg, addr); 549 550 rtk_phy_write(phy_reg, addr, data & 551 (~ENABLE_AUTO_SENSITIVITY_CALIBRATION)); 552 mdelay(1); 553 rtk_phy_write(phy_reg, addr, data | 554 (ENABLE_AUTO_SENSITIVITY_CALIBRATION)); 555 556 /* update dc disconnect level after toggle */ 557 update_dc_disconnect_level(rtk_phy, phy_parameter, true); 558 559 out: 560 return; 561 } 562 563 static int do_rtk_phy_init(struct rtk_phy *rtk_phy, int index) 564 { 565 struct phy_parameter *phy_parameter; 566 struct phy_cfg *phy_cfg; 567 struct phy_data *phy_data_page; 568 struct phy_reg *phy_reg; 569 int i; 570 571 phy_cfg = rtk_phy->phy_cfg; 572 phy_parameter = &((struct phy_parameter *)rtk_phy->phy_parameter)[index]; 573 phy_reg = &phy_parameter->phy_reg; 574 575 if (phy_cfg->use_default_parameter) { 576 dev_dbg(rtk_phy->dev, "%s phy#%d use default parameter\n", 577 __func__, index); 578 goto do_toggle; 579 } 580 581 /* Set page 0 */ 582 phy_data_page = phy_cfg->page0; 583 rtk_phy_set_page(phy_reg, 0); 584 585 for (i = 0; i < phy_cfg->page0_size; i++) { 586 struct phy_data *phy_data = phy_data_page + i; 587 u8 addr = phy_data->addr; 588 u8 data = phy_data->data; 589 590 if (!addr) 591 continue; 592 593 if (rtk_phy_write(phy_reg, addr, data)) { 594 dev_err(rtk_phy->dev, 595 "%s: Error to set page0 parameter addr=0x%x value=0x%x\n", 596 __func__, addr, data); 597 return -EINVAL; 598 } 599 } 600 601 /* Set page 1 */ 602 phy_data_page = phy_cfg->page1; 603 rtk_phy_set_page(phy_reg, 1); 604 605 for (i = 0; i < phy_cfg->page1_size; i++) { 606 struct phy_data *phy_data = phy_data_page + i; 607 u8 addr = phy_data->addr; 608 u8 data = phy_data->data; 609 610 if (!addr) 611 continue; 612 613 if (rtk_phy_write(phy_reg, addr, data)) { 614 dev_err(rtk_phy->dev, 615 "%s: Error to set page1 parameter addr=0x%x value=0x%x\n", 616 __func__, addr, data); 617 return -EINVAL; 618 } 619 } 620 621 if (phy_cfg->page2_size == 0) 622 goto do_toggle; 623 624 /* Set page 2 */ 625 phy_data_page = phy_cfg->page2; 626 rtk_phy_set_page(phy_reg, 2); 627 628 for (i = 0; i < phy_cfg->page2_size; i++) { 629 struct phy_data *phy_data = phy_data_page + i; 630 u8 addr = phy_data->addr; 631 u8 data = phy_data->data; 632 633 if (!addr) 634 continue; 635 636 if (rtk_phy_write(phy_reg, addr, data)) { 637 dev_err(rtk_phy->dev, 638 "%s: Error to set page2 parameter addr=0x%x value=0x%x\n", 639 __func__, addr, data); 640 return -EINVAL; 641 } 642 } 643 644 do_toggle: 645 do_rtk_phy_toggle(rtk_phy, index, false); 646 647 return 0; 648 } 649 650 static int rtk_phy_init(struct phy *phy) 651 { 652 struct rtk_phy *rtk_phy = phy_get_drvdata(phy); 653 unsigned long phy_init_time = jiffies; 654 int i, ret = 0; 655 656 if (!rtk_phy) 657 return -EINVAL; 658 659 for (i = 0; i < rtk_phy->num_phy; i++) 660 ret = do_rtk_phy_init(rtk_phy, i); 661 662 dev_dbg(rtk_phy->dev, "Initialized RTK USB 2.0 PHY (take %dms)\n", 663 jiffies_to_msecs(jiffies - phy_init_time)); 664 return ret; 665 } 666 667 static int rtk_phy_exit(struct phy *phy) 668 { 669 return 0; 670 } 671 672 static const struct phy_ops ops = { 673 .init = rtk_phy_init, 674 .exit = rtk_phy_exit, 675 .owner = THIS_MODULE, 676 }; 677 678 static void rtk_phy_toggle(struct usb_phy *usb2_phy, bool connect, int port) 679 { 680 int index = port; 681 struct rtk_phy *rtk_phy = NULL; 682 683 rtk_phy = dev_get_drvdata(usb2_phy->dev); 684 685 if (index > rtk_phy->num_phy) { 686 dev_err(rtk_phy->dev, "%s: The port=%d is not in usb phy (num_phy=%d)\n", 687 __func__, index, rtk_phy->num_phy); 688 return; 689 } 690 691 do_rtk_phy_toggle(rtk_phy, index, connect); 692 } 693 694 static int rtk_phy_notify_port_status(struct usb_phy *x, int port, 695 u16 portstatus, u16 portchange) 696 { 697 bool connect = false; 698 699 pr_debug("%s port=%d portstatus=0x%x portchange=0x%x\n", 700 __func__, port, (int)portstatus, (int)portchange); 701 if (portstatus & USB_PORT_STAT_CONNECTION) 702 connect = true; 703 704 if (portchange & USB_PORT_STAT_C_CONNECTION) 705 rtk_phy_toggle(x, connect, port); 706 707 return 0; 708 } 709 710 #ifdef CONFIG_DEBUG_FS 711 static struct dentry *create_phy_debug_root(void) 712 { 713 struct dentry *phy_debug_root; 714 715 phy_debug_root = debugfs_lookup("phy", usb_debug_root); 716 if (!phy_debug_root) 717 phy_debug_root = debugfs_create_dir("phy", usb_debug_root); 718 719 return phy_debug_root; 720 } 721 722 static int rtk_usb2_parameter_show(struct seq_file *s, void *unused) 723 { 724 struct rtk_phy *rtk_phy = s->private; 725 struct phy_cfg *phy_cfg; 726 int i, index; 727 728 phy_cfg = rtk_phy->phy_cfg; 729 730 seq_puts(s, "Property:\n"); 731 seq_printf(s, " check_efuse: %s\n", 732 phy_cfg->check_efuse ? "Enable" : "Disable"); 733 seq_printf(s, " check_efuse_version: %d\n", 734 phy_cfg->check_efuse_version); 735 seq_printf(s, " efuse_dc_driving_rate: %d\n", 736 phy_cfg->efuse_dc_driving_rate); 737 seq_printf(s, " dc_driving_mask: 0x%x\n", 738 phy_cfg->dc_driving_mask); 739 seq_printf(s, " efuse_dc_disconnect_rate: %d\n", 740 phy_cfg->efuse_dc_disconnect_rate); 741 seq_printf(s, " dc_disconnect_mask: 0x%x\n", 742 phy_cfg->dc_disconnect_mask); 743 seq_printf(s, " usb_dc_disconnect_at_page0: %s\n", 744 phy_cfg->usb_dc_disconnect_at_page0 ? "true" : "false"); 745 seq_printf(s, " do_toggle: %s\n", 746 phy_cfg->do_toggle ? "Enable" : "Disable"); 747 seq_printf(s, " do_toggle_driving: %s\n", 748 phy_cfg->do_toggle_driving ? "Enable" : "Disable"); 749 seq_printf(s, " driving_updated_for_dev_dis: 0x%x\n", 750 phy_cfg->driving_updated_for_dev_dis); 751 seq_printf(s, " use_default_parameter: %s\n", 752 phy_cfg->use_default_parameter ? "Enable" : "Disable"); 753 seq_printf(s, " is_double_sensitivity_mode: %s\n", 754 phy_cfg->is_double_sensitivity_mode ? "Enable" : "Disable"); 755 756 for (index = 0; index < rtk_phy->num_phy; index++) { 757 struct phy_parameter *phy_parameter; 758 struct phy_reg *phy_reg; 759 struct phy_data *phy_data_page; 760 761 phy_parameter = &((struct phy_parameter *)rtk_phy->phy_parameter)[index]; 762 phy_reg = &phy_parameter->phy_reg; 763 764 seq_printf(s, "PHY %d:\n", index); 765 766 seq_puts(s, "Page 0:\n"); 767 /* Set page 0 */ 768 phy_data_page = phy_cfg->page0; 769 rtk_phy_set_page(phy_reg, 0); 770 771 for (i = 0; i < phy_cfg->page0_size; i++) { 772 struct phy_data *phy_data = phy_data_page + i; 773 u8 addr = array_index_to_page_addr(i); 774 u8 data = phy_data->data; 775 u8 value = rtk_phy_read(phy_reg, addr); 776 777 if (phy_data->addr) 778 seq_printf(s, " Page 0: addr=0x%x data=0x%02x ==> read value=0x%02x\n", 779 addr, data, value); 780 else 781 seq_printf(s, " Page 0: addr=0x%x data=none ==> read value=0x%02x\n", 782 addr, value); 783 } 784 785 seq_puts(s, "Page 1:\n"); 786 /* Set page 1 */ 787 phy_data_page = phy_cfg->page1; 788 rtk_phy_set_page(phy_reg, 1); 789 790 for (i = 0; i < phy_cfg->page1_size; i++) { 791 struct phy_data *phy_data = phy_data_page + i; 792 u8 addr = array_index_to_page_addr(i); 793 u8 data = phy_data->data; 794 u8 value = rtk_phy_read(phy_reg, addr); 795 796 if (phy_data->addr) 797 seq_printf(s, " Page 1: addr=0x%x data=0x%02x ==> read value=0x%02x\n", 798 addr, data, value); 799 else 800 seq_printf(s, " Page 1: addr=0x%x data=none ==> read value=0x%02x\n", 801 addr, value); 802 } 803 804 if (phy_cfg->page2_size == 0) 805 goto out; 806 807 seq_puts(s, "Page 2:\n"); 808 /* Set page 2 */ 809 phy_data_page = phy_cfg->page2; 810 rtk_phy_set_page(phy_reg, 2); 811 812 for (i = 0; i < phy_cfg->page2_size; i++) { 813 struct phy_data *phy_data = phy_data_page + i; 814 u8 addr = array_index_to_page_addr(i); 815 u8 data = phy_data->data; 816 u8 value = rtk_phy_read(phy_reg, addr); 817 818 if (phy_data->addr) 819 seq_printf(s, " Page 2: addr=0x%x data=0x%02x ==> read value=0x%02x\n", 820 addr, data, value); 821 else 822 seq_printf(s, " Page 2: addr=0x%x data=none ==> read value=0x%02x\n", 823 addr, value); 824 } 825 826 out: 827 seq_puts(s, "PHY Property:\n"); 828 seq_printf(s, " efuse_usb_dc_cal: %d\n", 829 (int)phy_parameter->efuse_usb_dc_cal); 830 seq_printf(s, " efuse_usb_dc_dis: %d\n", 831 (int)phy_parameter->efuse_usb_dc_dis); 832 seq_printf(s, " inverse_hstx_sync_clock: %s\n", 833 phy_parameter->inverse_hstx_sync_clock ? "Enable" : "Disable"); 834 seq_printf(s, " driving_level: %d\n", 835 phy_parameter->driving_level); 836 seq_printf(s, " driving_level_compensate: %d\n", 837 phy_parameter->driving_level_compensate); 838 seq_printf(s, " disconnection_compensate: %d\n", 839 phy_parameter->disconnection_compensate); 840 } 841 842 return 0; 843 } 844 DEFINE_SHOW_ATTRIBUTE(rtk_usb2_parameter); 845 846 static inline void create_debug_files(struct rtk_phy *rtk_phy) 847 { 848 struct dentry *phy_debug_root = NULL; 849 850 phy_debug_root = create_phy_debug_root(); 851 if (!phy_debug_root) 852 return; 853 854 rtk_phy->debug_dir = debugfs_create_dir(dev_name(rtk_phy->dev), 855 phy_debug_root); 856 857 debugfs_create_file("parameter", 0444, rtk_phy->debug_dir, rtk_phy, 858 &rtk_usb2_parameter_fops); 859 860 return; 861 } 862 863 static inline void remove_debug_files(struct rtk_phy *rtk_phy) 864 { 865 debugfs_remove_recursive(rtk_phy->debug_dir); 866 } 867 #else 868 static inline void create_debug_files(struct rtk_phy *rtk_phy) { } 869 static inline void remove_debug_files(struct rtk_phy *rtk_phy) { } 870 #endif /* CONFIG_DEBUG_FS */ 871 872 static int get_phy_data_by_efuse(struct rtk_phy *rtk_phy, 873 struct phy_parameter *phy_parameter, int index) 874 { 875 struct phy_cfg *phy_cfg = rtk_phy->phy_cfg; 876 u8 value = 0; 877 struct nvmem_cell *cell; 878 struct soc_device_attribute rtk_soc_groot[] = { 879 { .family = "Realtek Groot",}, 880 { /* empty */ } }; 881 882 if (!phy_cfg->check_efuse) 883 goto out; 884 885 /* Read efuse for usb dc cal */ 886 cell = nvmem_cell_get(rtk_phy->dev, "usb-dc-cal"); 887 if (IS_ERR(cell)) { 888 dev_dbg(rtk_phy->dev, "%s no usb-dc-cal: %ld\n", 889 __func__, PTR_ERR(cell)); 890 } else { 891 unsigned char *buf; 892 size_t buf_size; 893 894 buf = nvmem_cell_read(cell, &buf_size); 895 if (!IS_ERR(buf)) { 896 value = buf[0] & phy_cfg->dc_driving_mask; 897 kfree(buf); 898 } 899 nvmem_cell_put(cell); 900 } 901 902 if (phy_cfg->check_efuse_version == CHECK_EFUSE_V1) { 903 int rate = phy_cfg->efuse_dc_driving_rate; 904 905 if (value <= EFUS_USB_DC_CAL_MAX) 906 phy_parameter->efuse_usb_dc_cal = (int8_t)(value * rate); 907 else 908 phy_parameter->efuse_usb_dc_cal = -(int8_t) 909 ((EFUS_USB_DC_CAL_MAX & value) * rate); 910 911 if (soc_device_match(rtk_soc_groot)) { 912 dev_dbg(rtk_phy->dev, "For groot IC we need a workaround to adjust efuse_usb_dc_cal\n"); 913 914 /* We don't multiple dc_cal_rate=2 for positive dc cal compensate */ 915 if (value <= EFUS_USB_DC_CAL_MAX) 916 phy_parameter->efuse_usb_dc_cal = (int8_t)(value); 917 918 /* We set max dc cal compensate is 0x8 if otp is 0x7 */ 919 if (value == 0x7) 920 phy_parameter->efuse_usb_dc_cal = (int8_t)(value + 1); 921 } 922 } else { /* for CHECK_EFUSE_V2 */ 923 phy_parameter->efuse_usb_dc_cal = value & phy_cfg->dc_driving_mask; 924 } 925 926 /* Read efuse for usb dc disconnect level */ 927 value = 0; 928 cell = nvmem_cell_get(rtk_phy->dev, "usb-dc-dis"); 929 if (IS_ERR(cell)) { 930 dev_dbg(rtk_phy->dev, "%s no usb-dc-dis: %ld\n", 931 __func__, PTR_ERR(cell)); 932 } else { 933 unsigned char *buf; 934 size_t buf_size; 935 936 buf = nvmem_cell_read(cell, &buf_size); 937 if (!IS_ERR(buf)) { 938 value = buf[0] & phy_cfg->dc_disconnect_mask; 939 kfree(buf); 940 } 941 nvmem_cell_put(cell); 942 } 943 944 if (phy_cfg->check_efuse_version == CHECK_EFUSE_V1) { 945 int rate = phy_cfg->efuse_dc_disconnect_rate; 946 947 if (value <= EFUS_USB_DC_DIS_MAX) 948 phy_parameter->efuse_usb_dc_dis = (int8_t)(value * rate); 949 else 950 phy_parameter->efuse_usb_dc_dis = -(int8_t) 951 ((EFUS_USB_DC_DIS_MAX & value) * rate); 952 } else { /* for CHECK_EFUSE_V2 */ 953 phy_parameter->efuse_usb_dc_dis = value & phy_cfg->dc_disconnect_mask; 954 } 955 956 out: 957 return 0; 958 } 959 960 static int parse_phy_data(struct rtk_phy *rtk_phy) 961 { 962 struct device *dev = rtk_phy->dev; 963 struct device_node *np = dev->of_node; 964 struct phy_parameter *phy_parameter; 965 int ret = 0; 966 int index; 967 968 rtk_phy->phy_parameter = devm_kzalloc(dev, sizeof(struct phy_parameter) * 969 rtk_phy->num_phy, GFP_KERNEL); 970 if (!rtk_phy->phy_parameter) 971 return -ENOMEM; 972 973 for (index = 0; index < rtk_phy->num_phy; index++) { 974 phy_parameter = &((struct phy_parameter *)rtk_phy->phy_parameter)[index]; 975 976 phy_parameter->phy_reg.reg_wrap_vstatus = of_iomap(np, 0); 977 phy_parameter->phy_reg.reg_gusb2phyacc0 = of_iomap(np, 1) + index; 978 phy_parameter->phy_reg.vstatus_index = index; 979 980 if (of_property_read_bool(np, "realtek,inverse-hstx-sync-clock")) 981 phy_parameter->inverse_hstx_sync_clock = true; 982 else 983 phy_parameter->inverse_hstx_sync_clock = false; 984 985 if (of_property_read_u32_index(np, "realtek,driving-level", 986 index, &phy_parameter->driving_level)) 987 phy_parameter->driving_level = DEFAULT_DC_DRIVING_VALUE; 988 989 if (of_property_read_u32_index(np, "realtek,driving-level-compensate", 990 index, &phy_parameter->driving_level_compensate)) 991 phy_parameter->driving_level_compensate = 0; 992 993 if (of_property_read_u32_index(np, "realtek,disconnection-compensate", 994 index, &phy_parameter->disconnection_compensate)) 995 phy_parameter->disconnection_compensate = 0; 996 997 get_phy_data_by_efuse(rtk_phy, phy_parameter, index); 998 999 update_dc_driving_level(rtk_phy, phy_parameter); 1000 1001 update_hs_clk_select(rtk_phy, phy_parameter); 1002 } 1003 1004 return ret; 1005 } 1006 1007 static int rtk_usb2phy_probe(struct platform_device *pdev) 1008 { 1009 struct rtk_phy *rtk_phy; 1010 struct device *dev = &pdev->dev; 1011 struct phy *generic_phy; 1012 struct phy_provider *phy_provider; 1013 const struct phy_cfg *phy_cfg; 1014 int ret = 0; 1015 1016 phy_cfg = of_device_get_match_data(dev); 1017 if (!phy_cfg) { 1018 dev_err(dev, "phy config are not assigned!\n"); 1019 return -EINVAL; 1020 } 1021 1022 rtk_phy = devm_kzalloc(dev, sizeof(*rtk_phy), GFP_KERNEL); 1023 if (!rtk_phy) 1024 return -ENOMEM; 1025 1026 rtk_phy->dev = &pdev->dev; 1027 rtk_phy->phy.dev = rtk_phy->dev; 1028 rtk_phy->phy.label = "rtk-usb2phy"; 1029 rtk_phy->phy.notify_port_status = rtk_phy_notify_port_status; 1030 1031 rtk_phy->phy_cfg = devm_kzalloc(dev, sizeof(*phy_cfg), GFP_KERNEL); 1032 1033 memcpy(rtk_phy->phy_cfg, phy_cfg, sizeof(*phy_cfg)); 1034 1035 rtk_phy->num_phy = phy_cfg->num_phy; 1036 1037 ret = parse_phy_data(rtk_phy); 1038 if (ret) 1039 goto err; 1040 1041 platform_set_drvdata(pdev, rtk_phy); 1042 1043 generic_phy = devm_phy_create(rtk_phy->dev, NULL, &ops); 1044 if (IS_ERR(generic_phy)) 1045 return PTR_ERR(generic_phy); 1046 1047 phy_set_drvdata(generic_phy, rtk_phy); 1048 1049 phy_provider = devm_of_phy_provider_register(rtk_phy->dev, 1050 of_phy_simple_xlate); 1051 if (IS_ERR(phy_provider)) 1052 return PTR_ERR(phy_provider); 1053 1054 ret = usb_add_phy_dev(&rtk_phy->phy); 1055 if (ret) 1056 goto err; 1057 1058 create_debug_files(rtk_phy); 1059 1060 err: 1061 return ret; 1062 } 1063 1064 static void rtk_usb2phy_remove(struct platform_device *pdev) 1065 { 1066 struct rtk_phy *rtk_phy = platform_get_drvdata(pdev); 1067 1068 remove_debug_files(rtk_phy); 1069 1070 usb_remove_phy(&rtk_phy->phy); 1071 } 1072 1073 static const struct phy_cfg rtd1295_phy_cfg = { 1074 .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE, 1075 .page0 = { [0] = {0xe0, 0x90}, 1076 [3] = {0xe3, 0x3a}, 1077 [4] = {0xe4, 0x68}, 1078 [6] = {0xe6, 0x91}, 1079 [13] = {0xf5, 0x81}, 1080 [15] = {0xf7, 0x02}, }, 1081 .page1_size = 8, 1082 .page1 = { /* default parameter */ }, 1083 .page2_size = 0, 1084 .page2 = { /* no parameter */ }, 1085 .num_phy = 1, 1086 .check_efuse = false, 1087 .check_efuse_version = CHECK_EFUSE_V1, 1088 .efuse_dc_driving_rate = 1, 1089 .dc_driving_mask = 0xf, 1090 .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE, 1091 .dc_disconnect_mask = 0xf, 1092 .usb_dc_disconnect_at_page0 = true, 1093 .do_toggle = true, 1094 .do_toggle_driving = false, 1095 .driving_updated_for_dev_dis = 0xf, 1096 .use_default_parameter = false, 1097 .is_double_sensitivity_mode = false, 1098 }; 1099 1100 static const struct phy_cfg rtd1395_phy_cfg = { 1101 .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE, 1102 .page0 = { [4] = {0xe4, 0xac}, 1103 [13] = {0xf5, 0x00}, 1104 [15] = {0xf7, 0x02}, }, 1105 .page1_size = 8, 1106 .page1 = { /* default parameter */ }, 1107 .page2_size = 0, 1108 .page2 = { /* no parameter */ }, 1109 .num_phy = 1, 1110 .check_efuse = false, 1111 .check_efuse_version = CHECK_EFUSE_V1, 1112 .efuse_dc_driving_rate = 1, 1113 .dc_driving_mask = 0xf, 1114 .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE, 1115 .dc_disconnect_mask = 0xf, 1116 .usb_dc_disconnect_at_page0 = true, 1117 .do_toggle = true, 1118 .do_toggle_driving = false, 1119 .driving_updated_for_dev_dis = 0xf, 1120 .use_default_parameter = false, 1121 .is_double_sensitivity_mode = false, 1122 }; 1123 1124 static const struct phy_cfg rtd1395_phy_cfg_2port = { 1125 .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE, 1126 .page0 = { [4] = {0xe4, 0xac}, 1127 [13] = {0xf5, 0x00}, 1128 [15] = {0xf7, 0x02}, }, 1129 .page1_size = 8, 1130 .page1 = { /* default parameter */ }, 1131 .page2_size = 0, 1132 .page2 = { /* no parameter */ }, 1133 .num_phy = 2, 1134 .check_efuse = false, 1135 .check_efuse_version = CHECK_EFUSE_V1, 1136 .efuse_dc_driving_rate = 1, 1137 .dc_driving_mask = 0xf, 1138 .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE, 1139 .dc_disconnect_mask = 0xf, 1140 .usb_dc_disconnect_at_page0 = true, 1141 .do_toggle = true, 1142 .do_toggle_driving = false, 1143 .driving_updated_for_dev_dis = 0xf, 1144 .use_default_parameter = false, 1145 .is_double_sensitivity_mode = false, 1146 }; 1147 1148 static const struct phy_cfg rtd1619_phy_cfg = { 1149 .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE, 1150 .page0 = { [4] = {0xe4, 0x68}, }, 1151 .page1_size = 8, 1152 .page1 = { /* default parameter */ }, 1153 .page2_size = 0, 1154 .page2 = { /* no parameter */ }, 1155 .num_phy = 1, 1156 .check_efuse = true, 1157 .check_efuse_version = CHECK_EFUSE_V1, 1158 .efuse_dc_driving_rate = 1, 1159 .dc_driving_mask = 0xf, 1160 .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE, 1161 .dc_disconnect_mask = 0xf, 1162 .usb_dc_disconnect_at_page0 = true, 1163 .do_toggle = true, 1164 .do_toggle_driving = false, 1165 .driving_updated_for_dev_dis = 0xf, 1166 .use_default_parameter = false, 1167 .is_double_sensitivity_mode = false, 1168 }; 1169 1170 static const struct phy_cfg rtd1319_phy_cfg = { 1171 .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE, 1172 .page0 = { [0] = {0xe0, 0x18}, 1173 [4] = {0xe4, 0x6a}, 1174 [7] = {0xe7, 0x71}, 1175 [13] = {0xf5, 0x15}, 1176 [15] = {0xf7, 0x32}, }, 1177 .page1_size = 8, 1178 .page1 = { [3] = {0xe3, 0x44}, }, 1179 .page2_size = MAX_USB_PHY_PAGE2_DATA_SIZE, 1180 .page2 = { [0] = {0xe0, 0x01}, }, 1181 .num_phy = 1, 1182 .check_efuse = true, 1183 .check_efuse_version = CHECK_EFUSE_V1, 1184 .efuse_dc_driving_rate = 1, 1185 .dc_driving_mask = 0xf, 1186 .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE, 1187 .dc_disconnect_mask = 0xf, 1188 .usb_dc_disconnect_at_page0 = true, 1189 .do_toggle = true, 1190 .do_toggle_driving = true, 1191 .driving_updated_for_dev_dis = 0xf, 1192 .use_default_parameter = false, 1193 .is_double_sensitivity_mode = true, 1194 }; 1195 1196 static const struct phy_cfg rtd1312c_phy_cfg = { 1197 .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE, 1198 .page0 = { [0] = {0xe0, 0x14}, 1199 [4] = {0xe4, 0x67}, 1200 [5] = {0xe5, 0x55}, }, 1201 .page1_size = 8, 1202 .page1 = { [3] = {0xe3, 0x23}, 1203 [6] = {0xe6, 0x58}, }, 1204 .page2_size = MAX_USB_PHY_PAGE2_DATA_SIZE, 1205 .page2 = { /* default parameter */ }, 1206 .num_phy = 1, 1207 .check_efuse = true, 1208 .check_efuse_version = CHECK_EFUSE_V1, 1209 .efuse_dc_driving_rate = 1, 1210 .dc_driving_mask = 0xf, 1211 .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE, 1212 .dc_disconnect_mask = 0xf, 1213 .usb_dc_disconnect_at_page0 = true, 1214 .do_toggle = true, 1215 .do_toggle_driving = true, 1216 .driving_updated_for_dev_dis = 0xf, 1217 .use_default_parameter = false, 1218 .is_double_sensitivity_mode = true, 1219 }; 1220 1221 static const struct phy_cfg rtd1619b_phy_cfg = { 1222 .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE, 1223 .page0 = { [0] = {0xe0, 0xa3}, 1224 [4] = {0xe4, 0x88}, 1225 [5] = {0xe5, 0x4f}, 1226 [6] = {0xe6, 0x02}, }, 1227 .page1_size = 8, 1228 .page1 = { [3] = {0xe3, 0x64}, }, 1229 .page2_size = MAX_USB_PHY_PAGE2_DATA_SIZE, 1230 .page2 = { [7] = {0xe7, 0x45}, }, 1231 .num_phy = 1, 1232 .check_efuse = true, 1233 .check_efuse_version = CHECK_EFUSE_V1, 1234 .efuse_dc_driving_rate = EFUS_USB_DC_CAL_RATE, 1235 .dc_driving_mask = 0x1f, 1236 .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE, 1237 .dc_disconnect_mask = 0xf, 1238 .usb_dc_disconnect_at_page0 = false, 1239 .do_toggle = true, 1240 .do_toggle_driving = true, 1241 .driving_updated_for_dev_dis = 0x8, 1242 .use_default_parameter = false, 1243 .is_double_sensitivity_mode = true, 1244 }; 1245 1246 static const struct phy_cfg rtd1319d_phy_cfg = { 1247 .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE, 1248 .page0 = { [0] = {0xe0, 0xa3}, 1249 [4] = {0xe4, 0x8e}, 1250 [5] = {0xe5, 0x4f}, 1251 [6] = {0xe6, 0x02}, }, 1252 .page1_size = MAX_USB_PHY_PAGE1_DATA_SIZE, 1253 .page1 = { [14] = {0xf5, 0x1}, }, 1254 .page2_size = MAX_USB_PHY_PAGE2_DATA_SIZE, 1255 .page2 = { [7] = {0xe7, 0x44}, }, 1256 .check_efuse = true, 1257 .num_phy = 1, 1258 .check_efuse_version = CHECK_EFUSE_V1, 1259 .efuse_dc_driving_rate = EFUS_USB_DC_CAL_RATE, 1260 .dc_driving_mask = 0x1f, 1261 .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE, 1262 .dc_disconnect_mask = 0xf, 1263 .usb_dc_disconnect_at_page0 = false, 1264 .do_toggle = true, 1265 .do_toggle_driving = false, 1266 .driving_updated_for_dev_dis = 0x8, 1267 .use_default_parameter = false, 1268 .is_double_sensitivity_mode = true, 1269 }; 1270 1271 static const struct phy_cfg rtd1315e_phy_cfg = { 1272 .page0_size = MAX_USB_PHY_PAGE0_DATA_SIZE, 1273 .page0 = { [0] = {0xe0, 0xa3}, 1274 [4] = {0xe4, 0x8c}, 1275 [5] = {0xe5, 0x4f}, 1276 [6] = {0xe6, 0x02}, }, 1277 .page1_size = MAX_USB_PHY_PAGE1_DATA_SIZE, 1278 .page1 = { [3] = {0xe3, 0x7f}, 1279 [14] = {0xf5, 0x01}, }, 1280 .page2_size = MAX_USB_PHY_PAGE2_DATA_SIZE, 1281 .page2 = { [7] = {0xe7, 0x44}, }, 1282 .num_phy = 1, 1283 .check_efuse = true, 1284 .check_efuse_version = CHECK_EFUSE_V2, 1285 .efuse_dc_driving_rate = EFUS_USB_DC_CAL_RATE, 1286 .dc_driving_mask = 0x1f, 1287 .efuse_dc_disconnect_rate = EFUS_USB_DC_DIS_RATE, 1288 .dc_disconnect_mask = 0xf, 1289 .usb_dc_disconnect_at_page0 = false, 1290 .do_toggle = true, 1291 .do_toggle_driving = false, 1292 .driving_updated_for_dev_dis = 0x8, 1293 .use_default_parameter = false, 1294 .is_double_sensitivity_mode = true, 1295 }; 1296 1297 static const struct of_device_id usbphy_rtk_dt_match[] = { 1298 { .compatible = "realtek,rtd1295-usb2phy", .data = &rtd1295_phy_cfg }, 1299 { .compatible = "realtek,rtd1312c-usb2phy", .data = &rtd1312c_phy_cfg }, 1300 { .compatible = "realtek,rtd1315e-usb2phy", .data = &rtd1315e_phy_cfg }, 1301 { .compatible = "realtek,rtd1319-usb2phy", .data = &rtd1319_phy_cfg }, 1302 { .compatible = "realtek,rtd1319d-usb2phy", .data = &rtd1319d_phy_cfg }, 1303 { .compatible = "realtek,rtd1395-usb2phy", .data = &rtd1395_phy_cfg }, 1304 { .compatible = "realtek,rtd1395-usb2phy-2port", .data = &rtd1395_phy_cfg_2port }, 1305 { .compatible = "realtek,rtd1619-usb2phy", .data = &rtd1619_phy_cfg }, 1306 { .compatible = "realtek,rtd1619b-usb2phy", .data = &rtd1619b_phy_cfg }, 1307 {}, 1308 }; 1309 MODULE_DEVICE_TABLE(of, usbphy_rtk_dt_match); 1310 1311 static struct platform_driver rtk_usb2phy_driver = { 1312 .probe = rtk_usb2phy_probe, 1313 .remove_new = rtk_usb2phy_remove, 1314 .driver = { 1315 .name = "rtk-usb2phy", 1316 .of_match_table = usbphy_rtk_dt_match, 1317 }, 1318 }; 1319 1320 module_platform_driver(rtk_usb2phy_driver); 1321 1322 MODULE_LICENSE("GPL"); 1323 MODULE_ALIAS("platform: rtk-usb2phy"); 1324 MODULE_AUTHOR("Stanley Chang <stanley_chang@realtek.com>"); 1325 MODULE_DESCRIPTION("Realtek usb 2.0 phy driver"); 1326