1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/phy/phy.h> 9 #include <linux/platform_device.h> 10 #include <linux/regulator/consumer.h> 11 #include <linux/reset.h> 12 13 #define USB_PHY_UTMI_CTRL0 (0x3c) 14 #define SLEEPM BIT(0) 15 #define OPMODE_MASK GENMASK(4, 3) 16 #define OPMODE_NONDRIVING BIT(3) 17 18 #define USB_PHY_UTMI_CTRL5 (0x50) 19 #define POR BIT(1) 20 21 #define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) 22 #define PHY_ENABLE BIT(0) 23 #define SIDDQ_SEL BIT(1) 24 #define SIDDQ BIT(2) 25 #define RETENABLEN BIT(3) 26 #define FSEL_MASK GENMASK(6, 4) 27 #define FSEL_19_2_MHZ_VAL (0x0) 28 #define FSEL_38_4_MHZ_VAL (0x4) 29 30 #define USB_PHY_CFG_CTRL_1 (0x58) 31 #define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1) 32 33 #define USB_PHY_CFG_CTRL_2 (0x5c) 34 #define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0) 35 #define DIV_7_0_19_2_MHZ_VAL (0x90) 36 #define DIV_7_0_38_4_MHZ_VAL (0xc8) 37 38 #define USB_PHY_CFG_CTRL_3 (0x60) 39 #define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) 40 #define DIV_11_8_19_2_MHZ_VAL (0x1) 41 #define DIV_11_8_38_4_MHZ_VAL (0x0) 42 43 #define PHY_CFG_PLL_REF_DIV GENMASK(7, 4) 44 #define PLL_REF_DIV_VAL (0x0) 45 46 #define USB_PHY_HS_PHY_CTRL2 (0x64) 47 #define VBUSVLDEXT0 BIT(0) 48 #define USB2_SUSPEND_N BIT(2) 49 #define USB2_SUSPEND_N_SEL BIT(3) 50 #define VBUS_DET_EXT_SEL BIT(4) 51 52 #define USB_PHY_CFG_CTRL_4 (0x68) 53 #define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0) 54 #define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2) 55 56 #define USB_PHY_CFG_CTRL_5 (0x6c) 57 #define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0) 58 #define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6) 59 60 #define USB_PHY_CFG_CTRL_6 (0x70) 61 #define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0) 62 63 #define USB_PHY_CFG_CTRL_7 (0x74) 64 65 #define USB_PHY_CFG_CTRL_8 (0x78) 66 #define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0) 67 #define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2) 68 #define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3) 69 #define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6) 70 71 #define USB_PHY_CFG_CTRL_9 (0x7c) 72 #define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0) 73 #define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3) 74 #define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5) 75 #define PHY_CFG_RCAL_BYPASS BIT(7) 76 77 #define USB_PHY_CFG_CTRL_10 (0x80) 78 79 #define USB_PHY_CFG0 (0x94) 80 #define DATAPATH_CTRL_OVERRIDE_EN BIT(0) 81 #define CMN_CTRL_OVERRIDE_EN BIT(1) 82 83 #define UTMI_PHY_CMN_CTRL0 (0x98) 84 #define TESTBURNIN BIT(6) 85 86 #define USB_PHY_FSEL_SEL (0xb8) 87 #define FSEL_SEL BIT(0) 88 89 #define USB_PHY_APB_ACCESS_CMD (0x130) 90 #define RW_ACCESS BIT(0) 91 #define APB_START_CMD BIT(1) 92 #define APB_LOGIC_RESET BIT(2) 93 94 #define USB_PHY_APB_ACCESS_STATUS (0x134) 95 #define ACCESS_DONE BIT(0) 96 #define TIMED_OUT BIT(1) 97 #define ACCESS_ERROR BIT(2) 98 #define ACCESS_IN_PROGRESS BIT(3) 99 100 #define USB_PHY_APB_ADDRESS (0x138) 101 #define APB_REG_ADDR_MASK GENMASK(7, 0) 102 103 #define USB_PHY_APB_WRDATA_LSB (0x13c) 104 #define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0) 105 106 #define USB_PHY_APB_WRDATA_MSB (0x140) 107 #define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4) 108 109 #define USB_PHY_APB_RDDATA_LSB (0x144) 110 #define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0) 111 112 #define USB_PHY_APB_RDDATA_MSB (0x148) 113 #define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4) 114 115 static const char * const eusb2_hsphy_vreg_names[] = { 116 "vdd", "vdda12", 117 }; 118 119 #define EUSB2_NUM_VREGS ARRAY_SIZE(eusb2_hsphy_vreg_names) 120 121 struct qcom_snps_eusb2_hsphy { 122 struct phy *phy; 123 void __iomem *base; 124 125 struct clk *ref_clk; 126 struct reset_control *phy_reset; 127 128 struct regulator_bulk_data vregs[EUSB2_NUM_VREGS]; 129 130 enum phy_mode mode; 131 }; 132 133 static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode) 134 { 135 struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); 136 137 phy->mode = mode; 138 139 return 0; 140 } 141 142 static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset, 143 u32 mask, u32 val) 144 { 145 u32 reg; 146 147 reg = readl_relaxed(base + offset); 148 reg &= ~mask; 149 reg |= val & mask; 150 writel_relaxed(reg, base + offset); 151 152 /* Ensure above write is completed */ 153 readl_relaxed(base + offset); 154 } 155 156 static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy) 157 { 158 /* default parameters: tx pre-emphasis */ 159 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, 160 PHY_CFG_TX_PREEMP_TUNE_MASK, 161 FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); 162 163 /* tx rise/fall time */ 164 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, 165 PHY_CFG_TX_RISE_TUNE_MASK, 166 FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2)); 167 168 /* source impedance adjustment */ 169 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, 170 PHY_CFG_TX_RES_TUNE_MASK, 171 FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1)); 172 173 /* dc voltage level adjustement */ 174 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8, 175 PHY_CFG_TX_HS_VREF_TUNE_MASK, 176 FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3)); 177 178 /* transmitter HS crossover adjustement */ 179 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8, 180 PHY_CFG_TX_HS_XV_TUNE_MASK, 181 FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); 182 } 183 184 static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy) 185 { 186 unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); 187 188 switch (ref_clk_freq) { 189 case 19200000: 190 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, 191 FSEL_MASK, 192 FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); 193 194 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2, 195 PHY_CFG_PLL_FB_DIV_7_0_MASK, 196 DIV_7_0_19_2_MHZ_VAL); 197 198 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, 199 PHY_CFG_PLL_FB_DIV_11_8_MASK, 200 DIV_11_8_19_2_MHZ_VAL); 201 break; 202 203 case 38400000: 204 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, 205 FSEL_MASK, 206 FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL)); 207 208 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2, 209 PHY_CFG_PLL_FB_DIV_7_0_MASK, 210 DIV_7_0_38_4_MHZ_VAL); 211 212 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, 213 PHY_CFG_PLL_FB_DIV_11_8_MASK, 214 DIV_11_8_38_4_MHZ_VAL); 215 break; 216 217 default: 218 dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq); 219 return -EINVAL; 220 } 221 222 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, 223 PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL); 224 225 return 0; 226 } 227 228 static int qcom_snps_eusb2_hsphy_init(struct phy *p) 229 { 230 struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); 231 int ret; 232 233 ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), phy->vregs); 234 if (ret) 235 return ret; 236 237 ret = clk_prepare_enable(phy->ref_clk); 238 if (ret) { 239 dev_err(&p->dev, "failed to enable ref clock, %d\n", ret); 240 goto disable_vreg; 241 } 242 243 ret = reset_control_assert(phy->phy_reset); 244 if (ret) { 245 dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret); 246 goto disable_ref_clk; 247 } 248 249 usleep_range(100, 150); 250 251 ret = reset_control_deassert(phy->phy_reset); 252 if (ret) { 253 dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret); 254 goto disable_ref_clk; 255 } 256 257 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG0, 258 CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN); 259 260 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR); 261 262 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, 263 PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN); 264 265 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_APB_ACCESS_CMD, 266 APB_LOGIC_RESET, APB_LOGIC_RESET); 267 268 qcom_snps_eusb2_hsphy_write_mask(phy->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0); 269 270 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_FSEL_SEL, 271 FSEL_SEL, FSEL_SEL); 272 273 /* update ref_clk related registers */ 274 ret = qcom_eusb2_ref_clk_init(phy); 275 if (ret) 276 goto disable_ref_clk; 277 278 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_1, 279 PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 280 FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1)); 281 282 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4, 283 PHY_CFG_PLL_INT_CNTRL_MASK, 284 FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8)); 285 286 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4, 287 PHY_CFG_PLL_GMP_CNTRL_MASK, 288 FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1)); 289 290 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5, 291 PHY_CFG_PLL_PROP_CNTRL_MASK, 292 FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10)); 293 294 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_6, 295 PHY_CFG_PLL_VCO_CNTRL_MASK, 296 FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0)); 297 298 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5, 299 PHY_CFG_PLL_VREF_TUNE_MASK, 300 FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1)); 301 302 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, 303 VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL); 304 305 /* set default parameters */ 306 qcom_eusb2_default_parameters(phy); 307 308 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, 309 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, 310 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); 311 312 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM); 313 314 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, 315 SIDDQ_SEL, SIDDQ_SEL); 316 317 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, 318 SIDDQ, 0); 319 320 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0); 321 322 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, 323 USB2_SUSPEND_N_SEL, 0); 324 325 return 0; 326 327 disable_ref_clk: 328 clk_disable_unprepare(phy->ref_clk); 329 330 disable_vreg: 331 regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs); 332 333 return ret; 334 } 335 336 static int qcom_snps_eusb2_hsphy_exit(struct phy *p) 337 { 338 struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); 339 340 clk_disable_unprepare(phy->ref_clk); 341 342 regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs); 343 344 return 0; 345 } 346 347 static const struct phy_ops qcom_snps_eusb2_hsphy_ops = { 348 .init = qcom_snps_eusb2_hsphy_init, 349 .exit = qcom_snps_eusb2_hsphy_exit, 350 .set_mode = qcom_snps_eusb2_hsphy_set_mode, 351 .owner = THIS_MODULE, 352 }; 353 354 static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev) 355 { 356 struct device *dev = &pdev->dev; 357 struct qcom_snps_eusb2_hsphy *phy; 358 struct phy_provider *phy_provider; 359 struct phy *generic_phy; 360 int ret, i; 361 int num; 362 363 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); 364 if (!phy) 365 return -ENOMEM; 366 367 phy->base = devm_platform_ioremap_resource(pdev, 0); 368 if (IS_ERR(phy->base)) 369 return PTR_ERR(phy->base); 370 371 phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL); 372 if (IS_ERR(phy->phy_reset)) 373 return PTR_ERR(phy->phy_reset); 374 375 phy->ref_clk = devm_clk_get(dev, "ref"); 376 if (IS_ERR(phy->ref_clk)) 377 return dev_err_probe(dev, PTR_ERR(phy->ref_clk), 378 "failed to get ref clk\n"); 379 380 num = ARRAY_SIZE(phy->vregs); 381 for (i = 0; i < num; i++) 382 phy->vregs[i].supply = eusb2_hsphy_vreg_names[i]; 383 384 ret = devm_regulator_bulk_get(dev, num, phy->vregs); 385 if (ret) 386 return dev_err_probe(dev, ret, 387 "failed to get regulator supplies\n"); 388 generic_phy = devm_phy_create(dev, NULL, &qcom_snps_eusb2_hsphy_ops); 389 if (IS_ERR(generic_phy)) { 390 dev_err(dev, "failed to create phy %d\n", ret); 391 return PTR_ERR(generic_phy); 392 } 393 394 dev_set_drvdata(dev, phy); 395 phy_set_drvdata(generic_phy, phy); 396 397 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 398 if (IS_ERR(phy_provider)) 399 return PTR_ERR(phy_provider); 400 401 dev_info(dev, "Registered Qcom-eUSB2 phy\n"); 402 403 return 0; 404 } 405 406 static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = { 407 { .compatible = "qcom,sm8550-snps-eusb2-phy", }, 408 { }, 409 }; 410 MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table); 411 412 static struct platform_driver qcom_snps_eusb2_hsphy_driver = { 413 .probe = qcom_snps_eusb2_hsphy_probe, 414 .driver = { 415 .name = "qcom-snps-eusb2-hsphy", 416 .of_match_table = qcom_snps_eusb2_hsphy_of_match_table, 417 }, 418 }; 419 420 module_platform_driver(qcom_snps_eusb2_hsphy_driver); 421 MODULE_DESCRIPTION("Qualcomm SNPS eUSB2 HS PHY driver"); 422 MODULE_LICENSE("GPL"); 423