1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/nvmem-consumer.h> 14 #include <linux/of.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 22 #include <dt-bindings/phy/phy-qcom-qusb2.h> 23 24 #define QUSB2PHY_PLL 0x0 25 #define QUSB2PHY_PLL_TEST 0x04 26 #define CLK_REF_SEL BIT(7) 27 28 #define QUSB2PHY_PLL_TUNE 0x08 29 #define QUSB2PHY_PLL_USER_CTL1 0x0c 30 #define QUSB2PHY_PLL_USER_CTL2 0x10 31 #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c 32 #define QUSB2PHY_PLL_PWR_CTRL 0x18 33 34 /* QUSB2PHY_PLL_STATUS register bits */ 35 #define PLL_LOCKED BIT(5) 36 37 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ 38 #define CORE_READY_STATUS BIT(0) 39 40 /* QUSB2PHY_PORT_POWERDOWN register bits */ 41 #define CLAMP_N_EN BIT(5) 42 #define FREEZIO_N BIT(1) 43 #define POWER_DOWN BIT(0) 44 45 /* QUSB2PHY_PWR_CTRL1 register bits */ 46 #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) 47 #define PWR_CTRL1_CLAMP_N_EN BIT(1) 48 49 #define QUSB2PHY_REFCLK_ENABLE BIT(0) 50 51 #define PHY_CLK_SCHEME_SEL BIT(0) 52 53 /* QUSB2PHY_INTR_CTRL register bits */ 54 #define DMSE_INTR_HIGH_SEL BIT(4) 55 #define DPSE_INTR_HIGH_SEL BIT(3) 56 #define CHG_DET_INTR_EN BIT(2) 57 #define DMSE_INTR_EN BIT(1) 58 #define DPSE_INTR_EN BIT(0) 59 60 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ 61 #define CORE_PLL_EN_FROM_RESET BIT(4) 62 #define CORE_RESET BIT(5) 63 #define CORE_RESET_MUX BIT(6) 64 65 /* QUSB2PHY_IMP_CTRL1 register bits */ 66 #define IMP_RES_OFFSET_MASK GENMASK(5, 0) 67 #define IMP_RES_OFFSET_SHIFT 0x0 68 69 /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ 70 #define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) 71 #define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 72 73 /* QUSB2PHY_CHG_CONTROL_2 register bits */ 74 #define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) 75 #define CHG_CTRL2_OFFSET_SHIFT 0x4 76 77 /* QUSB2PHY_PORT_TUNE1 register bits */ 78 #define HSTX_TRIM_MASK GENMASK(7, 4) 79 #define HSTX_TRIM_SHIFT 0x4 80 #define PREEMPH_WIDTH_HALF_BIT BIT(2) 81 #define PREEMPHASIS_EN_MASK GENMASK(1, 0) 82 #define PREEMPHASIS_EN_SHIFT 0x0 83 84 /* QUSB2PHY_PORT_TUNE2 register bits */ 85 #define HSDISC_TRIM_MASK GENMASK(1, 0) 86 #define HSDISC_TRIM_SHIFT 0x0 87 88 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 89 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c 90 #define QUSB2PHY_PLL_CMODE 0x2c 91 #define QUSB2PHY_PLL_LOCK_DELAY 0x184 92 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 93 #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 94 #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 95 #define QUSB2PHY_PWR_CTRL2 0x214 96 #define QUSB2PHY_IMP_CTRL1 0x220 97 #define QUSB2PHY_IMP_CTRL2 0x224 98 #define QUSB2PHY_CHG_CTRL2 0x23c 99 100 struct qusb2_phy_init_tbl { 101 unsigned int offset; 102 unsigned int val; 103 /* 104 * register part of layout ? 105 * if yes, then offset gives index in the reg-layout 106 */ 107 int in_layout; 108 }; 109 110 #define QUSB2_PHY_INIT_CFG(o, v) \ 111 { \ 112 .offset = o, \ 113 .val = v, \ 114 } 115 116 #define QUSB2_PHY_INIT_CFG_L(o, v) \ 117 { \ 118 .offset = o, \ 119 .val = v, \ 120 .in_layout = 1, \ 121 } 122 123 /* set of registers with offsets different per-PHY */ 124 enum qusb2phy_reg_layout { 125 QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, 126 QUSB2PHY_PLL_STATUS, 127 QUSB2PHY_PORT_TUNE1, 128 QUSB2PHY_PORT_TUNE2, 129 QUSB2PHY_PORT_TUNE3, 130 QUSB2PHY_PORT_TUNE4, 131 QUSB2PHY_PORT_TUNE5, 132 QUSB2PHY_PORT_TEST1, 133 QUSB2PHY_PORT_TEST2, 134 QUSB2PHY_PORT_POWERDOWN, 135 QUSB2PHY_INTR_CTRL, 136 }; 137 138 static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = { 139 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14), 140 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8), 141 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3), 142 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 143 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0), 144 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 145 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 146 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 147 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00), 148 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 149 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 150 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80), 151 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F), 152 }; 153 154 static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = { 155 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xc8), 156 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), 157 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 158 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0), 159 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 160 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 161 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 162 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 163 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 164 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 165 }; 166 167 static const unsigned int ipq6018_regs_layout[] = { 168 [QUSB2PHY_PLL_STATUS] = 0x38, 169 [QUSB2PHY_PORT_TUNE1] = 0x80, 170 [QUSB2PHY_PORT_TUNE2] = 0x84, 171 [QUSB2PHY_PORT_TUNE3] = 0x88, 172 [QUSB2PHY_PORT_TUNE4] = 0x8C, 173 [QUSB2PHY_PORT_TUNE5] = 0x90, 174 [QUSB2PHY_PORT_TEST1] = 0x98, 175 [QUSB2PHY_PORT_TEST2] = 0x9C, 176 [QUSB2PHY_PORT_POWERDOWN] = 0xB4, 177 [QUSB2PHY_INTR_CTRL] = 0xBC, 178 }; 179 180 static const unsigned int msm8996_regs_layout[] = { 181 [QUSB2PHY_PLL_STATUS] = 0x38, 182 [QUSB2PHY_PORT_TUNE1] = 0x80, 183 [QUSB2PHY_PORT_TUNE2] = 0x84, 184 [QUSB2PHY_PORT_TUNE3] = 0x88, 185 [QUSB2PHY_PORT_TUNE4] = 0x8c, 186 [QUSB2PHY_PORT_TUNE5] = 0x90, 187 [QUSB2PHY_PORT_TEST1] = 0xb8, 188 [QUSB2PHY_PORT_TEST2] = 0x9c, 189 [QUSB2PHY_PORT_POWERDOWN] = 0xb4, 190 [QUSB2PHY_INTR_CTRL] = 0xbc, 191 }; 192 193 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { 194 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), 195 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), 196 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 197 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0), 198 199 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 200 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 201 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 202 203 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 204 205 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 206 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 207 }; 208 209 static const unsigned int msm8998_regs_layout[] = { 210 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 211 [QUSB2PHY_PLL_STATUS] = 0x1a0, 212 [QUSB2PHY_PORT_TUNE1] = 0x23c, 213 [QUSB2PHY_PORT_TUNE2] = 0x240, 214 [QUSB2PHY_PORT_TUNE3] = 0x244, 215 [QUSB2PHY_PORT_TUNE4] = 0x248, 216 [QUSB2PHY_PORT_TEST1] = 0x24c, 217 [QUSB2PHY_PORT_TEST2] = 0x250, 218 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 219 [QUSB2PHY_INTR_CTRL] = 0x22c, 220 }; 221 222 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = { 223 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13), 224 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 225 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 226 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 227 228 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5), 229 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09), 230 231 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 232 }; 233 234 static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = { 235 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), 236 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), 237 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81), 238 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17), 239 240 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 241 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 242 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 243 244 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 245 246 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 247 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 248 }; 249 250 static const unsigned int qusb2_v2_regs_layout[] = { 251 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 252 [QUSB2PHY_PLL_STATUS] = 0x1a0, 253 [QUSB2PHY_PORT_TUNE1] = 0x240, 254 [QUSB2PHY_PORT_TUNE2] = 0x244, 255 [QUSB2PHY_PORT_TUNE3] = 0x248, 256 [QUSB2PHY_PORT_TUNE4] = 0x24c, 257 [QUSB2PHY_PORT_TUNE5] = 0x250, 258 [QUSB2PHY_PORT_TEST1] = 0x254, 259 [QUSB2PHY_PORT_TEST2] = 0x258, 260 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 261 [QUSB2PHY_INTR_CTRL] = 0x230, 262 }; 263 264 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { 265 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), 266 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 267 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 268 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 269 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 270 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), 271 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), 272 QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), 273 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), 274 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), 275 276 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), 277 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), 278 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), 279 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), 280 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), 281 282 QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), 283 }; 284 285 struct qusb2_phy_cfg { 286 const struct qusb2_phy_init_tbl *tbl; 287 /* number of entries in the table */ 288 unsigned int tbl_num; 289 /* offset to PHY_CLK_SCHEME register in TCSR map */ 290 unsigned int clk_scheme_offset; 291 292 /* array of registers with different offsets */ 293 const unsigned int *regs; 294 unsigned int mask_core_ready; 295 unsigned int disable_ctrl; 296 unsigned int autoresume_en; 297 298 /* true if PHY has PLL_TEST register to select clk_scheme */ 299 bool has_pll_test; 300 301 /* true if TUNE1 register must be updated by fused value, else TUNE2 */ 302 bool update_tune1_with_efuse; 303 304 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ 305 bool has_pll_override; 306 307 /* true if PHY default clk scheme is single-ended */ 308 bool se_clk_scheme_default; 309 }; 310 311 static const struct qusb2_phy_cfg msm8996_phy_cfg = { 312 .tbl = msm8996_init_tbl, 313 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 314 .regs = msm8996_regs_layout, 315 316 .has_pll_test = true, 317 .se_clk_scheme_default = true, 318 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 319 .mask_core_ready = PLL_LOCKED, 320 .autoresume_en = BIT(3), 321 }; 322 323 static const struct qusb2_phy_cfg msm8998_phy_cfg = { 324 .tbl = msm8998_init_tbl, 325 .tbl_num = ARRAY_SIZE(msm8998_init_tbl), 326 .regs = msm8998_regs_layout, 327 328 .disable_ctrl = POWER_DOWN, 329 .mask_core_ready = CORE_READY_STATUS, 330 .has_pll_override = true, 331 .se_clk_scheme_default = true, 332 .autoresume_en = BIT(0), 333 .update_tune1_with_efuse = true, 334 }; 335 336 static const struct qusb2_phy_cfg ipq6018_phy_cfg = { 337 .tbl = ipq6018_init_tbl, 338 .tbl_num = ARRAY_SIZE(ipq6018_init_tbl), 339 .regs = ipq6018_regs_layout, 340 341 .disable_ctrl = POWER_DOWN, 342 .mask_core_ready = PLL_LOCKED, 343 /* autoresume not used */ 344 .autoresume_en = BIT(0), 345 }; 346 347 static const struct qusb2_phy_cfg qcs615_phy_cfg = { 348 .tbl = qcs615_init_tbl, 349 .tbl_num = ARRAY_SIZE(qcs615_init_tbl), 350 .regs = ipq6018_regs_layout, 351 352 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 353 .mask_core_ready = PLL_LOCKED, 354 /* autoresume not used */ 355 .autoresume_en = BIT(0), 356 }; 357 358 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { 359 .tbl = qusb2_v2_init_tbl, 360 .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), 361 .regs = qusb2_v2_regs_layout, 362 363 .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | 364 POWER_DOWN), 365 .mask_core_ready = CORE_READY_STATUS, 366 .has_pll_override = true, 367 .se_clk_scheme_default = true, 368 .autoresume_en = BIT(0), 369 .update_tune1_with_efuse = true, 370 }; 371 372 static const struct qusb2_phy_cfg sdm660_phy_cfg = { 373 .tbl = msm8996_init_tbl, 374 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 375 .regs = msm8996_regs_layout, 376 377 .has_pll_test = true, 378 .se_clk_scheme_default = false, 379 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 380 .mask_core_ready = PLL_LOCKED, 381 .autoresume_en = BIT(3), 382 }; 383 384 static const struct qusb2_phy_cfg sm6115_phy_cfg = { 385 .tbl = sm6115_init_tbl, 386 .tbl_num = ARRAY_SIZE(sm6115_init_tbl), 387 .regs = msm8996_regs_layout, 388 389 .has_pll_test = true, 390 .se_clk_scheme_default = true, 391 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 392 .mask_core_ready = PLL_LOCKED, 393 .autoresume_en = BIT(3), 394 }; 395 396 static const char * const qusb2_phy_vreg_names[] = { 397 "vdd", "vdda-pll", "vdda-phy-dpdm", 398 }; 399 400 #define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names) 401 402 /* struct override_param - structure holding qusb2 v2 phy overriding param 403 * set override true if the device tree property exists and read and assign 404 * to value 405 */ 406 struct override_param { 407 bool override; 408 u8 value; 409 }; 410 411 /*struct override_params - structure holding qusb2 v2 phy overriding params 412 * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register 413 * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register 414 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register 415 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1 416 * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register 417 * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register 418 * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register 419 */ 420 struct override_params { 421 struct override_param imp_res_offset; 422 struct override_param hstx_trim; 423 struct override_param preemphasis; 424 struct override_param preemphasis_width; 425 struct override_param bias_ctrl; 426 struct override_param charge_ctrl; 427 struct override_param hsdisc_trim; 428 }; 429 430 /** 431 * struct qusb2_phy - structure holding qusb2 phy attributes 432 * 433 * @phy: generic phy 434 * @base: iomapped memory space for qubs2 phy 435 * 436 * @cfg_ahb_clk: AHB2PHY interface clock 437 * @ref_clk: phy reference clock 438 * @iface_clk: phy interface clock 439 * @phy_reset: phy reset control 440 * @vregs: regulator supplies bulk data 441 * 442 * @tcsr: TCSR syscon register map 443 * @cell: nvmem cell containing phy tuning value 444 * 445 * @overrides: pointer to structure for all overriding tuning params 446 * 447 * @cfg: phy config data 448 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme 449 * @phy_initialized: indicate if PHY has been initialized 450 * @mode: current PHY mode 451 */ 452 struct qusb2_phy { 453 struct phy *phy; 454 void __iomem *base; 455 456 struct clk *cfg_ahb_clk; 457 struct clk *ref_clk; 458 struct clk *iface_clk; 459 struct reset_control *phy_reset; 460 struct regulator_bulk_data vregs[QUSB2_NUM_VREGS]; 461 462 struct regmap *tcsr; 463 struct nvmem_cell *cell; 464 465 struct override_params overrides; 466 467 const struct qusb2_phy_cfg *cfg; 468 bool has_se_clk_scheme; 469 bool phy_initialized; 470 enum phy_mode mode; 471 }; 472 473 static inline void qusb2_write_mask(void __iomem *base, u32 offset, 474 u32 val, u32 mask) 475 { 476 u32 reg; 477 478 reg = readl(base + offset); 479 reg &= ~mask; 480 reg |= val & mask; 481 writel(reg, base + offset); 482 483 /* Ensure above write is completed */ 484 readl(base + offset); 485 } 486 487 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) 488 { 489 u32 reg; 490 491 reg = readl(base + offset); 492 reg |= val; 493 writel(reg, base + offset); 494 495 /* Ensure above write is completed */ 496 readl(base + offset); 497 } 498 499 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) 500 { 501 u32 reg; 502 503 reg = readl(base + offset); 504 reg &= ~val; 505 writel(reg, base + offset); 506 507 /* Ensure above write is completed */ 508 readl(base + offset); 509 } 510 511 static inline 512 void qcom_qusb2_phy_configure(void __iomem *base, 513 const unsigned int *regs, 514 const struct qusb2_phy_init_tbl tbl[], int num) 515 { 516 int i; 517 518 for (i = 0; i < num; i++) { 519 if (tbl[i].in_layout) 520 writel(tbl[i].val, base + regs[tbl[i].offset]); 521 else 522 writel(tbl[i].val, base + tbl[i].offset); 523 } 524 } 525 526 /* 527 * Update board specific PHY tuning override values if specified from 528 * device tree. 529 */ 530 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy) 531 { 532 const struct qusb2_phy_cfg *cfg = qphy->cfg; 533 struct override_params *or = &qphy->overrides; 534 535 if (or->imp_res_offset.override) 536 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, 537 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, 538 IMP_RES_OFFSET_MASK); 539 540 if (or->bias_ctrl.override) 541 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, 542 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, 543 BIAS_CTRL2_RES_OFFSET_MASK); 544 545 if (or->charge_ctrl.override) 546 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, 547 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, 548 CHG_CTRL2_OFFSET_MASK); 549 550 if (or->hstx_trim.override) 551 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 552 or->hstx_trim.value << HSTX_TRIM_SHIFT, 553 HSTX_TRIM_MASK); 554 555 if (or->preemphasis.override) 556 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 557 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, 558 PREEMPHASIS_EN_MASK); 559 560 if (or->preemphasis_width.override) { 561 if (or->preemphasis_width.value == 562 QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT) 563 qusb2_setbits(qphy->base, 564 cfg->regs[QUSB2PHY_PORT_TUNE1], 565 PREEMPH_WIDTH_HALF_BIT); 566 else 567 qusb2_clrbits(qphy->base, 568 cfg->regs[QUSB2PHY_PORT_TUNE1], 569 PREEMPH_WIDTH_HALF_BIT); 570 } 571 572 if (or->hsdisc_trim.override) 573 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 574 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, 575 HSDISC_TRIM_MASK); 576 } 577 578 /* 579 * Fetches HS Tx tuning value from nvmem and sets the 580 * QUSB2PHY_PORT_TUNE1/2 register. 581 * For error case, skip setting the value and use the default value. 582 */ 583 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) 584 { 585 struct device *dev = &qphy->phy->dev; 586 const struct qusb2_phy_cfg *cfg = qphy->cfg; 587 u8 *val, hstx_trim; 588 589 /* efuse register is optional */ 590 if (!qphy->cell) 591 return; 592 593 /* 594 * Read efuse register having TUNE2/1 parameter's high nibble. 595 * If efuse register shows value as 0x0 (indicating value is not 596 * fused), or if we fail to find a valid efuse register setting, 597 * then use default value for high nibble that we have already 598 * set while configuring the phy. 599 */ 600 val = nvmem_cell_read(qphy->cell, NULL); 601 if (IS_ERR(val)) { 602 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); 603 return; 604 } 605 hstx_trim = val[0]; 606 kfree(val); 607 if (!hstx_trim) { 608 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); 609 return; 610 } 611 612 /* Fused TUNE1/2 value is the higher nibble only */ 613 if (cfg->update_tune1_with_efuse) 614 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 615 hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK); 616 else 617 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 618 hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK); 619 } 620 621 static int qusb2_phy_set_mode(struct phy *phy, 622 enum phy_mode mode, int submode) 623 { 624 struct qusb2_phy *qphy = phy_get_drvdata(phy); 625 626 qphy->mode = mode; 627 628 return 0; 629 } 630 631 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev) 632 { 633 struct qusb2_phy *qphy = dev_get_drvdata(dev); 634 const struct qusb2_phy_cfg *cfg = qphy->cfg; 635 u32 intr_mask; 636 637 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); 638 639 if (!qphy->phy_initialized) { 640 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 641 return 0; 642 } 643 644 /* 645 * Enable DP/DM interrupts to detect line state changes based on current 646 * speed. In other words, enable the triggers _opposite_ of what the 647 * current D+/D- levels are e.g. if currently D+ high, D- low 648 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high 649 */ 650 intr_mask = DPSE_INTR_EN | DMSE_INTR_EN; 651 switch (qphy->mode) { 652 case PHY_MODE_USB_HOST_HS: 653 case PHY_MODE_USB_HOST_FS: 654 case PHY_MODE_USB_DEVICE_HS: 655 case PHY_MODE_USB_DEVICE_FS: 656 intr_mask |= DMSE_INTR_HIGH_SEL; 657 break; 658 case PHY_MODE_USB_HOST_LS: 659 case PHY_MODE_USB_DEVICE_LS: 660 intr_mask |= DPSE_INTR_HIGH_SEL; 661 break; 662 default: 663 /* No device connected, enable both DP/DM high interrupt */ 664 intr_mask |= DMSE_INTR_HIGH_SEL; 665 intr_mask |= DPSE_INTR_HIGH_SEL; 666 break; 667 } 668 669 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 670 671 /* hold core PLL into reset */ 672 if (cfg->has_pll_override) { 673 qusb2_setbits(qphy->base, 674 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 675 CORE_PLL_EN_FROM_RESET | CORE_RESET | 676 CORE_RESET_MUX); 677 } 678 679 /* enable phy auto-resume only if device is connected on bus */ 680 if (qphy->mode != PHY_MODE_INVALID) { 681 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 682 cfg->autoresume_en); 683 /* Autoresume bit has to be toggled in order to enable it */ 684 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 685 cfg->autoresume_en); 686 } 687 688 if (!qphy->has_se_clk_scheme) 689 clk_disable_unprepare(qphy->ref_clk); 690 691 clk_disable_unprepare(qphy->cfg_ahb_clk); 692 clk_disable_unprepare(qphy->iface_clk); 693 694 return 0; 695 } 696 697 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev) 698 { 699 struct qusb2_phy *qphy = dev_get_drvdata(dev); 700 const struct qusb2_phy_cfg *cfg = qphy->cfg; 701 int ret; 702 703 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); 704 705 if (!qphy->phy_initialized) { 706 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 707 return 0; 708 } 709 710 ret = clk_prepare_enable(qphy->iface_clk); 711 if (ret) { 712 dev_err(dev, "failed to enable iface_clk, %d\n", ret); 713 return ret; 714 } 715 716 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 717 if (ret) { 718 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret); 719 goto disable_iface_clk; 720 } 721 722 if (!qphy->has_se_clk_scheme) { 723 ret = clk_prepare_enable(qphy->ref_clk); 724 if (ret) { 725 dev_err(dev, "failed to enable ref clk, %d\n", ret); 726 goto disable_ahb_clk; 727 } 728 } 729 730 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 731 732 /* bring core PLL out of reset */ 733 if (cfg->has_pll_override) { 734 qusb2_clrbits(qphy->base, 735 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 736 CORE_RESET | CORE_RESET_MUX); 737 } 738 739 return 0; 740 741 disable_ahb_clk: 742 clk_disable_unprepare(qphy->cfg_ahb_clk); 743 disable_iface_clk: 744 clk_disable_unprepare(qphy->iface_clk); 745 746 return ret; 747 } 748 749 static int qusb2_phy_init(struct phy *phy) 750 { 751 struct qusb2_phy *qphy = phy_get_drvdata(phy); 752 const struct qusb2_phy_cfg *cfg = qphy->cfg; 753 unsigned int val = 0; 754 unsigned int clk_scheme; 755 int ret; 756 757 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); 758 759 /* turn on regulator supplies */ 760 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 761 if (ret) 762 return ret; 763 764 ret = clk_prepare_enable(qphy->iface_clk); 765 if (ret) { 766 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); 767 goto poweroff_phy; 768 } 769 770 /* enable ahb interface clock to program phy */ 771 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 772 if (ret) { 773 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); 774 goto disable_iface_clk; 775 } 776 777 /* Perform phy reset */ 778 ret = reset_control_assert(qphy->phy_reset); 779 if (ret) { 780 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); 781 goto disable_ahb_clk; 782 } 783 784 /* 100 us delay to keep PHY in reset mode */ 785 usleep_range(100, 150); 786 787 ret = reset_control_deassert(qphy->phy_reset); 788 if (ret) { 789 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); 790 goto disable_ahb_clk; 791 } 792 793 /* Disable the PHY */ 794 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 795 qphy->cfg->disable_ctrl); 796 797 if (cfg->has_pll_test) { 798 /* save reset value to override reference clock scheme later */ 799 val = readl(qphy->base + QUSB2PHY_PLL_TEST); 800 } 801 802 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, 803 cfg->tbl_num); 804 805 /* Override board specific PHY tuning values */ 806 qusb2_phy_override_phy_params(qphy); 807 808 /* Set efuse value for tuning the PHY */ 809 qusb2_phy_set_tune2_param(qphy); 810 811 /* Enable the PHY */ 812 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 813 POWER_DOWN); 814 815 /* Required to get phy pll lock successfully */ 816 usleep_range(150, 160); 817 818 /* 819 * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME 820 * register in the TCSR so, if there's none, use the default 821 * value hardcoded in the configuration. 822 */ 823 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default; 824 825 /* 826 * read TCSR_PHY_CLK_SCHEME register to check if single-ended 827 * clock scheme is selected. If yes, then disable differential 828 * ref_clk and use single-ended clock, otherwise use differential 829 * ref_clk only. 830 */ 831 if (qphy->tcsr) { 832 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, 833 &clk_scheme); 834 if (ret) { 835 dev_err(&phy->dev, "failed to read clk scheme reg\n"); 836 goto assert_phy_reset; 837 } 838 839 /* is it a differential clock scheme ? */ 840 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) { 841 dev_vdbg(&phy->dev, "%s(): select differential clk\n", 842 __func__); 843 qphy->has_se_clk_scheme = false; 844 } else { 845 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", 846 __func__); 847 } 848 } 849 850 if (!qphy->has_se_clk_scheme) { 851 ret = clk_prepare_enable(qphy->ref_clk); 852 if (ret) { 853 dev_err(&phy->dev, "failed to enable ref clk, %d\n", 854 ret); 855 goto assert_phy_reset; 856 } 857 } 858 859 if (cfg->has_pll_test) { 860 if (!qphy->has_se_clk_scheme) 861 val &= ~CLK_REF_SEL; 862 else 863 val |= CLK_REF_SEL; 864 865 writel(val, qphy->base + QUSB2PHY_PLL_TEST); 866 867 /* ensure above write is through */ 868 readl(qphy->base + QUSB2PHY_PLL_TEST); 869 } 870 871 /* Required to get phy pll lock successfully */ 872 usleep_range(100, 110); 873 874 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); 875 if (!(val & cfg->mask_core_ready)) { 876 dev_err(&phy->dev, 877 "QUSB2PHY pll lock failed: status reg = %x\n", val); 878 ret = -EBUSY; 879 goto disable_ref_clk; 880 } 881 qphy->phy_initialized = true; 882 883 return 0; 884 885 disable_ref_clk: 886 if (!qphy->has_se_clk_scheme) 887 clk_disable_unprepare(qphy->ref_clk); 888 assert_phy_reset: 889 reset_control_assert(qphy->phy_reset); 890 disable_ahb_clk: 891 clk_disable_unprepare(qphy->cfg_ahb_clk); 892 disable_iface_clk: 893 clk_disable_unprepare(qphy->iface_clk); 894 poweroff_phy: 895 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 896 897 return ret; 898 } 899 900 static int qusb2_phy_exit(struct phy *phy) 901 { 902 struct qusb2_phy *qphy = phy_get_drvdata(phy); 903 904 /* Disable the PHY */ 905 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], 906 qphy->cfg->disable_ctrl); 907 908 if (!qphy->has_se_clk_scheme) 909 clk_disable_unprepare(qphy->ref_clk); 910 911 reset_control_assert(qphy->phy_reset); 912 913 clk_disable_unprepare(qphy->cfg_ahb_clk); 914 clk_disable_unprepare(qphy->iface_clk); 915 916 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 917 918 qphy->phy_initialized = false; 919 920 return 0; 921 } 922 923 static const struct phy_ops qusb2_phy_gen_ops = { 924 .init = qusb2_phy_init, 925 .exit = qusb2_phy_exit, 926 .set_mode = qusb2_phy_set_mode, 927 .owner = THIS_MODULE, 928 }; 929 930 static const struct of_device_id qusb2_phy_of_match_table[] = { 931 { 932 .compatible = "qcom,ipq5424-qusb2-phy", 933 .data = &ipq6018_phy_cfg, 934 }, { 935 .compatible = "qcom,ipq6018-qusb2-phy", 936 .data = &ipq6018_phy_cfg, 937 }, { 938 .compatible = "qcom,ipq8074-qusb2-phy", 939 .data = &msm8996_phy_cfg, 940 }, { 941 .compatible = "qcom,ipq9574-qusb2-phy", 942 .data = &ipq6018_phy_cfg, 943 }, { 944 .compatible = "qcom,msm8953-qusb2-phy", 945 .data = &msm8996_phy_cfg, 946 }, { 947 .compatible = "qcom,msm8996-qusb2-phy", 948 .data = &msm8996_phy_cfg, 949 }, { 950 .compatible = "qcom,msm8998-qusb2-phy", 951 .data = &msm8998_phy_cfg, 952 }, { 953 .compatible = "qcom,qcs615-qusb2-phy", 954 .data = &qcs615_phy_cfg, 955 }, { 956 .compatible = "qcom,qcm2290-qusb2-phy", 957 .data = &sm6115_phy_cfg, 958 }, { 959 .compatible = "qcom,sdm660-qusb2-phy", 960 .data = &sdm660_phy_cfg, 961 }, { 962 .compatible = "qcom,sm4250-qusb2-phy", 963 .data = &sm6115_phy_cfg, 964 }, { 965 .compatible = "qcom,sm6115-qusb2-phy", 966 .data = &sm6115_phy_cfg, 967 }, { 968 /* 969 * Deprecated. Only here to support legacy device 970 * trees that didn't include "qcom,qusb2-v2-phy" 971 */ 972 .compatible = "qcom,sdm845-qusb2-phy", 973 .data = &qusb2_v2_phy_cfg, 974 }, { 975 .compatible = "qcom,qusb2-v2-phy", 976 .data = &qusb2_v2_phy_cfg, 977 }, 978 { }, 979 }; 980 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table); 981 982 static const struct dev_pm_ops qusb2_phy_pm_ops = { 983 SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend, 984 qusb2_phy_runtime_resume, NULL) 985 }; 986 987 static int qusb2_phy_probe(struct platform_device *pdev) 988 { 989 struct device *dev = &pdev->dev; 990 struct qusb2_phy *qphy; 991 struct phy_provider *phy_provider; 992 struct phy *generic_phy; 993 int ret, i; 994 int num; 995 u32 value; 996 struct override_params *or; 997 998 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 999 if (!qphy) 1000 return -ENOMEM; 1001 or = &qphy->overrides; 1002 1003 qphy->base = devm_platform_ioremap_resource(pdev, 0); 1004 if (IS_ERR(qphy->base)) 1005 return PTR_ERR(qphy->base); 1006 1007 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); 1008 if (IS_ERR(qphy->cfg_ahb_clk)) 1009 return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk), 1010 "failed to get cfg ahb clk\n"); 1011 1012 qphy->ref_clk = devm_clk_get(dev, "ref"); 1013 if (IS_ERR(qphy->ref_clk)) 1014 return dev_err_probe(dev, PTR_ERR(qphy->ref_clk), 1015 "failed to get ref clk\n"); 1016 1017 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); 1018 if (IS_ERR(qphy->iface_clk)) 1019 return PTR_ERR(qphy->iface_clk); 1020 1021 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); 1022 if (IS_ERR(qphy->phy_reset)) { 1023 dev_err(dev, "failed to get phy core reset\n"); 1024 return PTR_ERR(qphy->phy_reset); 1025 } 1026 1027 num = ARRAY_SIZE(qphy->vregs); 1028 for (i = 0; i < num; i++) 1029 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; 1030 1031 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); 1032 if (ret) 1033 return dev_err_probe(dev, ret, 1034 "failed to get regulator supplies\n"); 1035 1036 /* Get the specific init parameters of QMP phy */ 1037 qphy->cfg = of_device_get_match_data(dev); 1038 1039 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, 1040 "qcom,tcsr-syscon"); 1041 if (IS_ERR(qphy->tcsr)) { 1042 dev_dbg(dev, "failed to lookup TCSR regmap\n"); 1043 qphy->tcsr = NULL; 1044 } 1045 1046 qphy->cell = devm_nvmem_cell_get(dev, NULL); 1047 if (IS_ERR(qphy->cell)) { 1048 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) 1049 return -EPROBE_DEFER; 1050 qphy->cell = NULL; 1051 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); 1052 } 1053 1054 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", 1055 &value)) { 1056 or->imp_res_offset.value = (u8)value; 1057 or->imp_res_offset.override = true; 1058 } 1059 1060 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", 1061 &value)) { 1062 or->bias_ctrl.value = (u8)value; 1063 or->bias_ctrl.override = true; 1064 } 1065 1066 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", 1067 &value)) { 1068 or->charge_ctrl.value = (u8)value; 1069 or->charge_ctrl.override = true; 1070 } 1071 1072 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", 1073 &value)) { 1074 or->hstx_trim.value = (u8)value; 1075 or->hstx_trim.override = true; 1076 } 1077 1078 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", 1079 &value)) { 1080 or->preemphasis.value = (u8)value; 1081 or->preemphasis.override = true; 1082 } 1083 1084 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", 1085 &value)) { 1086 or->preemphasis_width.value = (u8)value; 1087 or->preemphasis_width.override = true; 1088 } 1089 1090 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", 1091 &value)) { 1092 or->hsdisc_trim.value = (u8)value; 1093 or->hsdisc_trim.override = true; 1094 } 1095 1096 pm_runtime_set_active(dev); 1097 pm_runtime_enable(dev); 1098 /* 1099 * Prevent runtime pm from being ON by default. Users can enable 1100 * it using power/control in sysfs. 1101 */ 1102 pm_runtime_forbid(dev); 1103 1104 generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops); 1105 if (IS_ERR(generic_phy)) { 1106 ret = PTR_ERR(generic_phy); 1107 dev_err(dev, "failed to create phy, %d\n", ret); 1108 pm_runtime_disable(dev); 1109 return ret; 1110 } 1111 qphy->phy = generic_phy; 1112 1113 dev_set_drvdata(dev, qphy); 1114 phy_set_drvdata(generic_phy, qphy); 1115 1116 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1117 if (IS_ERR(phy_provider)) 1118 pm_runtime_disable(dev); 1119 1120 return PTR_ERR_OR_ZERO(phy_provider); 1121 } 1122 1123 static struct platform_driver qusb2_phy_driver = { 1124 .probe = qusb2_phy_probe, 1125 .driver = { 1126 .name = "qcom-qusb2-phy", 1127 .pm = &qusb2_phy_pm_ops, 1128 .of_match_table = qusb2_phy_of_match_table, 1129 }, 1130 }; 1131 1132 module_platform_driver(qusb2_phy_driver); 1133 1134 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 1135 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver"); 1136 MODULE_LICENSE("GPL v2"); 1137