1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef QCOM_PHY_QMP_H_ 7 #define QCOM_PHY_QMP_H_ 8 9 #include "phy-qcom-qmp-qserdes-com.h" 10 #include "phy-qcom-qmp-qserdes-txrx.h" 11 12 #include "phy-qcom-qmp-qserdes-com-v2.h" 13 #include "phy-qcom-qmp-qserdes-txrx-v2.h" 14 15 #include "phy-qcom-qmp-qserdes-com-v3.h" 16 #include "phy-qcom-qmp-qserdes-txrx-v3.h" 17 18 #include "phy-qcom-qmp-qserdes-com-v4.h" 19 #include "phy-qcom-qmp-qserdes-txrx-v4.h" 20 #include "phy-qcom-qmp-qserdes-txrx-v4_20.h" 21 22 #include "phy-qcom-qmp-qserdes-com-v5.h" 23 #include "phy-qcom-qmp-qserdes-txrx-v5.h" 24 #include "phy-qcom-qmp-qserdes-txrx-v5_20.h" 25 #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h" 26 27 #include "phy-qcom-qmp-qserdes-com-v6.h" 28 #include "phy-qcom-qmp-qserdes-txrx-v6.h" 29 #include "phy-qcom-qmp-qserdes-txrx-v6_20.h" 30 #include "phy-qcom-qmp-qserdes-txrx-v6_n4.h" 31 #include "phy-qcom-qmp-qserdes-ln-shrd-v5.h" 32 #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h" 33 34 #include "phy-qcom-qmp-qserdes-com-v7.h" 35 #include "phy-qcom-qmp-qserdes-txrx-v7.h" 36 37 #include "phy-qcom-qmp-qserdes-com-v8.h" 38 #include "phy-qcom-qmp-usb43-qserdes-com-v8.h" 39 #include "phy-qcom-qmp-qserdes-txrx-v8.h" 40 #include "phy-qcom-qmp-qserdes-lalb-v8.h" 41 42 #include "phy-qcom-qmp-qserdes-pll.h" 43 44 #include "phy-qcom-qmp-pcs-v2.h" 45 46 #include "phy-qcom-qmp-pcs-v3.h" 47 48 #include "phy-qcom-qmp-pcs-v4.h" 49 50 #include "phy-qcom-qmp-pcs-v4_20.h" 51 52 #include "phy-qcom-qmp-pcs-v5.h" 53 54 #include "phy-qcom-qmp-pcs-v5_20.h" 55 56 #include "phy-qcom-qmp-pcs-v6.h" 57 58 #include "phy-qcom-qmp-pcs-v6-n4.h" 59 60 #include "phy-qcom-qmp-pcs-v6_20.h" 61 62 #include "phy-qcom-qmp-pcs-v7.h" 63 64 #include "phy-qcom-qmp-pcs-v8.h" 65 66 #include "phy-qcom-qmp-pcs-v8_50.h" 67 68 /* QPHY_SW_RESET bit */ 69 #define SW_RESET BIT(0) 70 /* QPHY_POWER_DOWN_CONTROL */ 71 #define SW_PWRDN BIT(0) 72 #define REFCLK_DRV_DSBL BIT(1) /* PCIe */ 73 74 /* QPHY_START_CONTROL bits */ 75 #define SERDES_START BIT(0) 76 #define PCS_START BIT(1) 77 78 /* QPHY_PCS_STATUS bit */ 79 #define PHYSTATUS BIT(6) 80 #define PHYSTATUS_4_20 BIT(7) 81 82 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 83 #define ARCVR_DTCT_EN BIT(0) 84 #define ALFPS_DTCT_EN BIT(1) 85 #define ARCVR_DTCT_EVENT_SEL BIT(4) 86 87 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 88 #define IRQ_CLEAR BIT(0) 89 90 /* QPHY_PCS_MISC_CLAMP_ENABLE register bits */ 91 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 92 93 #endif 94