1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef QCOM_PHY_QMP_H_ 7 #define QCOM_PHY_QMP_H_ 8 9 /* Only for QMP V2 PHY - QSERDES COM registers */ 10 #define QSERDES_COM_BG_TIMER 0x00c 11 #define QSERDES_COM_SSC_EN_CENTER 0x010 12 #define QSERDES_COM_SSC_ADJ_PER1 0x014 13 #define QSERDES_COM_SSC_ADJ_PER2 0x018 14 #define QSERDES_COM_SSC_PER1 0x01c 15 #define QSERDES_COM_SSC_PER2 0x020 16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024 17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028 18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 19 #define QSERDES_COM_CLK_ENABLE1 0x038 20 #define QSERDES_COM_SYS_CLK_CTRL 0x03c 21 #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 22 #define QSERDES_COM_PLL_IVCO 0x048 23 #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 24 #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 25 #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 26 #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 27 #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 28 #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 29 #define QSERDES_COM_BG_TRIM 0x070 30 #define QSERDES_COM_CLK_EP_DIV 0x074 31 #define QSERDES_COM_CP_CTRL_MODE0 0x078 32 #define QSERDES_COM_CP_CTRL_MODE1 0x07c 33 #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 34 #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 35 #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 36 #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 37 #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 38 #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 39 #define QSERDES_COM_RESETSM_CNTRL 0x0b4 40 #define QSERDES_COM_RESTRIM_CTRL 0x0bc 41 #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 42 #define QSERDES_COM_LOCK_CMP_EN 0x0c8 43 #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 44 #define QSERDES_COM_DEC_START_MODE0 0x0d0 45 #define QSERDES_COM_DEC_START_MODE1 0x0d4 46 #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 47 #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 48 #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 49 #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 50 #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 51 #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 52 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 53 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 54 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 55 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 56 #define QSERDES_COM_VCO_TUNE_CTRL 0x124 57 #define QSERDES_COM_VCO_TUNE_MAP 0x128 58 #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 59 #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 60 #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 61 #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 62 #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 63 #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 64 #define QSERDES_COM_BG_CTRL 0x170 65 #define QSERDES_COM_CLK_SELECT 0x174 66 #define QSERDES_COM_HSCLK_SEL 0x178 67 #define QSERDES_COM_CORECLK_DIV 0x184 68 #define QSERDES_COM_CORE_CLK_EN 0x18c 69 #define QSERDES_COM_C_READY_STATUS 0x190 70 #define QSERDES_COM_CMN_CONFIG 0x194 71 #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 72 #define QSERDES_COM_DEBUG_BUS0 0x1a0 73 #define QSERDES_COM_DEBUG_BUS1 0x1a4 74 #define QSERDES_COM_DEBUG_BUS2 0x1a8 75 #define QSERDES_COM_DEBUG_BUS3 0x1ac 76 #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 77 #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 78 79 /* Only for QMP V2 PHY - TX registers */ 80 #define QSERDES_TX_EMP_POST1_LVL 0x018 81 #define QSERDES_TX_SLEW_CNTL 0x040 82 #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 83 #define QSERDES_TX_DEBUG_BUS_SEL 0x064 84 #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 85 #define QSERDES_TX_LANE_MODE 0x094 86 #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 87 88 /* Only for QMP V2 PHY - RX registers */ 89 #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 90 #define QSERDES_RX_UCDR_SO_GAIN 0x01c 91 #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 92 #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 93 #define QSERDES_RX_RX_TERM_BW 0x090 94 #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 95 #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 96 #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 97 #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 98 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 99 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 100 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 101 #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 102 #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 103 #define QSERDES_RX_SIGDET_ENABLES 0x110 104 #define QSERDES_RX_SIGDET_CNTRL 0x114 105 #define QSERDES_RX_SIGDET_LVL 0x118 106 #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 107 #define QSERDES_RX_RX_BAND 0x120 108 #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 109 110 /* Only for QMP V2 PHY - PCS registers */ 111 #define QPHY_POWER_DOWN_CONTROL 0x04 112 #define QPHY_TXDEEMPH_M6DB_V0 0x24 113 #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 114 #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 115 #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 116 #define QPHY_POWER_STATE_CONFIG1 0x60 117 #define QPHY_POWER_STATE_CONFIG2 0x64 118 #define QPHY_POWER_STATE_CONFIG4 0x6c 119 #define QPHY_LOCK_DETECT_CONFIG1 0x80 120 #define QPHY_LOCK_DETECT_CONFIG2 0x84 121 #define QPHY_LOCK_DETECT_CONFIG3 0x88 122 #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 123 #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 124 #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 125 #define QPHY_OSC_DTCT_ACTIONS 0x1AC 126 #define QPHY_RX_SIGDET_LVL 0x1D8 127 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 128 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 129 130 /* Only for QMP V3 & V4 PHY - DP COM registers */ 131 #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 132 #define QPHY_V3_DP_COM_SW_RESET 0x04 133 #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 134 #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 135 #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 136 #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 137 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 138 139 /* Only for QMP V3 PHY - QSERDES COM registers */ 140 #define QSERDES_V3_COM_ATB_SEL1 0x000 141 #define QSERDES_V3_COM_ATB_SEL2 0x004 142 #define QSERDES_V3_COM_FREQ_UPDATE 0x008 143 #define QSERDES_V3_COM_BG_TIMER 0x00c 144 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 145 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 146 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 147 #define QSERDES_V3_COM_SSC_PER1 0x01c 148 #define QSERDES_V3_COM_SSC_PER2 0x020 149 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 150 #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 151 #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 152 # define QSERDES_V3_COM_BIAS_EN 0x0001 153 # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 154 # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 155 # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 156 # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 157 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 158 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 159 #define QSERDES_V3_COM_CLK_ENABLE1 0x038 160 #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 161 #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 162 #define QSERDES_V3_COM_PLL_IVCO 0x048 163 #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 164 #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 165 #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 166 #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 167 #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 168 #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 169 #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 170 #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 171 #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 172 #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 173 #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 174 #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 175 #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 176 #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 177 #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 178 #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 179 #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 180 #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 181 #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 182 #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 183 #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 184 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 185 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 186 #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 187 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 188 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 189 #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 190 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 191 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 192 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 193 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 194 #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 195 #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 196 #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 197 #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 198 #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 199 #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 200 #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 201 #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 202 #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 203 #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 204 #define QSERDES_V3_COM_CLK_SELECT 0x138 205 #define QSERDES_V3_COM_HSCLK_SEL 0x13c 206 #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 207 #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 208 #define QSERDES_V3_COM_CORE_CLK_EN 0x154 209 #define QSERDES_V3_COM_C_READY_STATUS 0x158 210 #define QSERDES_V3_COM_CMN_CONFIG 0x15c 211 #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 212 #define QSERDES_V3_COM_DEBUG_BUS0 0x168 213 #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 214 #define QSERDES_V3_COM_DEBUG_BUS2 0x170 215 #define QSERDES_V3_COM_DEBUG_BUS3 0x174 216 #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 217 #define QSERDES_V3_COM_CMN_MODE 0x184 218 219 /* Only for QMP V3 PHY - TX registers */ 220 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 221 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 222 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 223 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 224 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 225 226 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c 227 # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 228 # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 229 230 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 231 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 232 233 #define QSERDES_V3_TX_TX_BAND 0x02c 234 #define QSERDES_V3_TX_SLEW_CNTL 0x030 235 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034 236 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 237 #define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 238 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 239 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 240 #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 241 #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 242 #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 243 #define QSERDES_V3_TX_TX_POL_INV 0x064 244 #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 245 #define QSERDES_V3_TX_LANE_MODE_1 0x08c 246 #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 247 #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 248 #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 249 #define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 250 251 /* Only for QMP V3 PHY - RX registers */ 252 #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 253 #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 254 #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 255 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 256 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 257 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 258 #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 259 #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 260 #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 261 #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 262 #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 263 #define QSERDES_V3_RX_RX_TERM_BW 0x07c 264 #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 265 #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 266 #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 267 #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 268 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 269 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 270 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 271 #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 272 #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 273 #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 274 #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 275 #define QSERDES_V3_RX_SIGDET_LVL 0x108 276 #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 277 #define QSERDES_V3_RX_RX_BAND 0x110 278 #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 279 #define QSERDES_V3_RX_RX_MODE_00 0x164 280 #define QSERDES_V3_RX_RX_MODE_01 0x168 281 282 /* Only for QMP V3 PHY - PCS registers */ 283 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 284 #define QPHY_V3_PCS_TXMGN_V0 0x00c 285 #define QPHY_V3_PCS_TXMGN_V1 0x010 286 #define QPHY_V3_PCS_TXMGN_V2 0x014 287 #define QPHY_V3_PCS_TXMGN_V3 0x018 288 #define QPHY_V3_PCS_TXMGN_V4 0x01c 289 #define QPHY_V3_PCS_TXMGN_LS 0x020 290 #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 291 #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 292 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 293 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 294 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 295 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 296 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 297 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 298 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 299 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 300 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 301 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 302 #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 303 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 304 #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 305 #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 306 #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 307 #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 308 #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 309 #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 310 #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 311 #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 312 #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 313 #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 314 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 315 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 316 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 317 #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 318 #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 319 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 320 #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 321 #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 322 #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 323 #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 324 #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 325 #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 326 #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 327 #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 328 #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 329 #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 330 #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 331 #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 332 #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 333 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 334 #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 335 #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 336 #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 337 #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 338 #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 339 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 340 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 341 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 342 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 343 344 /* Only for QMP V3 PHY - PCS_MISC registers */ 345 #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 346 #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 347 #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 348 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 349 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 350 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 351 352 /* Only for QMP V3 PHY - DP PHY registers */ 353 #define QSERDES_V3_DP_PHY_REVISION_ID0 0x000 354 #define QSERDES_V3_DP_PHY_REVISION_ID1 0x004 355 #define QSERDES_V3_DP_PHY_REVISION_ID2 0x008 356 #define QSERDES_V3_DP_PHY_REVISION_ID3 0x00c 357 #define QSERDES_V3_DP_PHY_CFG 0x010 358 #define QSERDES_V3_DP_PHY_PD_CTL 0x018 359 # define DP_PHY_PD_CTL_PWRDN 0x001 360 # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 361 # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 362 # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 363 # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 364 # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 365 # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 366 #define QSERDES_V3_DP_PHY_MODE 0x01c 367 #define QSERDES_V3_DP_PHY_AUX_CFG0 0x020 368 #define QSERDES_V3_DP_PHY_AUX_CFG1 0x024 369 #define QSERDES_V3_DP_PHY_AUX_CFG2 0x028 370 #define QSERDES_V3_DP_PHY_AUX_CFG3 0x02c 371 #define QSERDES_V3_DP_PHY_AUX_CFG4 0x030 372 #define QSERDES_V3_DP_PHY_AUX_CFG5 0x034 373 #define QSERDES_V3_DP_PHY_AUX_CFG6 0x038 374 #define QSERDES_V3_DP_PHY_AUX_CFG7 0x03c 375 #define QSERDES_V3_DP_PHY_AUX_CFG8 0x040 376 #define QSERDES_V3_DP_PHY_AUX_CFG9 0x044 377 378 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 379 # define PHY_AUX_STOP_ERR_MASK 0x01 380 # define PHY_AUX_DEC_ERR_MASK 0x02 381 # define PHY_AUX_SYNC_ERR_MASK 0x04 382 # define PHY_AUX_ALIGN_ERR_MASK 0x08 383 # define PHY_AUX_REQ_ERR_MASK 0x10 384 385 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 386 #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 387 388 #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 389 #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 390 #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 391 392 #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 393 #define DP_PHY_SPARE0_MASK 0x0f 394 #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 395 396 #define QSERDES_V3_DP_PHY_STATUS 0x0c0 397 398 /* Only for QMP V4 PHY - QSERDES COM registers */ 399 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 400 #define QSERDES_V4_COM_SSC_PER1 0x01c 401 #define QSERDES_V4_COM_SSC_PER2 0x020 402 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 403 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 404 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 405 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 406 #define QSERDES_V4_COM_CLK_ENABLE1 0x048 407 #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 408 #define QSERDES_V4_COM_PLL_IVCO 0x058 409 #define QSERDES_V4_COM_CMN_IPTRIM 0x060 410 #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 411 #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 412 #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 413 #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 414 #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 415 #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 416 #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 417 #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 418 #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 419 #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 420 #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 421 #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 422 #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 423 #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 424 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 425 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 426 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 427 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 428 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 429 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 430 #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 431 #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 432 #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 433 #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 434 #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 435 #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 436 #define QSERDES_V4_COM_CLK_SELECT 0x154 437 #define QSERDES_V4_COM_HSCLK_SEL 0x158 438 #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 439 #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 440 #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 441 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 442 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 443 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 444 #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 445 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 446 447 /* Only for QMP V4 PHY - TX registers */ 448 #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 449 #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 450 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 451 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 452 #define QSERDES_V4_TX_LANE_MODE_1 0x84 453 #define QSERDES_V4_TX_LANE_MODE_2 0x88 454 #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 455 #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 456 #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 457 #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 458 #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 459 #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 460 #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 461 462 /* Only for QMP V4 PHY - RX registers */ 463 #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 464 #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 465 #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 466 #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 467 #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 468 #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 469 #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 470 #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 471 #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 472 #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 473 #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 474 #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 475 #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 476 #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 477 #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 478 #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 479 #define QSERDES_V4_RX_RX_TERM_BW 0x080 480 #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 481 #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 482 #define QSERDES_V4_RX_GM_CAL 0x0dc 483 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 484 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 485 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 486 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 487 #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 488 #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 489 #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 490 #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 491 #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 492 #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 493 #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 494 #define QSERDES_V4_RX_SIGDET_LVL 0x120 495 #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 496 #define QSERDES_V4_RX_RX_BAND 0x128 497 #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 498 #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 499 #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 500 #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 501 #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 502 #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 503 #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 504 #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 505 #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 506 #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 507 #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 508 #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 509 #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 510 #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 511 #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 512 #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 513 #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 514 #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 515 #define QSERDES_V4_RX_VTH_CODE 0x1c4 516 517 /* Only for QMP V4 PHY - UFS PCS registers */ 518 #define QPHY_V4_PCS_UFS_PHY_START 0x000 519 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 520 #define QPHY_V4_PCS_UFS_SW_RESET 0x008 521 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 522 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 523 #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 524 #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 525 #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 526 #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 527 #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 528 #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 529 #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 530 #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 531 #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 532 #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 533 #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 534 #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 535 #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 536 #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 537 #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 538 539 /* PCIE GEN3 COM registers */ 540 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 541 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 542 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 543 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 544 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 545 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 546 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 547 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 548 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 549 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 550 #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 551 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 552 #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 553 #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 554 #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 555 #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 556 #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 557 #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 558 #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 559 #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 560 #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 561 #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 562 #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 563 #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 564 #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 565 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 566 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 567 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 568 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 569 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 570 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 571 #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 572 #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 573 #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 574 #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 575 #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 576 #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 577 #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 578 #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 579 #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 580 #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 581 #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 582 #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 583 #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 584 #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 585 586 /* PCIE GEN3 QHP Lane registers */ 587 #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 588 #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 589 #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 590 #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 591 #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 592 #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 593 #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 594 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 595 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 596 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 597 #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 598 #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 599 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 600 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 601 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 602 #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 603 #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 604 #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 605 #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 606 #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 607 #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 608 #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 609 #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 610 #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 611 #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 612 #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 613 #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 614 #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 615 #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 616 #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 617 #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 618 #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 619 #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 620 #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 621 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 622 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 623 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 624 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 625 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 626 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 627 #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 628 #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 629 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 630 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 631 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 632 #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 633 #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 634 #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 635 #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 636 #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 637 #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 638 #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 639 #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 640 #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 641 #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 642 #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 643 644 /* PCIE GEN3 PCS registers */ 645 #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 646 #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 647 #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 648 #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 649 #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 650 #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 651 #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 652 653 /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 654 #define QPHY_V4_PCS_SW_RESET 0x000 655 #define QPHY_V4_PCS_REVISION_ID0 0x004 656 #define QPHY_V4_PCS_REVISION_ID1 0x008 657 #define QPHY_V4_PCS_REVISION_ID2 0x00c 658 #define QPHY_V4_PCS_REVISION_ID3 0x010 659 #define QPHY_V4_PCS_PCS_STATUS1 0x014 660 #define QPHY_V4_PCS_PCS_STATUS2 0x018 661 #define QPHY_V4_PCS_PCS_STATUS3 0x01c 662 #define QPHY_V4_PCS_PCS_STATUS4 0x020 663 #define QPHY_V4_PCS_PCS_STATUS5 0x024 664 #define QPHY_V4_PCS_PCS_STATUS6 0x028 665 #define QPHY_V4_PCS_PCS_STATUS7 0x02c 666 #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 667 #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 668 #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 669 #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 670 #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 671 #define QPHY_V4_PCS_START_CONTROL 0x044 672 #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 673 #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 674 #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 675 #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 676 #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 677 #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 678 #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 679 #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 680 #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 681 #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 682 #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 683 #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 684 #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 685 #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 686 #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 687 #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 688 #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 689 #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 690 #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 691 #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 692 #define QPHY_V4_PCS_FLL_CNTRL1 0x098 693 #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 694 #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 695 #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 696 #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 697 #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 698 #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 699 #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 700 #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 701 #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 702 #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 703 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 704 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 705 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 706 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 707 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 708 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 709 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 710 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 711 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 712 #define QPHY_V4_PCS_BIST_CTRL 0x0e8 713 #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 714 #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 715 #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 716 #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 717 #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 718 #define QPHY_V4_PCS_FIXED_PAT3 0x100 719 #define QPHY_V4_PCS_FIXED_PAT4 0x104 720 #define QPHY_V4_PCS_FIXED_PAT5 0x108 721 #define QPHY_V4_PCS_FIXED_PAT6 0x10c 722 #define QPHY_V4_PCS_FIXED_PAT7 0x110 723 #define QPHY_V4_PCS_FIXED_PAT8 0x114 724 #define QPHY_V4_PCS_FIXED_PAT9 0x118 725 #define QPHY_V4_PCS_FIXED_PAT10 0x11c 726 #define QPHY_V4_PCS_FIXED_PAT11 0x120 727 #define QPHY_V4_PCS_FIXED_PAT12 0x124 728 #define QPHY_V4_PCS_FIXED_PAT13 0x128 729 #define QPHY_V4_PCS_FIXED_PAT14 0x12c 730 #define QPHY_V4_PCS_FIXED_PAT15 0x130 731 #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 732 #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 733 #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 734 #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 735 #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 736 #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 737 #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 738 #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 739 #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 740 #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 741 #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 742 #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 743 #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 744 #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 745 #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 746 #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 747 #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 748 #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 749 #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 750 #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 751 #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 752 #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 753 #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 754 #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 755 #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 756 #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 757 #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 758 #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 759 #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 760 #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 761 #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 762 #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 763 #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 764 #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 765 #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 766 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 767 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 768 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 769 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 770 #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 771 #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 772 #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 773 #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 774 #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 775 #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 776 #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 777 #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 778 #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 779 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 780 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 781 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 782 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 783 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 784 #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 785 #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c 786 #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 787 #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 788 #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 789 #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c 790 #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 791 #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 792 #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 793 #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c 794 #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 795 #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 796 #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 797 #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c 798 #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 799 #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 800 #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 801 802 /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ 803 #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 804 #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 805 806 /* Only for QMP V4 PHY - PCS_MISC registers */ 807 #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 808 #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 809 #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 810 #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 811 #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 812 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 813 814 /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 815 #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 816 #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 817 #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 818 #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 819 #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 820 #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 821 #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 822 #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 823 #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 824 #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 825 #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 826 827 #endif 828