1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 #include <linux/usb/typec.h> 24 #include <linux/usb/typec_mux.h> 25 #include <dt-bindings/phy/phy-qcom-qmp.h> 26 27 #include "phy-qcom-qmp-common.h" 28 29 #include "phy-qcom-qmp.h" 30 #include "phy-qcom-qmp-pcs-misc-v3.h" 31 32 #include "phy-qcom-qmp-dp-phy.h" 33 #include "phy-qcom-qmp-dp-phy-v2.h" 34 35 #define PHY_INIT_COMPLETE_TIMEOUT 10000 36 #define SW_PORTSELECT_VAL BIT(0) 37 #define SW_PORTSELECT_MUX BIT(1) 38 39 /* set of registers with offsets different per-PHY */ 40 enum qphy_reg_layout { 41 /* PCS registers */ 42 QPHY_SW_RESET, 43 QPHY_START_CTRL, 44 QPHY_PCS_STATUS, 45 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 46 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 47 QPHY_PCS_POWER_DOWN_CONTROL, 48 /* Keep last to ensure regs_layout arrays are properly initialized */ 49 QPHY_LAYOUT_SIZE 50 }; 51 52 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 53 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 54 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 55 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 56 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 57 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 58 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 59 }; 60 61 static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = { 62 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 63 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 64 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 65 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 66 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 67 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 68 }; 69 70 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { 71 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 72 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 73 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 74 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), 75 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 76 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 77 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 78 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 79 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 80 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 81 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 82 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 83 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 84 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 85 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 86 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 87 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 88 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 89 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 90 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 91 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 92 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 93 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 94 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 95 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 96 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 97 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 98 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 99 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), 101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 103 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 109 }; 110 111 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { 112 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 113 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 114 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 115 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 116 }; 117 118 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { 119 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 120 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 121 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 122 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 123 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), 124 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 125 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), 126 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 127 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 128 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 129 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 130 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 131 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 132 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 133 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 134 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), 135 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 136 }; 137 138 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { 139 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 140 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 141 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 142 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 143 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 144 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 145 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 146 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 147 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 148 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 149 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 150 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 151 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 152 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 153 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 154 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 155 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 156 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 157 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 158 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 159 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 160 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 161 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), 162 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 163 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 164 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 165 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 166 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), 174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 177 }; 178 179 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { 180 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 181 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 182 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 183 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 184 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), 185 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), 186 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 187 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 188 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 189 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 190 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 191 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 192 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 193 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 194 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 195 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 196 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 197 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 198 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 199 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 200 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 201 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 202 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), 203 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 204 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 205 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 206 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 207 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 208 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 209 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 210 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 211 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 212 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 213 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 214 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 215 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 216 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), 217 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), 218 }; 219 220 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { 221 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 222 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 223 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 224 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 225 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), 226 }; 227 228 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { 229 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 230 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 231 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 232 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 233 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 234 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 235 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 236 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 237 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 238 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 239 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 240 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 241 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 242 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 243 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 244 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 245 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 246 }; 247 248 /* the only difference is QSERDES_V3_RX_UCDR_PI_CONTROLS */ 249 static const struct qmp_phy_init_tbl sdm660_usb3_rx_tbl[] = { 250 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 251 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), 252 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 253 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 254 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 255 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 256 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 257 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 258 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 259 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 260 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 261 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 262 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 263 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 264 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 265 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 266 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 267 }; 268 269 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { 270 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 271 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 272 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 273 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 274 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 275 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 277 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 278 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 279 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 280 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 291 }; 292 293 static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl[] = { 294 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 295 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x37), 296 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x00), 297 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 298 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 299 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x0e), 300 QMP_PHY_INIT_CFG(QSERDES_COM_BG_CTRL, 0x0f), 301 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06), 302 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 303 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 304 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 305 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 306 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 307 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x40), 308 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 309 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 310 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x08), 311 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x05), 312 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 313 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x00), 314 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x00), 315 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 316 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x0f), 317 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x02), 318 }; 319 320 static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_rbr[] = { 321 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x2c), 322 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), 323 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 324 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), 325 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), 326 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xbf), 327 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x21), 328 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 329 }; 330 331 static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_hbr[] = { 332 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x24), 333 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), 334 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 335 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), 336 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), 337 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x3f), 338 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x38), 339 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 340 }; 341 342 static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_hbr2[] = { 343 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x20), 344 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x8c), 345 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 346 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 347 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a), 348 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f), 349 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x70), 350 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 351 }; 352 353 static const struct qmp_phy_init_tbl qmp_v2_dp_tx_tbl[] = { 354 QMP_PHY_INIT_CFG(QSERDES_V2_TX_TRANSCEIVER_BIAS_EN, 0x1a), 355 QMP_PHY_INIT_CFG(QSERDES_V2_TX_VMODE_CTRL1, 0x40), 356 QMP_PHY_INIT_CFG(QSERDES_V2_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 357 QMP_PHY_INIT_CFG(QSERDES_V2_TX_INTERFACE_SELECT, 0x3d), 358 QMP_PHY_INIT_CFG(QSERDES_V2_TX_CLKBUF_ENABLE, 0x0f), 359 QMP_PHY_INIT_CFG(QSERDES_V2_TX_RESET_TSYNC_EN, 0x03), 360 QMP_PHY_INIT_CFG(QSERDES_V2_TX_TRAN_DRVR_EMP_EN, 0x03), 361 QMP_PHY_INIT_CFG(QSERDES_V2_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 362 QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_INTERFACE_MODE, 0x00), 363 QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_EMP_POST1_LVL, 0x2b), 364 QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_DRV_LVL, 0x2f), 365 QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_BAND, 0x4), 366 QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET_TX, 0x12), 367 QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET_RX, 0x12), 368 }; 369 370 struct qmp_usbc_offsets { 371 u16 serdes; 372 u16 pcs; 373 u16 pcs_misc; 374 u16 tx; 375 u16 rx; 376 /* for PHYs with >= 2 lanes */ 377 u16 tx2; 378 u16 rx2; 379 380 u16 dp_serdes; 381 u16 dp_txa; 382 u16 dp_txb; 383 u16 dp_dp_phy; 384 }; 385 386 struct qmp_usbc; 387 struct qmp_phy_cfg { 388 const struct qmp_usbc_offsets *offsets; 389 390 /* Init sequence for USB PHY blocks - serdes, tx, rx, pcs */ 391 const struct qmp_phy_init_tbl *serdes_tbl; 392 int serdes_tbl_num; 393 const struct qmp_phy_init_tbl *tx_tbl; 394 int tx_tbl_num; 395 const struct qmp_phy_init_tbl *rx_tbl; 396 int rx_tbl_num; 397 const struct qmp_phy_init_tbl *pcs_tbl; 398 int pcs_tbl_num; 399 400 /* Init sequence for DP PHY blocks - serdes, tx, rbr, hbr, hbr2 */ 401 const struct qmp_phy_init_tbl *dp_serdes_tbl; 402 int dp_serdes_tbl_num; 403 const struct qmp_phy_init_tbl *dp_tx_tbl; 404 int dp_tx_tbl_num; 405 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 406 int serdes_tbl_rbr_num; 407 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 408 int serdes_tbl_hbr_num; 409 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 410 int serdes_tbl_hbr2_num; 411 412 const u8 (*swing_tbl)[4][4]; 413 const u8 (*pre_emphasis_tbl)[4][4]; 414 415 /* DP PHY callbacks */ 416 void (*dp_aux_init)(struct qmp_usbc *qmp); 417 void (*configure_dp_tx)(struct qmp_usbc *qmp); 418 int (*configure_dp_phy)(struct qmp_usbc *qmp); 419 int (*calibrate_dp_phy)(struct qmp_usbc *qmp); 420 421 const char * const *reset_list; 422 int num_resets; 423 const struct regulator_bulk_data *vreg_list; 424 int num_vregs; 425 426 /* array of registers with different offsets */ 427 const unsigned int *regs; 428 }; 429 430 struct qmp_usbc { 431 struct device *dev; 432 433 const struct qmp_phy_cfg *cfg; 434 435 void __iomem *serdes; 436 void __iomem *pcs; 437 void __iomem *pcs_misc; 438 void __iomem *tx; 439 void __iomem *rx; 440 void __iomem *tx2; 441 void __iomem *rx2; 442 void __iomem *dp_dp_phy; 443 void __iomem *dp_tx; 444 void __iomem *dp_tx2; 445 void __iomem *dp_serdes; 446 447 struct clk *pipe_clk; 448 struct clk_fixed_rate pipe_clk_fixed; 449 450 struct clk_hw dp_link_hw; 451 struct clk_hw dp_pixel_hw; 452 struct clk_bulk_data *clks; 453 int num_clks; 454 int num_resets; 455 struct reset_control_bulk_data *resets; 456 struct regulator_bulk_data *vregs; 457 458 struct regmap *tcsr_map; 459 u32 vls_clamp_reg; 460 u32 dp_phy_mode_reg; 461 462 struct mutex phy_mutex; 463 464 struct phy *usb_phy; 465 enum phy_mode mode; 466 unsigned int usb_init_count; 467 468 struct phy *dp_phy; 469 unsigned int dp_aux_cfg; 470 struct phy_configure_opts_dp dp_opts; 471 unsigned int dp_init_count; 472 473 struct typec_switch_dev *sw; 474 enum typec_orientation orientation; 475 }; 476 477 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 478 { 479 u32 reg; 480 481 reg = readl(base + offset); 482 reg |= val; 483 writel(reg, base + offset); 484 485 /* ensure that above write is through */ 486 readl(base + offset); 487 } 488 489 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 490 { 491 u32 reg; 492 493 reg = readl(base + offset); 494 reg &= ~val; 495 writel(reg, base + offset); 496 497 /* ensure that above write is through */ 498 readl(base + offset); 499 } 500 501 /* list of clocks required by phy */ 502 static const char * const qmp_usbc_phy_clk_l[] = { 503 "aux", "cfg_ahb", "ref", "com_aux", 504 }; 505 506 /* list of resets */ 507 static const char * const usb3phy_legacy_reset_l[] = { 508 "phy", "common", 509 }; 510 511 static const char * const usb3phy_reset_l[] = { 512 "phy_phy", "phy", 513 }; 514 515 static const char * const usb3dpphy_reset_l[] = { 516 "phy_phy", "dp_phy", 517 }; 518 519 static const struct regulator_bulk_data qmp_phy_msm8998_vreg_l[] = { 520 { .supply = "vdda-phy", .init_load_uA = 68600 }, 521 { .supply = "vdda-pll", .init_load_uA = 14200 }, 522 }; 523 524 static const struct regulator_bulk_data qmp_phy_sm2290_vreg_l[] = { 525 { .supply = "vdda-phy", .init_load_uA = 66100 }, 526 { .supply = "vdda-pll", .init_load_uA = 13300 }, 527 }; 528 529 static const struct regulator_bulk_data qmp_phy_qcs615_vreg_l[] = { 530 { .supply = "vdda-phy", .init_load_uA = 50000 }, 531 { .supply = "vdda-pll", .init_load_uA = 20000 }, 532 }; 533 534 static const struct qmp_usbc_offsets qmp_usbc_offsets_v3_qcm2290 = { 535 .serdes = 0x0, 536 .pcs = 0xc00, 537 .pcs_misc = 0xa00, 538 .tx = 0x200, 539 .rx = 0x400, 540 .tx2 = 0x600, 541 .rx2 = 0x800, 542 }; 543 544 static const struct qmp_usbc_offsets qmp_usbc_usb3dp_offsets_qcs615 = { 545 .serdes = 0x0, 546 .pcs = 0xc00, 547 .pcs_misc = 0xa00, 548 .tx = 0x200, 549 .rx = 0x400, 550 .tx2 = 0x600, 551 .rx2 = 0x800, 552 .dp_serdes = 0x1c00, 553 .dp_txa = 0x1400, 554 .dp_txb = 0x1800, 555 .dp_dp_phy = 0x1000, 556 }; 557 558 static const u8 qmp_v2_dp_pre_emphasis_hbr2_rbr[4][4] = { 559 {0x00, 0x0b, 0x12, 0xff}, 560 {0x00, 0x0a, 0x12, 0xff}, 561 {0x00, 0x0c, 0xff, 0xff}, 562 {0xff, 0xff, 0xff, 0xff} 563 }; 564 565 static const u8 qmp_v2_dp_voltage_swing_hbr2_rbr[4][4] = { 566 {0x07, 0x0f, 0x14, 0xff}, 567 {0x11, 0x1d, 0x1f, 0xff}, 568 {0x18, 0x1f, 0xff, 0xff}, 569 {0xff, 0xff, 0xff, 0xff} 570 }; 571 572 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { 573 .offsets = &qmp_usbc_offsets_v3_qcm2290, 574 575 .serdes_tbl = msm8998_usb3_serdes_tbl, 576 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), 577 .tx_tbl = msm8998_usb3_tx_tbl, 578 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), 579 .rx_tbl = msm8998_usb3_rx_tbl, 580 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), 581 .pcs_tbl = msm8998_usb3_pcs_tbl, 582 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), 583 .reset_list = usb3phy_reset_l, 584 .num_resets = ARRAY_SIZE(usb3phy_reset_l), 585 .vreg_list = qmp_phy_msm8998_vreg_l, 586 .num_vregs = ARRAY_SIZE(qmp_phy_msm8998_vreg_l), 587 .regs = qmp_v3_usb3phy_regs_layout, 588 }; 589 590 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { 591 .offsets = &qmp_usbc_offsets_v3_qcm2290, 592 593 .serdes_tbl = qcm2290_usb3_serdes_tbl, 594 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 595 .tx_tbl = qcm2290_usb3_tx_tbl, 596 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 597 .rx_tbl = qcm2290_usb3_rx_tbl, 598 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 599 .pcs_tbl = qcm2290_usb3_pcs_tbl, 600 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 601 .reset_list = usb3phy_reset_l, 602 .num_resets = ARRAY_SIZE(usb3phy_reset_l), 603 .vreg_list = qmp_phy_sm2290_vreg_l, 604 .num_vregs = ARRAY_SIZE(qmp_phy_sm2290_vreg_l), 605 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 606 }; 607 608 static const struct qmp_phy_cfg sdm660_usb3phy_cfg = { 609 .offsets = &qmp_usbc_offsets_v3_qcm2290, 610 611 .serdes_tbl = qcm2290_usb3_serdes_tbl, 612 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 613 .tx_tbl = qcm2290_usb3_tx_tbl, 614 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 615 .rx_tbl = sdm660_usb3_rx_tbl, 616 .rx_tbl_num = ARRAY_SIZE(sdm660_usb3_rx_tbl), 617 .pcs_tbl = qcm2290_usb3_pcs_tbl, 618 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 619 .reset_list = usb3phy_reset_l, 620 .num_resets = ARRAY_SIZE(usb3phy_reset_l), 621 .vreg_list = qmp_phy_msm8998_vreg_l, 622 .num_vregs = ARRAY_SIZE(qmp_phy_msm8998_vreg_l), 623 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 624 }; 625 626 static const struct qmp_phy_cfg qcs615_usb3phy_cfg = { 627 .offsets = &qmp_usbc_offsets_v3_qcm2290, 628 629 .serdes_tbl = qcm2290_usb3_serdes_tbl, 630 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 631 .tx_tbl = qcm2290_usb3_tx_tbl, 632 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 633 .rx_tbl = qcm2290_usb3_rx_tbl, 634 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 635 .pcs_tbl = qcm2290_usb3_pcs_tbl, 636 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 637 .reset_list = usb3phy_reset_l, 638 .num_resets = ARRAY_SIZE(usb3phy_reset_l), 639 .vreg_list = qmp_phy_qcs615_vreg_l, 640 .num_vregs = ARRAY_SIZE(qmp_phy_qcs615_vreg_l), 641 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 642 }; 643 644 static void qmp_v2_dp_aux_init(struct qmp_usbc *qmp); 645 static void qmp_v2_configure_dp_tx(struct qmp_usbc *qmp); 646 static int qmp_v2_configure_dp_phy(struct qmp_usbc *qmp); 647 static int qmp_v2_calibrate_dp_phy(struct qmp_usbc *qmp); 648 649 static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = { 650 .offsets = &qmp_usbc_usb3dp_offsets_qcs615, 651 652 .serdes_tbl = qcm2290_usb3_serdes_tbl, 653 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 654 .tx_tbl = qcm2290_usb3_tx_tbl, 655 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 656 .rx_tbl = qcm2290_usb3_rx_tbl, 657 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 658 .pcs_tbl = qcm2290_usb3_pcs_tbl, 659 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 660 661 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 662 663 .dp_serdes_tbl = qmp_v2_dp_serdes_tbl, 664 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v2_dp_serdes_tbl), 665 .dp_tx_tbl = qmp_v2_dp_tx_tbl, 666 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v2_dp_tx_tbl), 667 668 .serdes_tbl_rbr = qmp_v2_dp_serdes_tbl_rbr, 669 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v2_dp_serdes_tbl_rbr), 670 .serdes_tbl_hbr = qmp_v2_dp_serdes_tbl_hbr, 671 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v2_dp_serdes_tbl_hbr), 672 .serdes_tbl_hbr2 = qmp_v2_dp_serdes_tbl_hbr2, 673 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v2_dp_serdes_tbl_hbr2), 674 675 .swing_tbl = &qmp_v2_dp_voltage_swing_hbr2_rbr, 676 .pre_emphasis_tbl = &qmp_v2_dp_pre_emphasis_hbr2_rbr, 677 678 .dp_aux_init = qmp_v2_dp_aux_init, 679 .configure_dp_tx = qmp_v2_configure_dp_tx, 680 .configure_dp_phy = qmp_v2_configure_dp_phy, 681 .calibrate_dp_phy = qmp_v2_calibrate_dp_phy, 682 683 .reset_list = usb3dpphy_reset_l, 684 .num_resets = ARRAY_SIZE(usb3dpphy_reset_l), 685 .vreg_list = qmp_phy_qcs615_vreg_l, 686 .num_vregs = ARRAY_SIZE(qmp_phy_qcs615_vreg_l), 687 }; 688 689 static void qmp_usbc_set_phy_mode(struct qmp_usbc *qmp, bool is_dp) 690 { 691 if (qmp->tcsr_map && qmp->dp_phy_mode_reg) 692 regmap_write(qmp->tcsr_map, qmp->dp_phy_mode_reg, is_dp); 693 } 694 695 static int qmp_usbc_com_init(struct phy *phy) 696 { 697 struct qmp_usbc *qmp = phy_get_drvdata(phy); 698 const struct qmp_phy_cfg *cfg = qmp->cfg; 699 int ret; 700 701 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 702 if (ret) { 703 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 704 return ret; 705 } 706 707 ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets); 708 if (ret) { 709 dev_err(qmp->dev, "reset assert failed\n"); 710 goto err_disable_regulators; 711 } 712 713 ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets); 714 if (ret) { 715 dev_err(qmp->dev, "reset deassert failed\n"); 716 goto err_disable_regulators; 717 } 718 719 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 720 if (ret) 721 goto err_assert_reset; 722 723 return 0; 724 725 err_assert_reset: 726 reset_control_bulk_assert(qmp->num_resets, qmp->resets); 727 err_disable_regulators: 728 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 729 730 return ret; 731 } 732 733 static int qmp_usbc_com_exit(struct phy *phy) 734 { 735 struct qmp_usbc *qmp = phy_get_drvdata(phy); 736 const struct qmp_phy_cfg *cfg = qmp->cfg; 737 738 reset_control_bulk_assert(qmp->num_resets, qmp->resets); 739 740 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 741 742 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 743 744 return 0; 745 } 746 747 static void qmp_v2_dp_aux_init(struct qmp_usbc *qmp) 748 { 749 writel(DP_PHY_PD_CTL_AUX_PWRDN | 750 DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | 751 DP_PHY_PD_CTL_PLL_PWRDN, 752 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 753 754 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 755 DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | 756 DP_PHY_PD_CTL_PLL_PWRDN, 757 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 758 759 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 760 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 761 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 762 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 763 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 764 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 765 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 766 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 767 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 768 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 769 qmp->dp_aux_cfg = 0; 770 771 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 772 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 773 PHY_AUX_REQ_ERR_MASK, 774 qmp->dp_dp_phy + QSERDES_V2_DP_PHY_AUX_INTERRUPT_MASK); 775 } 776 777 static int qmp_v2_configure_dp_swing(struct qmp_usbc *qmp) 778 { 779 const struct qmp_phy_cfg *cfg = qmp->cfg; 780 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 781 void __iomem *tx = qmp->dp_tx; 782 void __iomem *tx2 = qmp->dp_tx2; 783 unsigned int v_level = 0, p_level = 0; 784 u8 voltage_swing_cfg, pre_emphasis_cfg; 785 int i; 786 787 if (dp_opts->lanes > 4) { 788 dev_err(qmp->dev, "Invalid lane_num(%d)\n", dp_opts->lanes); 789 return -EINVAL; 790 } 791 792 for (i = 0; i < dp_opts->lanes; i++) { 793 v_level = max(v_level, dp_opts->voltage[i]); 794 p_level = max(p_level, dp_opts->pre[i]); 795 } 796 797 if (v_level > 4 || p_level > 4) { 798 dev_err(qmp->dev, "Invalid v(%d) | p(%d) level)\n", 799 v_level, p_level); 800 return -EINVAL; 801 } 802 803 voltage_swing_cfg = (*cfg->swing_tbl)[v_level][p_level]; 804 pre_emphasis_cfg = (*cfg->pre_emphasis_tbl)[v_level][p_level]; 805 806 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 807 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 808 809 if (voltage_swing_cfg == 0xff && pre_emphasis_cfg == 0xff) 810 return -EINVAL; 811 812 writel(voltage_swing_cfg, tx + QSERDES_V2_TX_TX_DRV_LVL); 813 writel(pre_emphasis_cfg, tx + QSERDES_V2_TX_TX_EMP_POST1_LVL); 814 writel(voltage_swing_cfg, tx2 + QSERDES_V2_TX_TX_DRV_LVL); 815 writel(pre_emphasis_cfg, tx2 + QSERDES_V2_TX_TX_EMP_POST1_LVL); 816 817 return 0; 818 } 819 820 static void qmp_usbc_configure_dp_mode(struct qmp_usbc *qmp) 821 { 822 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 823 u32 val; 824 825 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 826 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN; 827 828 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 829 830 if (reverse) 831 writel(0xc9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 832 else 833 writel(0xd9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 834 } 835 836 static int qmp_usbc_configure_dp_clocks(struct qmp_usbc *qmp) 837 { 838 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 839 u32 phy_vco_div; 840 unsigned long pixel_freq; 841 842 switch (dp_opts->link_rate) { 843 case 1620: 844 phy_vco_div = 0x1; 845 pixel_freq = 1620000000UL / 2; 846 break; 847 case 2700: 848 phy_vco_div = 0x1; 849 pixel_freq = 2700000000UL / 2; 850 break; 851 case 5400: 852 phy_vco_div = 0x2; 853 pixel_freq = 5400000000UL / 4; 854 break; 855 default: 856 dev_err(qmp->dev, "link rate:%d not supported\n", dp_opts->link_rate); 857 return -EINVAL; 858 } 859 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_VCO_DIV); 860 861 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 862 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 863 864 return 0; 865 } 866 867 static void qmp_v2_configure_dp_tx(struct qmp_usbc *qmp) 868 { 869 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 870 void __iomem *tx = qmp->dp_tx; 871 void __iomem *tx2 = qmp->dp_tx2; 872 873 /* program default setting first */ 874 writel(0x2a, tx + QSERDES_V2_TX_TX_DRV_LVL); 875 writel(0x20, tx + QSERDES_V2_TX_TX_EMP_POST1_LVL); 876 writel(0x2a, tx2 + QSERDES_V2_TX_TX_DRV_LVL); 877 writel(0x20, tx2 + QSERDES_V2_TX_TX_EMP_POST1_LVL); 878 879 if (dp_opts->link_rate >= 2700) { 880 writel(0xc4, tx + QSERDES_V2_TX_LANE_MODE_1); 881 writel(0xc4, tx2 + QSERDES_V2_TX_LANE_MODE_1); 882 } else { 883 writel(0xc6, tx + QSERDES_V2_TX_LANE_MODE_1); 884 writel(0xc6, tx2 + QSERDES_V2_TX_LANE_MODE_1); 885 } 886 887 qmp_v2_configure_dp_swing(qmp); 888 } 889 890 static int qmp_v2_configure_dp_phy(struct qmp_usbc *qmp) 891 { 892 u32 status; 893 int ret; 894 895 qmp_usbc_configure_dp_mode(qmp); 896 897 writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX0_TX1_LANE_CTL); 898 writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX2_TX3_LANE_CTL); 899 900 ret = qmp_usbc_configure_dp_clocks(qmp); 901 if (ret) 902 return ret; 903 904 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 905 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 906 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 907 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 908 909 writel(0x20, qmp->dp_serdes + QSERDES_COM_RESETSM_CNTRL); 910 911 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_C_READY_STATUS, 912 status, 913 ((status & BIT(0)) > 0), 914 500, 915 10000)) { 916 dev_err(qmp->dev, "C_READY not ready\n"); 917 return -ETIMEDOUT; 918 } 919 920 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS, 921 status, 922 ((status & BIT(0)) > 0), 923 500, 924 10000)){ 925 dev_err(qmp->dev, "FREQ_DONE not ready\n"); 926 return -ETIMEDOUT; 927 } 928 929 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS, 930 status, 931 ((status & BIT(1)) > 0), 932 500, 933 10000)){ 934 dev_err(qmp->dev, "PLL_LOCKED not ready\n"); 935 return -ETIMEDOUT; 936 } 937 938 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 939 940 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, 941 status, 942 ((status & BIT(0)) > 0), 943 500, 944 10000)){ 945 dev_err(qmp->dev, "TSYNC_DONE not ready\n"); 946 return -ETIMEDOUT; 947 } 948 949 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, 950 status, 951 ((status & BIT(1)) > 0), 952 500, 953 10000)){ 954 dev_err(qmp->dev, "PHY_READY not ready\n"); 955 return -ETIMEDOUT; 956 } 957 958 writel(0x3f, qmp->dp_tx + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); 959 writel(0x10, qmp->dp_tx + QSERDES_V2_TX_HIGHZ_DRVR_EN); 960 writel(0x0a, qmp->dp_tx + QSERDES_V2_TX_TX_POL_INV); 961 writel(0x3f, qmp->dp_tx2 + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); 962 writel(0x10, qmp->dp_tx2 + QSERDES_V2_TX_HIGHZ_DRVR_EN); 963 writel(0x0a, qmp->dp_tx2 + QSERDES_V2_TX_TX_POL_INV); 964 965 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 966 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 967 968 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, 969 status, 970 ((status & BIT(1)) > 0), 971 500, 972 10000)){ 973 dev_err(qmp->dev, "PHY_READY not ready\n"); 974 return -ETIMEDOUT; 975 } 976 977 return 0; 978 } 979 980 static int qmp_v2_calibrate_dp_phy(struct qmp_usbc *qmp) 981 { 982 static const u8 cfg1_settings[] = {0x13, 0x23, 0x1d}; 983 u8 val; 984 985 qmp->dp_aux_cfg++; 986 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 987 val = cfg1_settings[qmp->dp_aux_cfg]; 988 989 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 990 991 return 0; 992 } 993 994 static int qmp_usbc_usb_power_on(struct phy *phy) 995 { 996 struct qmp_usbc *qmp = phy_get_drvdata(phy); 997 const struct qmp_phy_cfg *cfg = qmp->cfg; 998 void __iomem *status; 999 unsigned int val; 1000 int ret; 1001 1002 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1003 1004 /* Use software based port select and switch on typec orientation */ 1005 val = SW_PORTSELECT_MUX; 1006 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 1007 val |= SW_PORTSELECT_VAL; 1008 writel(val, qmp->pcs_misc); 1009 1010 qmp_configure(qmp->dev, qmp->serdes, cfg->serdes_tbl, 1011 cfg->serdes_tbl_num); 1012 1013 ret = clk_prepare_enable(qmp->pipe_clk); 1014 if (ret) { 1015 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1016 return ret; 1017 } 1018 1019 /* Tx, Rx, and PCS configurations */ 1020 qmp_configure_lane(qmp->dev, qmp->tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 1021 qmp_configure_lane(qmp->dev, qmp->rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 1022 1023 qmp_configure_lane(qmp->dev, qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 1024 qmp_configure_lane(qmp->dev, qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 1025 1026 qmp_configure(qmp->dev, qmp->pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1027 1028 /* Pull PHY out of reset state */ 1029 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1030 1031 /* start SerDes and Phy-Coding-Sublayer */ 1032 qphy_setbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 1033 1034 status = qmp->pcs + cfg->regs[QPHY_PCS_STATUS]; 1035 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 1036 PHY_INIT_COMPLETE_TIMEOUT); 1037 if (ret) { 1038 dev_err(qmp->dev, "phy initialization timed-out\n"); 1039 goto err_disable_pipe_clk; 1040 } 1041 1042 return 0; 1043 1044 err_disable_pipe_clk: 1045 clk_disable_unprepare(qmp->pipe_clk); 1046 1047 return ret; 1048 } 1049 1050 static int qmp_usbc_usb_power_off(struct phy *phy) 1051 { 1052 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1053 const struct qmp_phy_cfg *cfg = qmp->cfg; 1054 1055 clk_disable_unprepare(qmp->pipe_clk); 1056 1057 /* PHY reset */ 1058 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1059 1060 /* stop SerDes and Phy-Coding-Sublayer */ 1061 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 1062 SERDES_START | PCS_START); 1063 1064 /* Put PHY into POWER DOWN state: active low */ 1065 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1066 SW_PWRDN); 1067 1068 return 0; 1069 } 1070 1071 static int qmp_usbc_check_phy_status(struct qmp_usbc *qmp, bool is_dp) 1072 { 1073 if ((is_dp && qmp->usb_init_count) || 1074 (!is_dp && qmp->dp_init_count)) { 1075 dev_err(qmp->dev, 1076 "PHY is configured for %s, can not enable %s\n", 1077 is_dp ? "USB" : "DP", is_dp ? "DP" : "USB"); 1078 return -EBUSY; 1079 } 1080 1081 return 0; 1082 } 1083 1084 static int qmp_usbc_usb_enable(struct phy *phy) 1085 { 1086 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1087 int ret; 1088 1089 mutex_lock(&qmp->phy_mutex); 1090 1091 ret = qmp_usbc_check_phy_status(qmp, false); 1092 if (ret) 1093 goto out_unlock; 1094 1095 ret = qmp_usbc_com_init(phy); 1096 if (ret) 1097 goto out_unlock; 1098 1099 qmp_usbc_set_phy_mode(qmp, false); 1100 1101 ret = qmp_usbc_usb_power_on(phy); 1102 if (ret) { 1103 qmp_usbc_com_exit(phy); 1104 goto out_unlock; 1105 } 1106 1107 qmp->usb_init_count++; 1108 out_unlock: 1109 mutex_unlock(&qmp->phy_mutex); 1110 1111 return ret; 1112 } 1113 1114 static int qmp_usbc_usb_disable(struct phy *phy) 1115 { 1116 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1117 int ret; 1118 1119 qmp->usb_init_count--; 1120 ret = qmp_usbc_usb_power_off(phy); 1121 if (ret) 1122 return ret; 1123 return qmp_usbc_com_exit(phy); 1124 } 1125 1126 static int qmp_usbc_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 1127 { 1128 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1129 1130 qmp->mode = mode; 1131 1132 return 0; 1133 } 1134 1135 static int qmp_usbc_dp_enable(struct phy *phy) 1136 { 1137 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1138 const struct qmp_phy_cfg *cfg = qmp->cfg; 1139 int ret; 1140 1141 if (qmp->dp_init_count) { 1142 dev_err(qmp->dev, "DP already inited\n"); 1143 return 0; 1144 } 1145 1146 mutex_lock(&qmp->phy_mutex); 1147 1148 ret = qmp_usbc_check_phy_status(qmp, true); 1149 if (ret) 1150 goto dp_init_unlock; 1151 1152 ret = qmp_usbc_com_init(phy); 1153 if (ret) 1154 goto dp_init_unlock; 1155 1156 qmp_usbc_set_phy_mode(qmp, true); 1157 1158 cfg->dp_aux_init(qmp); 1159 1160 qmp->dp_init_count++; 1161 1162 dp_init_unlock: 1163 mutex_unlock(&qmp->phy_mutex); 1164 return ret; 1165 } 1166 1167 static int qmp_usbc_dp_disable(struct phy *phy) 1168 { 1169 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1170 1171 mutex_lock(&qmp->phy_mutex); 1172 1173 qmp_usbc_com_exit(phy); 1174 1175 qmp->dp_init_count--; 1176 1177 mutex_unlock(&qmp->phy_mutex); 1178 1179 return 0; 1180 } 1181 1182 static int qmp_usbc_dp_configure(struct phy *phy, union phy_configure_opts *opts) 1183 { 1184 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 1185 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1186 const struct qmp_phy_cfg *cfg = qmp->cfg; 1187 1188 mutex_lock(&qmp->phy_mutex); 1189 1190 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 1191 if (qmp->dp_opts.set_voltages) { 1192 cfg->configure_dp_tx(qmp); 1193 qmp->dp_opts.set_voltages = 0; 1194 } 1195 1196 mutex_unlock(&qmp->phy_mutex); 1197 1198 return 0; 1199 } 1200 1201 static int qmp_usbc_dp_calibrate(struct phy *phy) 1202 { 1203 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1204 const struct qmp_phy_cfg *cfg = qmp->cfg; 1205 int ret = 0; 1206 1207 mutex_lock(&qmp->phy_mutex); 1208 1209 if (cfg->calibrate_dp_phy) { 1210 ret = cfg->calibrate_dp_phy(qmp); 1211 if (ret) { 1212 dev_err(qmp->dev, "dp calibrate err(%d)\n", ret); 1213 mutex_unlock(&qmp->phy_mutex); 1214 return ret; 1215 } 1216 } 1217 1218 mutex_unlock(&qmp->phy_mutex); 1219 return 0; 1220 } 1221 1222 static int qmp_usbc_dp_serdes_init(struct qmp_usbc *qmp) 1223 { 1224 const struct qmp_phy_cfg *cfg = qmp->cfg; 1225 void __iomem *serdes = qmp->dp_serdes; 1226 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1227 1228 qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, 1229 cfg->dp_serdes_tbl_num); 1230 1231 switch (dp_opts->link_rate) { 1232 case 1620: 1233 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, 1234 cfg->serdes_tbl_rbr_num); 1235 break; 1236 case 2700: 1237 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, 1238 cfg->serdes_tbl_hbr_num); 1239 break; 1240 case 5400: 1241 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, 1242 cfg->serdes_tbl_hbr2_num); 1243 break; 1244 default: 1245 /* Other link rates aren't supported */ 1246 return -EINVAL; 1247 } 1248 1249 return 0; 1250 } 1251 1252 static int qmp_usbc_dp_power_on(struct phy *phy) 1253 { 1254 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1255 const struct qmp_phy_cfg *cfg = qmp->cfg; 1256 1257 void __iomem *tx = qmp->dp_tx; 1258 void __iomem *tx2 = qmp->dp_tx2; 1259 1260 /* 1261 * FIXME: SW_PORTSELECT handling for DP orientation flip is not implemented. 1262 * Expected: 1263 * - For standard lane mapping: configure SW_PORTSELECT in QSERDES_DP_PHY_CFG_1. 1264 * - For non-standard mapping: pass orientation to dp_ctrl and handle flip 1265 * via logical2physical lane remapping. 1266 */ 1267 1268 mutex_lock(&qmp->phy_mutex); 1269 1270 qmp_usbc_dp_serdes_init(qmp); 1271 1272 qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 1273 qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 1274 1275 /* Configure special DP tx tunings */ 1276 cfg->configure_dp_tx(qmp); 1277 1278 /* Configure link rate, swing, etc. */ 1279 cfg->configure_dp_phy(qmp); 1280 1281 mutex_unlock(&qmp->phy_mutex); 1282 1283 return 0; 1284 } 1285 1286 static int qmp_usbc_dp_power_off(struct phy *phy) 1287 { 1288 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1289 1290 mutex_lock(&qmp->phy_mutex); 1291 1292 /* Assert DP PHY power down */ 1293 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1294 1295 mutex_unlock(&qmp->phy_mutex); 1296 1297 return 0; 1298 } 1299 1300 static const struct phy_ops qmp_usbc_usb_phy_ops = { 1301 .init = qmp_usbc_usb_enable, 1302 .exit = qmp_usbc_usb_disable, 1303 .set_mode = qmp_usbc_usb_set_mode, 1304 .owner = THIS_MODULE, 1305 }; 1306 1307 static const struct phy_ops qmp_usbc_dp_phy_ops = { 1308 .init = qmp_usbc_dp_enable, 1309 .exit = qmp_usbc_dp_disable, 1310 .configure = qmp_usbc_dp_configure, 1311 .calibrate = qmp_usbc_dp_calibrate, 1312 .power_on = qmp_usbc_dp_power_on, 1313 .power_off = qmp_usbc_dp_power_off, 1314 .owner = THIS_MODULE, 1315 }; 1316 1317 static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp) 1318 { 1319 const struct qmp_phy_cfg *cfg = qmp->cfg; 1320 void __iomem *pcs = qmp->pcs; 1321 u32 intr_mask; 1322 1323 if (qmp->mode == PHY_MODE_USB_HOST_SS || 1324 qmp->mode == PHY_MODE_USB_DEVICE_SS) 1325 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 1326 else 1327 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 1328 1329 /* Clear any pending interrupts status */ 1330 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1331 /* Writing 1 followed by 0 clears the interrupt */ 1332 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1333 1334 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1335 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 1336 1337 /* Enable required PHY autonomous mode interrupts */ 1338 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 1339 1340 /* Enable i/o clamp_n for autonomous mode */ 1341 if (qmp->tcsr_map && qmp->vls_clamp_reg) 1342 regmap_write(qmp->tcsr_map, qmp->vls_clamp_reg, 1); 1343 } 1344 1345 static void qmp_usbc_disable_autonomous_mode(struct qmp_usbc *qmp) 1346 { 1347 const struct qmp_phy_cfg *cfg = qmp->cfg; 1348 void __iomem *pcs = qmp->pcs; 1349 1350 /* Disable i/o clamp_n on resume for normal mode */ 1351 if (qmp->tcsr_map && qmp->vls_clamp_reg) 1352 regmap_write(qmp->tcsr_map, qmp->vls_clamp_reg, 0); 1353 1354 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1355 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 1356 1357 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1358 /* Writing 1 followed by 0 clears the interrupt */ 1359 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1360 } 1361 1362 static int __maybe_unused qmp_usbc_runtime_suspend(struct device *dev) 1363 { 1364 struct qmp_usbc *qmp = dev_get_drvdata(dev); 1365 1366 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 1367 1368 if (!qmp->usb_init_count && !qmp->dp_init_count) { 1369 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1370 return 0; 1371 } 1372 1373 qmp_usbc_enable_autonomous_mode(qmp); 1374 1375 clk_disable_unprepare(qmp->pipe_clk); 1376 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 1377 1378 return 0; 1379 } 1380 1381 static int __maybe_unused qmp_usbc_runtime_resume(struct device *dev) 1382 { 1383 struct qmp_usbc *qmp = dev_get_drvdata(dev); 1384 int ret = 0; 1385 1386 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 1387 1388 if (!qmp->usb_init_count && !qmp->dp_init_count) { 1389 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1390 return 0; 1391 } 1392 1393 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 1394 if (ret) 1395 return ret; 1396 1397 ret = clk_prepare_enable(qmp->pipe_clk); 1398 if (ret) { 1399 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 1400 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 1401 return ret; 1402 } 1403 1404 qmp_usbc_disable_autonomous_mode(qmp); 1405 1406 return 0; 1407 } 1408 1409 static const struct dev_pm_ops qmp_usbc_pm_ops = { 1410 SET_RUNTIME_PM_OPS(qmp_usbc_runtime_suspend, 1411 qmp_usbc_runtime_resume, NULL) 1412 }; 1413 1414 static int qmp_usbc_reset_init(struct qmp_usbc *qmp, 1415 const char *const *reset_list, 1416 int num_resets) 1417 { 1418 struct device *dev = qmp->dev; 1419 int i; 1420 int ret; 1421 1422 qmp->resets = devm_kcalloc(dev, num_resets, 1423 sizeof(*qmp->resets), GFP_KERNEL); 1424 if (!qmp->resets) 1425 return -ENOMEM; 1426 1427 for (i = 0; i < num_resets; i++) 1428 qmp->resets[i].id = reset_list[i]; 1429 1430 qmp->num_resets = num_resets; 1431 1432 ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets); 1433 if (ret) 1434 return dev_err_probe(dev, ret, "failed to get resets\n"); 1435 1436 return 0; 1437 } 1438 1439 static int qmp_usbc_clk_init(struct qmp_usbc *qmp) 1440 { 1441 struct device *dev = qmp->dev; 1442 int num = ARRAY_SIZE(qmp_usbc_phy_clk_l); 1443 int i; 1444 1445 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 1446 if (!qmp->clks) 1447 return -ENOMEM; 1448 1449 for (i = 0; i < num; i++) 1450 qmp->clks[i].id = qmp_usbc_phy_clk_l[i]; 1451 1452 qmp->num_clks = num; 1453 1454 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 1455 } 1456 1457 static struct clk_hw *qmp_usbc_clks_hw_get(struct of_phandle_args *clkspec, void *data) 1458 { 1459 struct qmp_usbc *qmp = data; 1460 1461 if (clkspec->args_count == 0) 1462 return &qmp->pipe_clk_fixed.hw; 1463 1464 switch (clkspec->args[0]) { 1465 case QMP_USB43DP_USB3_PIPE_CLK: 1466 return &qmp->pipe_clk_fixed.hw; 1467 case QMP_USB43DP_DP_LINK_CLK: 1468 return &qmp->dp_link_hw; 1469 case QMP_USB43DP_DP_VCO_DIV_CLK: 1470 return &qmp->dp_pixel_hw; 1471 } 1472 1473 return ERR_PTR(-EINVAL); 1474 } 1475 1476 /* 1477 * Register a fixed rate pipe clock. 1478 * 1479 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 1480 * controls it. The <s>_pipe_clk coming out of the GCC is requested 1481 * by the PHY driver for its operations. 1482 * We register the <s>_pipe_clksrc here. The gcc driver takes care 1483 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 1484 * Below picture shows this relationship. 1485 * 1486 * +---------------+ 1487 * | PHY block |<<---------------------------------------+ 1488 * | | | 1489 * | +-------+ | +-----+ | 1490 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 1491 * clk | +-------+ | +-----+ 1492 * +---------------+ 1493 */ 1494 static int phy_pipe_clk_register(struct qmp_usbc *qmp, struct device_node *np) 1495 { 1496 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 1497 struct clk_init_data init = { }; 1498 char name[64]; 1499 int ret; 1500 1501 ret = of_property_read_string(np, "clock-output-names", &init.name); 1502 if (ret) { 1503 /* Clock name is not mandatory. */ 1504 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 1505 init.name = name; 1506 } 1507 1508 init.ops = &clk_fixed_rate_ops; 1509 1510 /* controllers using QMP phys use 125MHz pipe clock interface */ 1511 fixed->fixed_rate = 125000000; 1512 fixed->hw.init = &init; 1513 1514 return devm_clk_hw_register(qmp->dev, &fixed->hw); 1515 } 1516 1517 /* 1518 * Display Port PLL driver block diagram for branch clocks 1519 * 1520 * +------------------------------+ 1521 * | DP_VCO_CLK | 1522 * | | 1523 * | +-------------------+ | 1524 * | | (DP PLL/VCO) | | 1525 * | +---------+---------+ | 1526 * | v | 1527 * | +----------+-----------+ | 1528 * | | hsclk_divsel_clk_src | | 1529 * | +----------+-----------+ | 1530 * +------------------------------+ 1531 * | 1532 * +---------<---------v------------>----------+ 1533 * | | 1534 * +--------v----------------+ | 1535 * | dp_phy_pll_link_clk | | 1536 * | link_clk | | 1537 * +--------+----------------+ | 1538 * | | 1539 * | | 1540 * v v 1541 * Input to DISPCC block | 1542 * for link clk, crypto clk | 1543 * and interface clock | 1544 * | 1545 * | 1546 * +--------<------------+-----------------+---<---+ 1547 * | | | 1548 * +----v---------+ +--------v-----+ +--------v------+ 1549 * | vco_divided | | vco_divided | | vco_divided | 1550 * | _clk_src | | _clk_src | | _clk_src | 1551 * | | | | | | 1552 * |divsel_six | | divsel_two | | divsel_four | 1553 * +-------+------+ +-----+--------+ +--------+------+ 1554 * | | | 1555 * v---->----------v-------------<------v 1556 * | 1557 * +----------+-----------------+ 1558 * | dp_phy_pll_vco_div_clk | 1559 * +---------+------------------+ 1560 * | 1561 * v 1562 * Input to DISPCC block 1563 * for DP pixel clock 1564 * 1565 */ 1566 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 1567 { 1568 switch (req->rate) { 1569 case 1620000000UL / 2: 1570 case 2700000000UL / 2: 1571 /* 5.4 is same link rate as 2.7GHz, i.e. div 4 */ 1572 return 0; 1573 default: 1574 return -EINVAL; 1575 } 1576 } 1577 1578 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1579 { 1580 const struct qmp_usbc *qmp; 1581 const struct phy_configure_opts_dp *dp_opts; 1582 1583 qmp = container_of(hw, struct qmp_usbc, dp_pixel_hw); 1584 1585 dp_opts = &qmp->dp_opts; 1586 1587 switch (dp_opts->link_rate) { 1588 case 1620: 1589 return 1620000000UL / 2; 1590 case 2700: 1591 return 2700000000UL / 2; 1592 case 5400: 1593 return 5400000000UL / 4; 1594 default: 1595 return 0; 1596 } 1597 } 1598 1599 static const struct clk_ops qmp_dp_pixel_clk_ops = { 1600 .determine_rate = qmp_dp_pixel_clk_determine_rate, 1601 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 1602 }; 1603 1604 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 1605 { 1606 switch (req->rate) { 1607 case 162000000: 1608 case 270000000: 1609 case 540000000: 1610 return 0; 1611 default: 1612 return -EINVAL; 1613 } 1614 } 1615 1616 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1617 { 1618 const struct qmp_usbc *qmp; 1619 const struct phy_configure_opts_dp *dp_opts; 1620 1621 qmp = container_of(hw, struct qmp_usbc, dp_link_hw); 1622 dp_opts = &qmp->dp_opts; 1623 1624 switch (dp_opts->link_rate) { 1625 case 1620: 1626 case 2700: 1627 case 5400: 1628 return dp_opts->link_rate * 100000; 1629 default: 1630 return 0; 1631 } 1632 } 1633 1634 static const struct clk_ops qmp_dp_link_clk_ops = { 1635 .determine_rate = qmp_dp_link_clk_determine_rate, 1636 .recalc_rate = qmp_dp_link_clk_recalc_rate, 1637 }; 1638 1639 static int phy_dp_clks_register(struct qmp_usbc *qmp, struct device_node *np) 1640 { 1641 struct clk_init_data init = { }; 1642 char name[64]; 1643 int ret; 1644 1645 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 1646 init.ops = &qmp_dp_link_clk_ops; 1647 init.name = name; 1648 qmp->dp_link_hw.init = &init; 1649 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 1650 if (ret < 0) { 1651 dev_err(qmp->dev, "link clk reg fail ret=%d\n", ret); 1652 return ret; 1653 } 1654 1655 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 1656 init.ops = &qmp_dp_pixel_clk_ops; 1657 init.name = name; 1658 qmp->dp_pixel_hw.init = &init; 1659 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 1660 if (ret) { 1661 dev_err(qmp->dev, "pxl clk reg fail ret=%d\n", ret); 1662 return ret; 1663 } 1664 1665 return 0; 1666 } 1667 1668 static void phy_clk_release_provider(void *res) 1669 { 1670 of_clk_del_provider(res); 1671 } 1672 1673 static int qmp_usbc_register_clocks(struct qmp_usbc *qmp, struct device_node *np) 1674 { 1675 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 1676 int ret; 1677 1678 ret = phy_pipe_clk_register(qmp, np); 1679 if (ret) 1680 return ret; 1681 1682 if (qmp->dp_serdes != 0) { 1683 ret = phy_dp_clks_register(qmp, np); 1684 if (ret) 1685 return ret; 1686 } 1687 1688 if (np == qmp->dev->of_node) 1689 return devm_of_clk_add_hw_provider(qmp->dev, qmp_usbc_clks_hw_get, qmp); 1690 1691 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 1692 if (ret) 1693 return ret; 1694 1695 /* 1696 * Roll a devm action because the clock provider is the child node, but 1697 * the child node is not actually a device. 1698 */ 1699 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 1700 } 1701 1702 #if IS_ENABLED(CONFIG_TYPEC) 1703 static int qmp_usbc_typec_switch_set(struct typec_switch_dev *sw, 1704 enum typec_orientation orientation) 1705 { 1706 struct qmp_usbc *qmp = typec_switch_get_drvdata(sw); 1707 1708 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 1709 return 0; 1710 1711 mutex_lock(&qmp->phy_mutex); 1712 qmp->orientation = orientation; 1713 1714 if (qmp->usb_init_count) { 1715 qmp_usbc_usb_power_off(qmp->usb_phy); 1716 qmp_usbc_com_exit(qmp->usb_phy); 1717 1718 qmp_usbc_com_init(qmp->usb_phy); 1719 qmp_usbc_set_phy_mode(qmp, false); 1720 qmp_usbc_usb_power_on(qmp->usb_phy); 1721 } 1722 1723 mutex_unlock(&qmp->phy_mutex); 1724 1725 return 0; 1726 } 1727 1728 static void qmp_usbc_typec_unregister(void *data) 1729 { 1730 struct qmp_usbc *qmp = data; 1731 1732 typec_switch_unregister(qmp->sw); 1733 } 1734 1735 static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp) 1736 { 1737 struct typec_switch_desc sw_desc = {}; 1738 struct device *dev = qmp->dev; 1739 1740 sw_desc.drvdata = qmp; 1741 sw_desc.fwnode = dev->fwnode; 1742 sw_desc.set = qmp_usbc_typec_switch_set; 1743 qmp->sw = typec_switch_register(dev, &sw_desc); 1744 if (IS_ERR(qmp->sw)) { 1745 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 1746 return PTR_ERR(qmp->sw); 1747 } 1748 1749 return devm_add_action_or_reset(dev, qmp_usbc_typec_unregister, qmp); 1750 } 1751 #else 1752 static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp) 1753 { 1754 return 0; 1755 } 1756 #endif 1757 1758 static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *qmp, struct device_node *np) 1759 { 1760 struct platform_device *pdev = to_platform_device(qmp->dev); 1761 struct device *dev = qmp->dev; 1762 int ret; 1763 1764 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 1765 if (IS_ERR(qmp->serdes)) 1766 return PTR_ERR(qmp->serdes); 1767 1768 /* 1769 * Get memory resources for the PHY: 1770 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 1771 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 1772 * For single lane PHYs: pcs_misc (optional) -> 3. 1773 */ 1774 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 1775 if (IS_ERR(qmp->tx)) 1776 return PTR_ERR(qmp->tx); 1777 1778 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 1779 if (IS_ERR(qmp->rx)) 1780 return PTR_ERR(qmp->rx); 1781 1782 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 1783 if (IS_ERR(qmp->pcs)) 1784 return PTR_ERR(qmp->pcs); 1785 1786 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 1787 if (IS_ERR(qmp->tx2)) 1788 return PTR_ERR(qmp->tx2); 1789 1790 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 1791 if (IS_ERR(qmp->rx2)) 1792 return PTR_ERR(qmp->rx2); 1793 1794 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 1795 if (IS_ERR(qmp->pcs_misc)) { 1796 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 1797 qmp->pcs_misc = NULL; 1798 } 1799 1800 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 1801 if (IS_ERR(qmp->pipe_clk)) { 1802 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 1803 "failed to get pipe clock\n"); 1804 } 1805 1806 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 1807 if (ret < 0) 1808 return ret; 1809 1810 qmp->num_clks = ret; 1811 1812 ret = qmp_usbc_reset_init(qmp, usb3phy_legacy_reset_l, 1813 ARRAY_SIZE(usb3phy_legacy_reset_l)); 1814 if (ret) 1815 return ret; 1816 1817 return 0; 1818 } 1819 1820 static int qmp_usbc_parse_dt(struct qmp_usbc *qmp) 1821 { 1822 struct platform_device *pdev = to_platform_device(qmp->dev); 1823 const struct qmp_phy_cfg *cfg = qmp->cfg; 1824 const struct qmp_usbc_offsets *offs = cfg->offsets; 1825 struct device *dev = qmp->dev; 1826 void __iomem *base; 1827 int ret; 1828 1829 if (!offs) 1830 return -EINVAL; 1831 1832 base = devm_platform_ioremap_resource(pdev, 0); 1833 if (IS_ERR(base)) 1834 return PTR_ERR(base); 1835 1836 if (offs->dp_serdes != 0) { 1837 qmp->dp_serdes = base + offs->dp_serdes; 1838 qmp->dp_tx = base + offs->dp_txa; 1839 qmp->dp_tx2 = base + offs->dp_txb; 1840 qmp->dp_dp_phy = base + offs->dp_dp_phy; 1841 } 1842 1843 qmp->serdes = base + offs->serdes; 1844 qmp->pcs = base + offs->pcs; 1845 if (offs->pcs_misc) 1846 qmp->pcs_misc = base + offs->pcs_misc; 1847 qmp->tx = base + offs->tx; 1848 qmp->rx = base + offs->rx; 1849 1850 qmp->tx2 = base + offs->tx2; 1851 qmp->rx2 = base + offs->rx2; 1852 1853 ret = qmp_usbc_clk_init(qmp); 1854 if (ret) 1855 return ret; 1856 1857 qmp->pipe_clk = devm_clk_get(dev, "pipe"); 1858 if (IS_ERR(qmp->pipe_clk)) { 1859 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 1860 "failed to get pipe clock\n"); 1861 } 1862 1863 ret = qmp_usbc_reset_init(qmp, cfg->reset_list, cfg->num_resets); 1864 if (ret) 1865 return ret; 1866 1867 return 0; 1868 } 1869 1870 static int qmp_usbc_parse_tcsr(struct qmp_usbc *qmp) 1871 { 1872 struct of_phandle_args tcsr_args; 1873 struct device *dev = qmp->dev; 1874 int ret, args_count; 1875 1876 args_count = of_property_count_u32_elems(dev->of_node, "qcom,tcsr-reg"); 1877 args_count = args_count - 1; 1878 ret = of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1879 args_count, 0, &tcsr_args); 1880 if (ret == -ENOENT) 1881 return 0; 1882 else if (ret < 0) 1883 return dev_err_probe(dev, ret, "Failed to parse qcom,tcsr-reg\n"); 1884 1885 qmp->tcsr_map = syscon_node_to_regmap(tcsr_args.np); 1886 of_node_put(tcsr_args.np); 1887 if (IS_ERR(qmp->tcsr_map)) 1888 return PTR_ERR(qmp->tcsr_map); 1889 1890 qmp->vls_clamp_reg = tcsr_args.args[0]; 1891 1892 if (args_count > 1) 1893 qmp->dp_phy_mode_reg = tcsr_args.args[1]; 1894 1895 return 0; 1896 } 1897 1898 static struct phy *qmp_usbc_phy_xlate(struct device *dev, const struct of_phandle_args *args) 1899 { 1900 struct qmp_usbc *qmp = dev_get_drvdata(dev); 1901 1902 if (args->args_count == 0) 1903 return qmp->usb_phy; 1904 1905 switch (args->args[0]) { 1906 case QMP_USB43DP_USB3_PHY: 1907 return qmp->usb_phy; 1908 case QMP_USB43DP_DP_PHY: 1909 return qmp->dp_phy ?: ERR_PTR(-ENODEV); 1910 } 1911 1912 return ERR_PTR(-EINVAL); 1913 } 1914 1915 static int qmp_usbc_probe(struct platform_device *pdev) 1916 { 1917 struct device *dev = &pdev->dev; 1918 struct phy_provider *phy_provider; 1919 struct device_node *np; 1920 struct qmp_usbc *qmp; 1921 int ret; 1922 1923 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 1924 if (!qmp) 1925 return -ENOMEM; 1926 1927 qmp->dev = dev; 1928 dev_set_drvdata(dev, qmp); 1929 1930 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 1931 1932 qmp->cfg = of_device_get_match_data(dev); 1933 if (!qmp->cfg) 1934 return -EINVAL; 1935 1936 mutex_init(&qmp->phy_mutex); 1937 1938 ret = devm_regulator_bulk_get_const(qmp->dev, qmp->cfg->num_vregs, 1939 qmp->cfg->vreg_list, &qmp->vregs); 1940 if (ret) 1941 return ret; 1942 1943 ret = qmp_usbc_typec_switch_register(qmp); 1944 if (ret) 1945 return ret; 1946 1947 ret = qmp_usbc_parse_tcsr(qmp); 1948 if (ret) 1949 return ret; 1950 1951 /* Check for legacy binding with child node. */ 1952 np = of_get_child_by_name(dev->of_node, "phy"); 1953 if (np) { 1954 ret = qmp_usbc_parse_dt_legacy(qmp, np); 1955 } else { 1956 np = of_node_get(dev->of_node); 1957 ret = qmp_usbc_parse_dt(qmp); 1958 } 1959 if (ret) 1960 goto err_node_put; 1961 1962 pm_runtime_set_active(dev); 1963 ret = devm_pm_runtime_enable(dev); 1964 if (ret) 1965 goto err_node_put; 1966 /* 1967 * Prevent runtime pm from being ON by default. Users can enable 1968 * it using power/control in sysfs. 1969 */ 1970 pm_runtime_forbid(dev); 1971 1972 ret = qmp_usbc_register_clocks(qmp, np); 1973 if (ret) 1974 goto err_node_put; 1975 1976 qmp->usb_phy = devm_phy_create(dev, np, &qmp_usbc_usb_phy_ops); 1977 if (IS_ERR(qmp->usb_phy)) { 1978 ret = PTR_ERR(qmp->usb_phy); 1979 dev_err(dev, "failed to create PHY: %d\n", ret); 1980 goto err_node_put; 1981 } 1982 1983 phy_set_drvdata(qmp->usb_phy, qmp); 1984 1985 if (qmp->dp_serdes != 0) { 1986 qmp->dp_phy = devm_phy_create(dev, np, &qmp_usbc_dp_phy_ops); 1987 if (IS_ERR(qmp->dp_phy)) { 1988 ret = PTR_ERR(qmp->dp_phy); 1989 dev_err(dev, "failed to create PHY: %d\n", ret); 1990 goto err_node_put; 1991 } 1992 phy_set_drvdata(qmp->dp_phy, qmp); 1993 } 1994 1995 of_node_put(np); 1996 1997 phy_provider = devm_of_phy_provider_register(dev, qmp_usbc_phy_xlate); 1998 1999 return PTR_ERR_OR_ZERO(phy_provider); 2000 2001 err_node_put: 2002 of_node_put(np); 2003 return ret; 2004 } 2005 2006 static const struct of_device_id qmp_usbc_of_match_table[] = { 2007 { 2008 .compatible = "qcom,msm8998-qmp-usb3-phy", 2009 .data = &msm8998_usb3phy_cfg, 2010 }, { 2011 .compatible = "qcom,qcm2290-qmp-usb3-phy", 2012 .data = &qcm2290_usb3phy_cfg, 2013 }, { 2014 .compatible = "qcom,qcs615-qmp-usb3-dp-phy", 2015 .data = &qcs615_usb3dp_phy_cfg, 2016 }, { 2017 .compatible = "qcom,qcs615-qmp-usb3-phy", 2018 .data = &qcs615_usb3phy_cfg, 2019 }, { 2020 .compatible = "qcom,sdm660-qmp-usb3-phy", 2021 .data = &sdm660_usb3phy_cfg, 2022 }, { 2023 .compatible = "qcom,sm6115-qmp-usb3-phy", 2024 .data = &qcm2290_usb3phy_cfg, 2025 }, 2026 { }, 2027 }; 2028 MODULE_DEVICE_TABLE(of, qmp_usbc_of_match_table); 2029 2030 static struct platform_driver qmp_usbc_driver = { 2031 .probe = qmp_usbc_probe, 2032 .driver = { 2033 .name = "qcom-qmp-usbc-phy", 2034 .pm = &qmp_usbc_pm_ops, 2035 .of_match_table = qmp_usbc_of_match_table, 2036 }, 2037 }; 2038 2039 module_platform_driver(qmp_usbc_driver); 2040 2041 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2042 MODULE_DESCRIPTION("Qualcomm QMP USB-C PHY driver"); 2043 MODULE_LICENSE("GPL"); 2044