1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 #include <linux/usb/typec.h> 24 #include <linux/usb/typec_mux.h> 25 #include <dt-bindings/phy/phy-qcom-qmp.h> 26 27 #include "phy-qcom-qmp-common.h" 28 29 #include "phy-qcom-qmp.h" 30 #include "phy-qcom-qmp-pcs-misc-v3.h" 31 32 #include "phy-qcom-qmp-dp-phy.h" 33 #include "phy-qcom-qmp-dp-phy-v2.h" 34 35 #define PHY_INIT_COMPLETE_TIMEOUT 10000 36 #define SW_PORTSELECT_VAL BIT(0) 37 #define SW_PORTSELECT_MUX BIT(1) 38 39 /* set of registers with offsets different per-PHY */ 40 enum qphy_reg_layout { 41 /* PCS registers */ 42 QPHY_SW_RESET, 43 QPHY_START_CTRL, 44 QPHY_PCS_STATUS, 45 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 46 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 47 QPHY_PCS_POWER_DOWN_CONTROL, 48 /* Keep last to ensure regs_layout arrays are properly initialized */ 49 QPHY_LAYOUT_SIZE 50 }; 51 52 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 53 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 54 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 55 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 56 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 57 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 58 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 59 }; 60 61 static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = { 62 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 63 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 64 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 65 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 66 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 67 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 68 }; 69 70 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { 71 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 72 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 73 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 74 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), 75 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 76 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 77 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 78 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 79 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 80 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 81 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 82 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 83 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 84 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 85 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 86 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 87 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 88 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 89 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 90 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 91 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 92 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 93 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 94 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 95 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 96 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 97 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 98 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 99 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), 101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 103 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 109 }; 110 111 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { 112 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 113 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 114 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 115 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 116 }; 117 118 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { 119 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 120 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 121 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 122 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 123 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), 124 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 125 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), 126 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 127 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 128 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 129 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 130 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 131 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 132 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 133 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 134 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), 135 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 136 }; 137 138 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { 139 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 140 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 141 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 142 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 143 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 144 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 145 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 146 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 147 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 148 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 149 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 150 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 151 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 152 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 153 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 154 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 155 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 156 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 157 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 158 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 159 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 160 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 161 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), 162 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 163 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 164 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 165 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 166 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), 174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 177 }; 178 179 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { 180 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x14), 181 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 182 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), 183 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x06), 184 QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x00), 185 QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL2, 0x08), 186 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), 187 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), 188 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), 189 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), 190 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), 191 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), 192 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x03), 193 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), 194 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), 195 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), 196 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 197 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 198 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0x0a), 199 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x15), 200 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x34), 201 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), 202 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x00), 203 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), 204 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00), 205 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), 206 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a), 207 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x01), 208 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), 209 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x01), 210 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x00), 211 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x00), 212 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0xde), 213 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x07), 214 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), 215 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), 216 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_INITVAL, 0x80), 217 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CTRL_BY_PSM, 0x01), 218 }; 219 220 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { 221 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 222 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 223 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 224 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 225 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), 226 }; 227 228 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { 229 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 230 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 231 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 232 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 233 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 234 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 235 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 236 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 237 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 238 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 239 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 240 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 241 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 242 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 243 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 244 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 245 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 246 }; 247 248 /* the only difference is QSERDES_V3_RX_UCDR_PI_CONTROLS */ 249 static const struct qmp_phy_init_tbl sdm660_usb3_rx_tbl[] = { 250 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 251 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), 252 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 253 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 254 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 255 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 256 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 257 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 258 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 259 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 260 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 261 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 262 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 263 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 264 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 265 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 266 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 267 }; 268 269 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { 270 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 271 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 272 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 273 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 274 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 275 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 277 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 278 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 279 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 280 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 291 }; 292 293 static const struct qmp_phy_init_tbl qcs615_dp_serdes_tbl[] = { 294 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), 295 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x37), 296 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x00), 297 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x06), 298 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 299 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x0e), 300 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_CTRL, 0x0f), 301 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_BUF_ENABLE, 0x06), 302 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), 303 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), 304 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), 305 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), 306 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), 307 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x40), 308 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 309 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), 310 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x08), 311 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0x05), 312 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_CTRL, 0x00), 313 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE1_MODE0, 0x00), 314 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE2_MODE0, 0x00), 315 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_CTRL, 0x00), 316 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x0f), 317 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x02), 318 }; 319 320 static const struct qmp_phy_init_tbl qcs615_dp_serdes_tbl_rbr[] = { 321 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x2c), 322 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x69), 323 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), 324 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x80), 325 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x07), 326 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0xbf), 327 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x21), 328 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), 329 }; 330 331 static const struct qmp_phy_init_tbl qcs615_dp_serdes_tbl_hbr[] = { 332 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x24), 333 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x69), 334 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), 335 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x80), 336 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x07), 337 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x3f), 338 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x38), 339 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), 340 }; 341 342 static const struct qmp_phy_init_tbl qcs615_dp_serdes_tbl_hbr2[] = { 343 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x20), 344 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x8c), 345 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), 346 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x00), 347 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x0a), 348 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x7f), 349 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x70), 350 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), 351 }; 352 353 static const struct qmp_phy_init_tbl qcs615_dp_tx_tbl[] = { 354 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 355 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 356 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 357 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 358 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 359 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 360 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 361 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 362 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 363 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x2b), 364 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x2f), 365 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 366 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x12), 367 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x12), 368 }; 369 370 struct qmp_usbc_offsets { 371 u16 serdes; 372 u16 pcs; 373 u16 pcs_misc; 374 u16 tx; 375 u16 rx; 376 /* for PHYs with >= 2 lanes */ 377 u16 tx2; 378 u16 rx2; 379 380 u16 dp_serdes; 381 u16 dp_txa; 382 u16 dp_txb; 383 u16 dp_dp_phy; 384 }; 385 386 struct qmp_usbc; 387 struct qmp_phy_cfg { 388 const struct qmp_usbc_offsets *offsets; 389 390 /* Init sequence for USB PHY blocks - serdes, tx, rx, pcs */ 391 const struct qmp_phy_init_tbl *serdes_tbl; 392 int serdes_tbl_num; 393 const struct qmp_phy_init_tbl *tx_tbl; 394 int tx_tbl_num; 395 const struct qmp_phy_init_tbl *rx_tbl; 396 int rx_tbl_num; 397 const struct qmp_phy_init_tbl *pcs_tbl; 398 int pcs_tbl_num; 399 400 /* Init sequence for DP PHY blocks - serdes, tx, rbr, hbr, hbr2 */ 401 const struct qmp_phy_init_tbl *dp_serdes_tbl; 402 int dp_serdes_tbl_num; 403 const struct qmp_phy_init_tbl *dp_tx_tbl; 404 int dp_tx_tbl_num; 405 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 406 int serdes_tbl_rbr_num; 407 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 408 int serdes_tbl_hbr_num; 409 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 410 int serdes_tbl_hbr2_num; 411 412 const u8 (*swing_tbl)[4][4]; 413 const u8 (*pre_emphasis_tbl)[4][4]; 414 415 /* DP PHY callbacks */ 416 void (*dp_aux_init)(struct qmp_usbc *qmp); 417 void (*configure_dp_tx)(struct qmp_usbc *qmp); 418 int (*configure_dp_phy)(struct qmp_usbc *qmp); 419 int (*calibrate_dp_phy)(struct qmp_usbc *qmp); 420 421 const char * const *reset_list; 422 int num_resets; 423 const struct regulator_bulk_data *vreg_list; 424 int num_vregs; 425 426 /* array of registers with different offsets */ 427 const unsigned int *regs; 428 }; 429 430 struct qmp_usbc { 431 struct device *dev; 432 433 const struct qmp_phy_cfg *cfg; 434 435 void __iomem *serdes; 436 void __iomem *pcs; 437 void __iomem *pcs_misc; 438 void __iomem *tx; 439 void __iomem *rx; 440 void __iomem *tx2; 441 void __iomem *rx2; 442 void __iomem *dp_dp_phy; 443 void __iomem *dp_tx; 444 void __iomem *dp_tx2; 445 void __iomem *dp_serdes; 446 447 struct clk *pipe_clk; 448 struct clk_fixed_rate pipe_clk_fixed; 449 450 struct clk_hw dp_link_hw; 451 struct clk_hw dp_pixel_hw; 452 struct clk_bulk_data *clks; 453 int num_clks; 454 int num_resets; 455 struct reset_control_bulk_data *resets; 456 struct regulator_bulk_data *vregs; 457 458 struct regmap *tcsr_map; 459 u32 vls_clamp_reg; 460 u32 dp_phy_mode_reg; 461 462 struct mutex phy_mutex; 463 464 struct phy *usb_phy; 465 enum phy_mode mode; 466 unsigned int usb_init_count; 467 468 struct phy *dp_phy; 469 unsigned int dp_aux_cfg; 470 struct phy_configure_opts_dp dp_opts; 471 unsigned int dp_init_count; 472 473 struct typec_switch_dev *sw; 474 enum typec_orientation orientation; 475 }; 476 477 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 478 { 479 u32 reg; 480 481 reg = readl(base + offset); 482 reg |= val; 483 writel(reg, base + offset); 484 485 /* ensure that above write is through */ 486 readl(base + offset); 487 } 488 489 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 490 { 491 u32 reg; 492 493 reg = readl(base + offset); 494 reg &= ~val; 495 writel(reg, base + offset); 496 497 /* ensure that above write is through */ 498 readl(base + offset); 499 } 500 501 /* list of clocks required by phy */ 502 static const char * const qmp_usbc_phy_clk_l[] = { 503 "aux", "cfg_ahb", "ref", "com_aux", 504 }; 505 506 /* list of resets */ 507 static const char * const usb3phy_legacy_reset_l[] = { 508 "phy", "common", 509 }; 510 511 static const char * const usb3phy_reset_l[] = { 512 "phy_phy", "phy", 513 }; 514 515 static const char * const qcs615_usb3dpphy_reset_l[] = { 516 "phy_phy", "dp_phy", 517 }; 518 519 static const char * const shikra_usb3dpphy_reset_l[] = { 520 "phy_phy", "dp_phy", "phy", 521 }; 522 523 static const struct regulator_bulk_data qmp_phy_msm8998_vreg_l[] = { 524 { .supply = "vdda-phy", .init_load_uA = 68600 }, 525 { .supply = "vdda-pll", .init_load_uA = 14200 }, 526 }; 527 528 static const struct regulator_bulk_data qmp_phy_sm2290_vreg_l[] = { 529 { .supply = "vdda-phy", .init_load_uA = 66100 }, 530 { .supply = "vdda-pll", .init_load_uA = 13300 }, 531 }; 532 533 static const struct regulator_bulk_data qmp_phy_qcs615_vreg_l[] = { 534 { .supply = "vdda-phy", .init_load_uA = 50000 }, 535 { .supply = "vdda-pll", .init_load_uA = 20000 }, 536 }; 537 538 static const struct qmp_usbc_offsets qmp_usbc_offsets_v3_qcm2290 = { 539 .serdes = 0x0, 540 .pcs = 0xc00, 541 .pcs_misc = 0xa00, 542 .tx = 0x200, 543 .rx = 0x400, 544 .tx2 = 0x600, 545 .rx2 = 0x800, 546 }; 547 548 static const struct qmp_usbc_offsets qmp_usbc_usb3dp_offsets_qcs615 = { 549 .serdes = 0x0, 550 .pcs = 0xc00, 551 .pcs_misc = 0xa00, 552 .tx = 0x200, 553 .rx = 0x400, 554 .tx2 = 0x600, 555 .rx2 = 0x800, 556 .dp_serdes = 0x1c00, 557 .dp_txa = 0x1400, 558 .dp_txb = 0x1800, 559 .dp_dp_phy = 0x1000, 560 }; 561 562 static const u8 qcs615_dp_pre_emphasis_hbr2_rbr[4][4] = { 563 {0x00, 0x0b, 0x12, 0xff}, 564 {0x00, 0x0a, 0x12, 0xff}, 565 {0x00, 0x0c, 0xff, 0xff}, 566 {0xff, 0xff, 0xff, 0xff} 567 }; 568 569 static const u8 qcs615_dp_voltage_swing_hbr2_rbr[4][4] = { 570 {0x07, 0x0f, 0x14, 0xff}, 571 {0x11, 0x1d, 0x1f, 0xff}, 572 {0x18, 0x1f, 0xff, 0xff}, 573 {0xff, 0xff, 0xff, 0xff} 574 }; 575 576 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { 577 .offsets = &qmp_usbc_offsets_v3_qcm2290, 578 579 .serdes_tbl = msm8998_usb3_serdes_tbl, 580 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), 581 .tx_tbl = msm8998_usb3_tx_tbl, 582 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), 583 .rx_tbl = msm8998_usb3_rx_tbl, 584 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), 585 .pcs_tbl = msm8998_usb3_pcs_tbl, 586 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), 587 .reset_list = usb3phy_reset_l, 588 .num_resets = ARRAY_SIZE(usb3phy_reset_l), 589 .vreg_list = qmp_phy_msm8998_vreg_l, 590 .num_vregs = ARRAY_SIZE(qmp_phy_msm8998_vreg_l), 591 .regs = qmp_v3_usb3phy_regs_layout, 592 }; 593 594 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { 595 .offsets = &qmp_usbc_offsets_v3_qcm2290, 596 597 .serdes_tbl = qcm2290_usb3_serdes_tbl, 598 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 599 .tx_tbl = qcm2290_usb3_tx_tbl, 600 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 601 .rx_tbl = qcm2290_usb3_rx_tbl, 602 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 603 .pcs_tbl = qcm2290_usb3_pcs_tbl, 604 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 605 .reset_list = usb3phy_reset_l, 606 .num_resets = ARRAY_SIZE(usb3phy_reset_l), 607 .vreg_list = qmp_phy_sm2290_vreg_l, 608 .num_vregs = ARRAY_SIZE(qmp_phy_sm2290_vreg_l), 609 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 610 }; 611 612 static const struct qmp_phy_cfg sdm660_usb3phy_cfg = { 613 .offsets = &qmp_usbc_offsets_v3_qcm2290, 614 615 .serdes_tbl = qcm2290_usb3_serdes_tbl, 616 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 617 .tx_tbl = qcm2290_usb3_tx_tbl, 618 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 619 .rx_tbl = sdm660_usb3_rx_tbl, 620 .rx_tbl_num = ARRAY_SIZE(sdm660_usb3_rx_tbl), 621 .pcs_tbl = qcm2290_usb3_pcs_tbl, 622 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 623 .reset_list = usb3phy_reset_l, 624 .num_resets = ARRAY_SIZE(usb3phy_reset_l), 625 .vreg_list = qmp_phy_msm8998_vreg_l, 626 .num_vregs = ARRAY_SIZE(qmp_phy_msm8998_vreg_l), 627 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 628 }; 629 630 static const struct qmp_phy_cfg qcs615_usb3phy_cfg = { 631 .offsets = &qmp_usbc_offsets_v3_qcm2290, 632 633 .serdes_tbl = qcm2290_usb3_serdes_tbl, 634 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 635 .tx_tbl = qcm2290_usb3_tx_tbl, 636 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 637 .rx_tbl = qcm2290_usb3_rx_tbl, 638 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 639 .pcs_tbl = qcm2290_usb3_pcs_tbl, 640 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 641 .reset_list = usb3phy_reset_l, 642 .num_resets = ARRAY_SIZE(usb3phy_reset_l), 643 .vreg_list = qmp_phy_qcs615_vreg_l, 644 .num_vregs = ARRAY_SIZE(qmp_phy_qcs615_vreg_l), 645 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 646 }; 647 648 static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp); 649 static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp); 650 static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp); 651 static int qcs615_qmp_calibrate_dp_phy(struct qmp_usbc *qmp); 652 653 static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = { 654 .offsets = &qmp_usbc_usb3dp_offsets_qcs615, 655 656 .serdes_tbl = qcm2290_usb3_serdes_tbl, 657 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 658 .tx_tbl = qcm2290_usb3_tx_tbl, 659 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 660 .rx_tbl = qcm2290_usb3_rx_tbl, 661 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 662 .pcs_tbl = qcm2290_usb3_pcs_tbl, 663 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 664 665 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 666 667 .dp_serdes_tbl = qcs615_dp_serdes_tbl, 668 .dp_serdes_tbl_num = ARRAY_SIZE(qcs615_dp_serdes_tbl), 669 .dp_tx_tbl = qcs615_dp_tx_tbl, 670 .dp_tx_tbl_num = ARRAY_SIZE(qcs615_dp_tx_tbl), 671 672 .serdes_tbl_rbr = qcs615_dp_serdes_tbl_rbr, 673 .serdes_tbl_rbr_num = ARRAY_SIZE(qcs615_dp_serdes_tbl_rbr), 674 .serdes_tbl_hbr = qcs615_dp_serdes_tbl_hbr, 675 .serdes_tbl_hbr_num = ARRAY_SIZE(qcs615_dp_serdes_tbl_hbr), 676 .serdes_tbl_hbr2 = qcs615_dp_serdes_tbl_hbr2, 677 .serdes_tbl_hbr2_num = ARRAY_SIZE(qcs615_dp_serdes_tbl_hbr2), 678 679 .swing_tbl = &qcs615_dp_voltage_swing_hbr2_rbr, 680 .pre_emphasis_tbl = &qcs615_dp_pre_emphasis_hbr2_rbr, 681 682 .dp_aux_init = qcs615_qmp_dp_aux_init, 683 .configure_dp_tx = qcs615_qmp_configure_dp_tx, 684 .configure_dp_phy = qcs615_qmp_configure_dp_phy, 685 .calibrate_dp_phy = qcs615_qmp_calibrate_dp_phy, 686 687 .reset_list = qcs615_usb3dpphy_reset_l, 688 .num_resets = ARRAY_SIZE(qcs615_usb3dpphy_reset_l), 689 .vreg_list = qmp_phy_qcs615_vreg_l, 690 .num_vregs = ARRAY_SIZE(qmp_phy_qcs615_vreg_l), 691 }; 692 693 static const struct qmp_phy_cfg shikra_usb3dp_phy_cfg = { 694 .offsets = &qmp_usbc_usb3dp_offsets_qcs615, 695 696 .serdes_tbl = qcm2290_usb3_serdes_tbl, 697 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 698 .tx_tbl = qcm2290_usb3_tx_tbl, 699 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 700 .rx_tbl = qcm2290_usb3_rx_tbl, 701 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 702 .pcs_tbl = qcm2290_usb3_pcs_tbl, 703 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 704 705 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 706 707 .dp_serdes_tbl = qcs615_dp_serdes_tbl, 708 .dp_serdes_tbl_num = ARRAY_SIZE(qcs615_dp_serdes_tbl), 709 .dp_tx_tbl = qcs615_dp_tx_tbl, 710 .dp_tx_tbl_num = ARRAY_SIZE(qcs615_dp_tx_tbl), 711 712 .serdes_tbl_rbr = qcs615_dp_serdes_tbl_rbr, 713 .serdes_tbl_rbr_num = ARRAY_SIZE(qcs615_dp_serdes_tbl_rbr), 714 .serdes_tbl_hbr = qcs615_dp_serdes_tbl_hbr, 715 .serdes_tbl_hbr_num = ARRAY_SIZE(qcs615_dp_serdes_tbl_hbr), 716 .serdes_tbl_hbr2 = qcs615_dp_serdes_tbl_hbr2, 717 .serdes_tbl_hbr2_num = ARRAY_SIZE(qcs615_dp_serdes_tbl_hbr2), 718 719 .swing_tbl = &qcs615_dp_voltage_swing_hbr2_rbr, 720 .pre_emphasis_tbl = &qcs615_dp_pre_emphasis_hbr2_rbr, 721 722 .dp_aux_init = qcs615_qmp_dp_aux_init, 723 .configure_dp_tx = qcs615_qmp_configure_dp_tx, 724 .configure_dp_phy = qcs615_qmp_configure_dp_phy, 725 .calibrate_dp_phy = qcs615_qmp_calibrate_dp_phy, 726 727 .reset_list = shikra_usb3dpphy_reset_l, 728 .num_resets = ARRAY_SIZE(shikra_usb3dpphy_reset_l), 729 .vreg_list = qmp_phy_qcs615_vreg_l, 730 .num_vregs = ARRAY_SIZE(qmp_phy_qcs615_vreg_l), 731 }; 732 733 static void qmp_usbc_set_phy_mode(struct qmp_usbc *qmp, bool is_dp) 734 { 735 if (qmp->tcsr_map && qmp->dp_phy_mode_reg) 736 regmap_write(qmp->tcsr_map, qmp->dp_phy_mode_reg, is_dp); 737 } 738 739 static int qmp_usbc_com_init(struct phy *phy) 740 { 741 struct qmp_usbc *qmp = phy_get_drvdata(phy); 742 const struct qmp_phy_cfg *cfg = qmp->cfg; 743 int ret; 744 745 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 746 if (ret) { 747 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 748 return ret; 749 } 750 751 ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets); 752 if (ret) { 753 dev_err(qmp->dev, "reset assert failed\n"); 754 goto err_disable_regulators; 755 } 756 757 ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets); 758 if (ret) { 759 dev_err(qmp->dev, "reset deassert failed\n"); 760 goto err_disable_regulators; 761 } 762 763 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 764 if (ret) 765 goto err_assert_reset; 766 767 return 0; 768 769 err_assert_reset: 770 reset_control_bulk_assert(qmp->num_resets, qmp->resets); 771 err_disable_regulators: 772 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 773 774 return ret; 775 } 776 777 static int qmp_usbc_com_exit(struct phy *phy) 778 { 779 struct qmp_usbc *qmp = phy_get_drvdata(phy); 780 const struct qmp_phy_cfg *cfg = qmp->cfg; 781 782 reset_control_bulk_assert(qmp->num_resets, qmp->resets); 783 784 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 785 786 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 787 788 return 0; 789 } 790 791 static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp) 792 { 793 writel(DP_PHY_PD_CTL_AUX_PWRDN | 794 DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | 795 DP_PHY_PD_CTL_PLL_PWRDN, 796 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 797 798 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 799 DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | 800 DP_PHY_PD_CTL_PLL_PWRDN, 801 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 802 803 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 804 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 805 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 806 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 807 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 808 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 809 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 810 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 811 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 812 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 813 qmp->dp_aux_cfg = 0; 814 815 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 816 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 817 PHY_AUX_REQ_ERR_MASK, 818 qmp->dp_dp_phy + QSERDES_V2_DP_PHY_AUX_INTERRUPT_MASK); 819 } 820 821 static int qcs615_qmp_configure_dp_swing(struct qmp_usbc *qmp) 822 { 823 const struct qmp_phy_cfg *cfg = qmp->cfg; 824 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 825 void __iomem *tx = qmp->dp_tx; 826 void __iomem *tx2 = qmp->dp_tx2; 827 unsigned int v_level = 0, p_level = 0; 828 u8 voltage_swing_cfg, pre_emphasis_cfg; 829 int i; 830 831 if (dp_opts->lanes > 4) { 832 dev_err(qmp->dev, "Invalid lane_num(%d)\n", dp_opts->lanes); 833 return -EINVAL; 834 } 835 836 for (i = 0; i < dp_opts->lanes; i++) { 837 v_level = max(v_level, dp_opts->voltage[i]); 838 p_level = max(p_level, dp_opts->pre[i]); 839 } 840 841 if (v_level >= 4 || p_level >= 4) { 842 dev_err(qmp->dev, "Invalid v(%d) | p(%d) level)\n", 843 v_level, p_level); 844 return -EINVAL; 845 } 846 847 voltage_swing_cfg = (*cfg->swing_tbl)[v_level][p_level]; 848 pre_emphasis_cfg = (*cfg->pre_emphasis_tbl)[v_level][p_level]; 849 850 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 851 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 852 853 if (voltage_swing_cfg == 0xff && pre_emphasis_cfg == 0xff) 854 return -EINVAL; 855 856 writel(voltage_swing_cfg, tx + QSERDES_V3_TX_TX_DRV_LVL); 857 writel(pre_emphasis_cfg, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); 858 writel(voltage_swing_cfg, tx2 + QSERDES_V3_TX_TX_DRV_LVL); 859 writel(pre_emphasis_cfg, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); 860 861 return 0; 862 } 863 864 static void qmp_usbc_configure_dp_mode(struct qmp_usbc *qmp) 865 { 866 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 867 u32 val; 868 869 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 870 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN; 871 872 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 873 874 if (reverse) 875 writel(0xc9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 876 else 877 writel(0xd9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 878 } 879 880 static int qmp_usbc_configure_dp_clocks(struct qmp_usbc *qmp) 881 { 882 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 883 u32 phy_vco_div; 884 unsigned long pixel_freq; 885 886 switch (dp_opts->link_rate) { 887 case 1620: 888 phy_vco_div = 0x1; 889 pixel_freq = 1620000000UL / 2; 890 break; 891 case 2700: 892 phy_vco_div = 0x1; 893 pixel_freq = 2700000000UL / 2; 894 break; 895 case 5400: 896 phy_vco_div = 0x2; 897 pixel_freq = 5400000000UL / 4; 898 break; 899 default: 900 dev_err(qmp->dev, "link rate:%d not supported\n", dp_opts->link_rate); 901 return -EINVAL; 902 } 903 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_VCO_DIV); 904 905 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 906 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 907 908 return 0; 909 } 910 911 static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp) 912 { 913 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 914 void __iomem *tx = qmp->dp_tx; 915 void __iomem *tx2 = qmp->dp_tx2; 916 917 /* program default setting first */ 918 writel(0x2a, tx + QSERDES_V3_TX_TX_DRV_LVL); 919 writel(0x20, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); 920 writel(0x2a, tx2 + QSERDES_V3_TX_TX_DRV_LVL); 921 writel(0x20, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); 922 923 if (dp_opts->link_rate >= 2700) { 924 writel(0xc4, tx + QSERDES_V3_TX_LANE_MODE_1); 925 writel(0xc4, tx2 + QSERDES_V3_TX_LANE_MODE_1); 926 } else { 927 writel(0xc6, tx + QSERDES_V3_TX_LANE_MODE_1); 928 writel(0xc6, tx2 + QSERDES_V3_TX_LANE_MODE_1); 929 } 930 931 qcs615_qmp_configure_dp_swing(qmp); 932 } 933 934 static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp) 935 { 936 u32 status; 937 int ret; 938 939 qmp_usbc_configure_dp_mode(qmp); 940 941 writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX0_TX1_LANE_CTL); 942 writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX2_TX3_LANE_CTL); 943 944 ret = qmp_usbc_configure_dp_clocks(qmp); 945 if (ret) 946 return ret; 947 948 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 949 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 950 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 951 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 952 953 writel(0x20, qmp->dp_serdes + QSERDES_V2_COM_RESETSM_CNTRL); 954 955 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V2_COM_C_READY_STATUS, 956 status, 957 ((status & BIT(0)) > 0), 958 500, 959 10000)) { 960 dev_err(qmp->dev, "C_READY not ready\n"); 961 return -ETIMEDOUT; 962 } 963 964 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V2_COM_CMN_STATUS, 965 status, 966 ((status & BIT(0)) > 0), 967 500, 968 10000)){ 969 dev_err(qmp->dev, "FREQ_DONE not ready\n"); 970 return -ETIMEDOUT; 971 } 972 973 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V2_COM_CMN_STATUS, 974 status, 975 ((status & BIT(1)) > 0), 976 500, 977 10000)){ 978 dev_err(qmp->dev, "PLL_LOCKED not ready\n"); 979 return -ETIMEDOUT; 980 } 981 982 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 983 984 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, 985 status, 986 ((status & BIT(0)) > 0), 987 500, 988 10000)){ 989 dev_err(qmp->dev, "TSYNC_DONE not ready\n"); 990 return -ETIMEDOUT; 991 } 992 993 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, 994 status, 995 ((status & BIT(1)) > 0), 996 500, 997 10000)){ 998 dev_err(qmp->dev, "PHY_READY not ready\n"); 999 return -ETIMEDOUT; 1000 } 1001 1002 writel(0x3f, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1003 writel(0x10, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1004 writel(0x0a, qmp->dp_tx + QSERDES_V3_TX_TX_POL_INV); 1005 writel(0x3f, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1006 writel(0x10, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1007 writel(0x0a, qmp->dp_tx2 + QSERDES_V3_TX_TX_POL_INV); 1008 1009 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1010 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1011 1012 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, 1013 status, 1014 ((status & BIT(1)) > 0), 1015 500, 1016 10000)){ 1017 dev_err(qmp->dev, "PHY_READY not ready\n"); 1018 return -ETIMEDOUT; 1019 } 1020 1021 return 0; 1022 } 1023 1024 static int qcs615_qmp_calibrate_dp_phy(struct qmp_usbc *qmp) 1025 { 1026 static const u8 cfg1_settings[] = {0x13, 0x23, 0x1d}; 1027 u8 val; 1028 1029 qmp->dp_aux_cfg++; 1030 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1031 val = cfg1_settings[qmp->dp_aux_cfg]; 1032 1033 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1034 1035 return 0; 1036 } 1037 1038 static int qmp_usbc_usb_power_on(struct phy *phy) 1039 { 1040 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1041 const struct qmp_phy_cfg *cfg = qmp->cfg; 1042 void __iomem *status; 1043 unsigned int val; 1044 int ret; 1045 1046 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1047 1048 /* Use software based port select and switch on typec orientation */ 1049 val = SW_PORTSELECT_MUX; 1050 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 1051 val |= SW_PORTSELECT_VAL; 1052 writel(val, qmp->pcs_misc); 1053 1054 qmp_configure(qmp->dev, qmp->serdes, cfg->serdes_tbl, 1055 cfg->serdes_tbl_num); 1056 1057 ret = clk_prepare_enable(qmp->pipe_clk); 1058 if (ret) { 1059 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1060 return ret; 1061 } 1062 1063 /* Tx, Rx, and PCS configurations */ 1064 qmp_configure_lane(qmp->dev, qmp->tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 1065 qmp_configure_lane(qmp->dev, qmp->rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 1066 1067 qmp_configure_lane(qmp->dev, qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 1068 qmp_configure_lane(qmp->dev, qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 1069 1070 qmp_configure(qmp->dev, qmp->pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1071 1072 /* Pull PHY out of reset state */ 1073 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1074 1075 /* start SerDes and Phy-Coding-Sublayer */ 1076 qphy_setbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 1077 1078 status = qmp->pcs + cfg->regs[QPHY_PCS_STATUS]; 1079 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 1080 PHY_INIT_COMPLETE_TIMEOUT); 1081 if (ret) { 1082 dev_err(qmp->dev, "phy initialization timed-out\n"); 1083 goto err_disable_pipe_clk; 1084 } 1085 1086 return 0; 1087 1088 err_disable_pipe_clk: 1089 clk_disable_unprepare(qmp->pipe_clk); 1090 1091 return ret; 1092 } 1093 1094 static int qmp_usbc_usb_power_off(struct phy *phy) 1095 { 1096 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1097 const struct qmp_phy_cfg *cfg = qmp->cfg; 1098 1099 clk_disable_unprepare(qmp->pipe_clk); 1100 1101 /* PHY reset */ 1102 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1103 1104 /* stop SerDes and Phy-Coding-Sublayer */ 1105 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 1106 SERDES_START | PCS_START); 1107 1108 /* Put PHY into POWER DOWN state: active low */ 1109 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1110 SW_PWRDN); 1111 1112 return 0; 1113 } 1114 1115 static int qmp_usbc_check_phy_status(struct qmp_usbc *qmp, bool is_dp) 1116 { 1117 if ((is_dp && qmp->usb_init_count) || 1118 (!is_dp && qmp->dp_init_count)) { 1119 dev_err(qmp->dev, 1120 "PHY is configured for %s, can not enable %s\n", 1121 is_dp ? "USB" : "DP", is_dp ? "DP" : "USB"); 1122 return -EBUSY; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int qmp_usbc_usb_enable(struct phy *phy) 1129 { 1130 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1131 int ret; 1132 1133 mutex_lock(&qmp->phy_mutex); 1134 1135 ret = qmp_usbc_check_phy_status(qmp, false); 1136 if (ret) 1137 goto out_unlock; 1138 1139 ret = qmp_usbc_com_init(phy); 1140 if (ret) 1141 goto out_unlock; 1142 1143 qmp_usbc_set_phy_mode(qmp, false); 1144 1145 ret = qmp_usbc_usb_power_on(phy); 1146 if (ret) { 1147 qmp_usbc_com_exit(phy); 1148 goto out_unlock; 1149 } 1150 1151 qmp->usb_init_count++; 1152 out_unlock: 1153 mutex_unlock(&qmp->phy_mutex); 1154 1155 return ret; 1156 } 1157 1158 static int qmp_usbc_usb_disable(struct phy *phy) 1159 { 1160 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1161 int ret; 1162 1163 qmp->usb_init_count--; 1164 ret = qmp_usbc_usb_power_off(phy); 1165 if (ret) 1166 return ret; 1167 return qmp_usbc_com_exit(phy); 1168 } 1169 1170 static int qmp_usbc_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 1171 { 1172 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1173 1174 qmp->mode = mode; 1175 1176 return 0; 1177 } 1178 1179 static int qmp_usbc_dp_enable(struct phy *phy) 1180 { 1181 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1182 const struct qmp_phy_cfg *cfg = qmp->cfg; 1183 int ret; 1184 1185 if (qmp->dp_init_count) { 1186 dev_err(qmp->dev, "DP already inited\n"); 1187 return 0; 1188 } 1189 1190 mutex_lock(&qmp->phy_mutex); 1191 1192 ret = qmp_usbc_check_phy_status(qmp, true); 1193 if (ret) 1194 goto dp_init_unlock; 1195 1196 ret = qmp_usbc_com_init(phy); 1197 if (ret) 1198 goto dp_init_unlock; 1199 1200 qmp_usbc_set_phy_mode(qmp, true); 1201 1202 cfg->dp_aux_init(qmp); 1203 1204 qmp->dp_init_count++; 1205 1206 dp_init_unlock: 1207 mutex_unlock(&qmp->phy_mutex); 1208 return ret; 1209 } 1210 1211 static int qmp_usbc_dp_disable(struct phy *phy) 1212 { 1213 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1214 1215 mutex_lock(&qmp->phy_mutex); 1216 1217 qmp_usbc_com_exit(phy); 1218 1219 qmp->dp_init_count--; 1220 1221 mutex_unlock(&qmp->phy_mutex); 1222 1223 return 0; 1224 } 1225 1226 static int qmp_usbc_dp_configure(struct phy *phy, union phy_configure_opts *opts) 1227 { 1228 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 1229 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1230 const struct qmp_phy_cfg *cfg = qmp->cfg; 1231 1232 mutex_lock(&qmp->phy_mutex); 1233 1234 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 1235 if (qmp->dp_opts.set_voltages) { 1236 cfg->configure_dp_tx(qmp); 1237 qmp->dp_opts.set_voltages = 0; 1238 } 1239 1240 mutex_unlock(&qmp->phy_mutex); 1241 1242 return 0; 1243 } 1244 1245 static int qmp_usbc_dp_calibrate(struct phy *phy) 1246 { 1247 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1248 const struct qmp_phy_cfg *cfg = qmp->cfg; 1249 int ret = 0; 1250 1251 mutex_lock(&qmp->phy_mutex); 1252 1253 if (cfg->calibrate_dp_phy) { 1254 ret = cfg->calibrate_dp_phy(qmp); 1255 if (ret) { 1256 dev_err(qmp->dev, "dp calibrate err(%d)\n", ret); 1257 mutex_unlock(&qmp->phy_mutex); 1258 return ret; 1259 } 1260 } 1261 1262 mutex_unlock(&qmp->phy_mutex); 1263 return 0; 1264 } 1265 1266 static int qmp_usbc_dp_serdes_init(struct qmp_usbc *qmp) 1267 { 1268 const struct qmp_phy_cfg *cfg = qmp->cfg; 1269 void __iomem *serdes = qmp->dp_serdes; 1270 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1271 1272 qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, 1273 cfg->dp_serdes_tbl_num); 1274 1275 switch (dp_opts->link_rate) { 1276 case 1620: 1277 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, 1278 cfg->serdes_tbl_rbr_num); 1279 break; 1280 case 2700: 1281 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, 1282 cfg->serdes_tbl_hbr_num); 1283 break; 1284 case 5400: 1285 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, 1286 cfg->serdes_tbl_hbr2_num); 1287 break; 1288 default: 1289 /* Other link rates aren't supported */ 1290 return -EINVAL; 1291 } 1292 1293 return 0; 1294 } 1295 1296 static int qmp_usbc_dp_power_on(struct phy *phy) 1297 { 1298 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1299 const struct qmp_phy_cfg *cfg = qmp->cfg; 1300 1301 void __iomem *tx = qmp->dp_tx; 1302 void __iomem *tx2 = qmp->dp_tx2; 1303 1304 /* 1305 * FIXME: SW_PORTSELECT handling for DP orientation flip is not implemented. 1306 * Expected: 1307 * - For standard lane mapping: configure SW_PORTSELECT in QSERDES_DP_PHY_CFG_1. 1308 * - For non-standard mapping: pass orientation to dp_ctrl and handle flip 1309 * via logical2physical lane remapping. 1310 */ 1311 1312 mutex_lock(&qmp->phy_mutex); 1313 1314 qmp_usbc_dp_serdes_init(qmp); 1315 1316 qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 1317 qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 1318 1319 /* Configure special DP tx tunings */ 1320 cfg->configure_dp_tx(qmp); 1321 1322 /* Configure link rate, swing, etc. */ 1323 cfg->configure_dp_phy(qmp); 1324 1325 mutex_unlock(&qmp->phy_mutex); 1326 1327 return 0; 1328 } 1329 1330 static int qmp_usbc_dp_power_off(struct phy *phy) 1331 { 1332 struct qmp_usbc *qmp = phy_get_drvdata(phy); 1333 1334 mutex_lock(&qmp->phy_mutex); 1335 1336 /* Assert DP PHY power down */ 1337 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1338 1339 mutex_unlock(&qmp->phy_mutex); 1340 1341 return 0; 1342 } 1343 1344 static const struct phy_ops qmp_usbc_usb_phy_ops = { 1345 .init = qmp_usbc_usb_enable, 1346 .exit = qmp_usbc_usb_disable, 1347 .set_mode = qmp_usbc_usb_set_mode, 1348 .owner = THIS_MODULE, 1349 }; 1350 1351 static const struct phy_ops qmp_usbc_dp_phy_ops = { 1352 .init = qmp_usbc_dp_enable, 1353 .exit = qmp_usbc_dp_disable, 1354 .configure = qmp_usbc_dp_configure, 1355 .calibrate = qmp_usbc_dp_calibrate, 1356 .power_on = qmp_usbc_dp_power_on, 1357 .power_off = qmp_usbc_dp_power_off, 1358 .owner = THIS_MODULE, 1359 }; 1360 1361 static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp) 1362 { 1363 const struct qmp_phy_cfg *cfg = qmp->cfg; 1364 void __iomem *pcs = qmp->pcs; 1365 u32 intr_mask; 1366 1367 if (qmp->mode == PHY_MODE_USB_HOST_SS || 1368 qmp->mode == PHY_MODE_USB_DEVICE_SS) 1369 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 1370 else 1371 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 1372 1373 /* Clear any pending interrupts status */ 1374 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1375 /* Writing 1 followed by 0 clears the interrupt */ 1376 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1377 1378 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1379 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 1380 1381 /* Enable required PHY autonomous mode interrupts */ 1382 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 1383 1384 /* Enable i/o clamp_n for autonomous mode */ 1385 if (qmp->tcsr_map && qmp->vls_clamp_reg) 1386 regmap_write(qmp->tcsr_map, qmp->vls_clamp_reg, 1); 1387 } 1388 1389 static void qmp_usbc_disable_autonomous_mode(struct qmp_usbc *qmp) 1390 { 1391 const struct qmp_phy_cfg *cfg = qmp->cfg; 1392 void __iomem *pcs = qmp->pcs; 1393 1394 /* Disable i/o clamp_n on resume for normal mode */ 1395 if (qmp->tcsr_map && qmp->vls_clamp_reg) 1396 regmap_write(qmp->tcsr_map, qmp->vls_clamp_reg, 0); 1397 1398 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1399 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 1400 1401 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1402 /* Writing 1 followed by 0 clears the interrupt */ 1403 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1404 } 1405 1406 static int __maybe_unused qmp_usbc_runtime_suspend(struct device *dev) 1407 { 1408 struct qmp_usbc *qmp = dev_get_drvdata(dev); 1409 1410 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 1411 1412 if (!qmp->usb_init_count && !qmp->dp_init_count) { 1413 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1414 return 0; 1415 } 1416 1417 qmp_usbc_enable_autonomous_mode(qmp); 1418 1419 clk_disable_unprepare(qmp->pipe_clk); 1420 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 1421 1422 return 0; 1423 } 1424 1425 static int __maybe_unused qmp_usbc_runtime_resume(struct device *dev) 1426 { 1427 struct qmp_usbc *qmp = dev_get_drvdata(dev); 1428 int ret = 0; 1429 1430 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 1431 1432 if (!qmp->usb_init_count && !qmp->dp_init_count) { 1433 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1434 return 0; 1435 } 1436 1437 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 1438 if (ret) 1439 return ret; 1440 1441 ret = clk_prepare_enable(qmp->pipe_clk); 1442 if (ret) { 1443 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 1444 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 1445 return ret; 1446 } 1447 1448 qmp_usbc_disable_autonomous_mode(qmp); 1449 1450 return 0; 1451 } 1452 1453 static const struct dev_pm_ops qmp_usbc_pm_ops = { 1454 SET_RUNTIME_PM_OPS(qmp_usbc_runtime_suspend, 1455 qmp_usbc_runtime_resume, NULL) 1456 }; 1457 1458 static int qmp_usbc_reset_init(struct qmp_usbc *qmp, 1459 const char *const *reset_list, 1460 int num_resets) 1461 { 1462 struct device *dev = qmp->dev; 1463 int i; 1464 int ret; 1465 1466 qmp->resets = devm_kcalloc(dev, num_resets, 1467 sizeof(*qmp->resets), GFP_KERNEL); 1468 if (!qmp->resets) 1469 return -ENOMEM; 1470 1471 for (i = 0; i < num_resets; i++) 1472 qmp->resets[i].id = reset_list[i]; 1473 1474 qmp->num_resets = num_resets; 1475 1476 ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets); 1477 if (ret) 1478 return dev_err_probe(dev, ret, "failed to get resets\n"); 1479 1480 return 0; 1481 } 1482 1483 static int qmp_usbc_clk_init(struct qmp_usbc *qmp) 1484 { 1485 struct device *dev = qmp->dev; 1486 int num = ARRAY_SIZE(qmp_usbc_phy_clk_l); 1487 int i; 1488 1489 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 1490 if (!qmp->clks) 1491 return -ENOMEM; 1492 1493 for (i = 0; i < num; i++) 1494 qmp->clks[i].id = qmp_usbc_phy_clk_l[i]; 1495 1496 qmp->num_clks = num; 1497 1498 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 1499 } 1500 1501 static struct clk_hw *qmp_usbc_clks_hw_get(struct of_phandle_args *clkspec, void *data) 1502 { 1503 struct qmp_usbc *qmp = data; 1504 1505 if (clkspec->args_count == 0) 1506 return &qmp->pipe_clk_fixed.hw; 1507 1508 switch (clkspec->args[0]) { 1509 case QMP_USB43DP_USB3_PIPE_CLK: 1510 return &qmp->pipe_clk_fixed.hw; 1511 case QMP_USB43DP_DP_LINK_CLK: 1512 return &qmp->dp_link_hw; 1513 case QMP_USB43DP_DP_VCO_DIV_CLK: 1514 return &qmp->dp_pixel_hw; 1515 } 1516 1517 return ERR_PTR(-EINVAL); 1518 } 1519 1520 /* 1521 * Register a fixed rate pipe clock. 1522 * 1523 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 1524 * controls it. The <s>_pipe_clk coming out of the GCC is requested 1525 * by the PHY driver for its operations. 1526 * We register the <s>_pipe_clksrc here. The gcc driver takes care 1527 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 1528 * Below picture shows this relationship. 1529 * 1530 * +---------------+ 1531 * | PHY block |<<---------------------------------------+ 1532 * | | | 1533 * | +-------+ | +-----+ | 1534 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 1535 * clk | +-------+ | +-----+ 1536 * +---------------+ 1537 */ 1538 static int phy_pipe_clk_register(struct qmp_usbc *qmp, struct device_node *np) 1539 { 1540 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 1541 struct clk_init_data init = { }; 1542 char name[64]; 1543 int ret; 1544 1545 ret = of_property_read_string(np, "clock-output-names", &init.name); 1546 if (ret) { 1547 /* Clock name is not mandatory. */ 1548 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 1549 init.name = name; 1550 } 1551 1552 init.ops = &clk_fixed_rate_ops; 1553 1554 /* controllers using QMP phys use 125MHz pipe clock interface */ 1555 fixed->fixed_rate = 125000000; 1556 fixed->hw.init = &init; 1557 1558 return devm_clk_hw_register(qmp->dev, &fixed->hw); 1559 } 1560 1561 /* 1562 * Display Port PLL driver block diagram for branch clocks 1563 * 1564 * +------------------------------+ 1565 * | DP_VCO_CLK | 1566 * | | 1567 * | +-------------------+ | 1568 * | | (DP PLL/VCO) | | 1569 * | +---------+---------+ | 1570 * | v | 1571 * | +----------+-----------+ | 1572 * | | hsclk_divsel_clk_src | | 1573 * | +----------+-----------+ | 1574 * +------------------------------+ 1575 * | 1576 * +---------<---------v------------>----------+ 1577 * | | 1578 * +--------v----------------+ | 1579 * | dp_phy_pll_link_clk | | 1580 * | link_clk | | 1581 * +--------+----------------+ | 1582 * | | 1583 * | | 1584 * v v 1585 * Input to DISPCC block | 1586 * for link clk, crypto clk | 1587 * and interface clock | 1588 * | 1589 * | 1590 * +--------<------------+-----------------+---<---+ 1591 * | | | 1592 * +----v---------+ +--------v-----+ +--------v------+ 1593 * | vco_divided | | vco_divided | | vco_divided | 1594 * | _clk_src | | _clk_src | | _clk_src | 1595 * | | | | | | 1596 * |divsel_six | | divsel_two | | divsel_four | 1597 * +-------+------+ +-----+--------+ +--------+------+ 1598 * | | | 1599 * v---->----------v-------------<------v 1600 * | 1601 * +----------+-----------------+ 1602 * | dp_phy_pll_vco_div_clk | 1603 * +---------+------------------+ 1604 * | 1605 * v 1606 * Input to DISPCC block 1607 * for DP pixel clock 1608 * 1609 */ 1610 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 1611 { 1612 switch (req->rate) { 1613 case 1620000000UL / 2: 1614 case 2700000000UL / 2: 1615 /* 5.4 is same link rate as 2.7GHz, i.e. div 4 */ 1616 return 0; 1617 default: 1618 return -EINVAL; 1619 } 1620 } 1621 1622 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1623 { 1624 const struct qmp_usbc *qmp; 1625 const struct phy_configure_opts_dp *dp_opts; 1626 1627 qmp = container_of(hw, struct qmp_usbc, dp_pixel_hw); 1628 1629 dp_opts = &qmp->dp_opts; 1630 1631 switch (dp_opts->link_rate) { 1632 case 1620: 1633 return 1620000000UL / 2; 1634 case 2700: 1635 return 2700000000UL / 2; 1636 case 5400: 1637 return 5400000000UL / 4; 1638 default: 1639 return 0; 1640 } 1641 } 1642 1643 static const struct clk_ops qmp_dp_pixel_clk_ops = { 1644 .determine_rate = qmp_dp_pixel_clk_determine_rate, 1645 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 1646 }; 1647 1648 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 1649 { 1650 switch (req->rate) { 1651 case 162000000: 1652 case 270000000: 1653 case 540000000: 1654 return 0; 1655 default: 1656 return -EINVAL; 1657 } 1658 } 1659 1660 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1661 { 1662 const struct qmp_usbc *qmp; 1663 const struct phy_configure_opts_dp *dp_opts; 1664 1665 qmp = container_of(hw, struct qmp_usbc, dp_link_hw); 1666 dp_opts = &qmp->dp_opts; 1667 1668 switch (dp_opts->link_rate) { 1669 case 1620: 1670 case 2700: 1671 case 5400: 1672 return dp_opts->link_rate * 100000; 1673 default: 1674 return 0; 1675 } 1676 } 1677 1678 static const struct clk_ops qmp_dp_link_clk_ops = { 1679 .determine_rate = qmp_dp_link_clk_determine_rate, 1680 .recalc_rate = qmp_dp_link_clk_recalc_rate, 1681 }; 1682 1683 static int phy_dp_clks_register(struct qmp_usbc *qmp, struct device_node *np) 1684 { 1685 struct clk_init_data init = { }; 1686 char name[64]; 1687 int ret; 1688 1689 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 1690 init.ops = &qmp_dp_link_clk_ops; 1691 init.name = name; 1692 qmp->dp_link_hw.init = &init; 1693 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 1694 if (ret < 0) { 1695 dev_err(qmp->dev, "link clk reg fail ret=%d\n", ret); 1696 return ret; 1697 } 1698 1699 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 1700 init.ops = &qmp_dp_pixel_clk_ops; 1701 init.name = name; 1702 qmp->dp_pixel_hw.init = &init; 1703 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 1704 if (ret) { 1705 dev_err(qmp->dev, "pxl clk reg fail ret=%d\n", ret); 1706 return ret; 1707 } 1708 1709 return 0; 1710 } 1711 1712 static void phy_clk_release_provider(void *res) 1713 { 1714 of_clk_del_provider(res); 1715 } 1716 1717 static int qmp_usbc_register_clocks(struct qmp_usbc *qmp, struct device_node *np) 1718 { 1719 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 1720 int ret; 1721 1722 ret = phy_pipe_clk_register(qmp, np); 1723 if (ret) 1724 return ret; 1725 1726 if (qmp->dp_serdes) { 1727 ret = phy_dp_clks_register(qmp, np); 1728 if (ret) 1729 return ret; 1730 } 1731 1732 if (np == qmp->dev->of_node) 1733 return devm_of_clk_add_hw_provider(qmp->dev, qmp_usbc_clks_hw_get, qmp); 1734 1735 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 1736 if (ret) 1737 return ret; 1738 1739 /* 1740 * Roll a devm action because the clock provider is the child node, but 1741 * the child node is not actually a device. 1742 */ 1743 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 1744 } 1745 1746 #if IS_ENABLED(CONFIG_TYPEC) 1747 static int qmp_usbc_typec_switch_set(struct typec_switch_dev *sw, 1748 enum typec_orientation orientation) 1749 { 1750 struct qmp_usbc *qmp = typec_switch_get_drvdata(sw); 1751 1752 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 1753 return 0; 1754 1755 mutex_lock(&qmp->phy_mutex); 1756 qmp->orientation = orientation; 1757 1758 if (qmp->usb_init_count) { 1759 qmp_usbc_usb_power_off(qmp->usb_phy); 1760 qmp_usbc_com_exit(qmp->usb_phy); 1761 1762 qmp_usbc_com_init(qmp->usb_phy); 1763 qmp_usbc_set_phy_mode(qmp, false); 1764 qmp_usbc_usb_power_on(qmp->usb_phy); 1765 } 1766 1767 mutex_unlock(&qmp->phy_mutex); 1768 1769 return 0; 1770 } 1771 1772 static void qmp_usbc_typec_unregister(void *data) 1773 { 1774 struct qmp_usbc *qmp = data; 1775 1776 typec_switch_unregister(qmp->sw); 1777 } 1778 1779 static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp) 1780 { 1781 struct typec_switch_desc sw_desc = {}; 1782 struct device *dev = qmp->dev; 1783 1784 sw_desc.drvdata = qmp; 1785 sw_desc.fwnode = dev->fwnode; 1786 sw_desc.set = qmp_usbc_typec_switch_set; 1787 qmp->sw = typec_switch_register(dev, &sw_desc); 1788 if (IS_ERR(qmp->sw)) { 1789 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 1790 return PTR_ERR(qmp->sw); 1791 } 1792 1793 return devm_add_action_or_reset(dev, qmp_usbc_typec_unregister, qmp); 1794 } 1795 #else 1796 static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp) 1797 { 1798 return 0; 1799 } 1800 #endif 1801 1802 static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *qmp, struct device_node *np) 1803 { 1804 struct platform_device *pdev = to_platform_device(qmp->dev); 1805 struct device *dev = qmp->dev; 1806 int ret; 1807 1808 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 1809 if (IS_ERR(qmp->serdes)) 1810 return PTR_ERR(qmp->serdes); 1811 1812 /* 1813 * Get memory resources for the PHY: 1814 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 1815 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 1816 * For single lane PHYs: pcs_misc (optional) -> 3. 1817 */ 1818 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 1819 if (IS_ERR(qmp->tx)) 1820 return PTR_ERR(qmp->tx); 1821 1822 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 1823 if (IS_ERR(qmp->rx)) 1824 return PTR_ERR(qmp->rx); 1825 1826 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 1827 if (IS_ERR(qmp->pcs)) 1828 return PTR_ERR(qmp->pcs); 1829 1830 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 1831 if (IS_ERR(qmp->tx2)) 1832 return PTR_ERR(qmp->tx2); 1833 1834 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 1835 if (IS_ERR(qmp->rx2)) 1836 return PTR_ERR(qmp->rx2); 1837 1838 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 1839 if (IS_ERR(qmp->pcs_misc)) { 1840 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 1841 qmp->pcs_misc = NULL; 1842 } 1843 1844 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 1845 if (IS_ERR(qmp->pipe_clk)) { 1846 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 1847 "failed to get pipe clock\n"); 1848 } 1849 1850 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 1851 if (ret < 0) 1852 return ret; 1853 1854 qmp->num_clks = ret; 1855 1856 ret = qmp_usbc_reset_init(qmp, usb3phy_legacy_reset_l, 1857 ARRAY_SIZE(usb3phy_legacy_reset_l)); 1858 if (ret) 1859 return ret; 1860 1861 return 0; 1862 } 1863 1864 static int qmp_usbc_parse_dt(struct qmp_usbc *qmp) 1865 { 1866 struct platform_device *pdev = to_platform_device(qmp->dev); 1867 const struct qmp_phy_cfg *cfg = qmp->cfg; 1868 const struct qmp_usbc_offsets *offs = cfg->offsets; 1869 struct device *dev = qmp->dev; 1870 void __iomem *base; 1871 int ret; 1872 1873 if (!offs) 1874 return -EINVAL; 1875 1876 base = devm_platform_ioremap_resource(pdev, 0); 1877 if (IS_ERR(base)) 1878 return PTR_ERR(base); 1879 1880 if (offs->dp_serdes) { 1881 qmp->dp_serdes = base + offs->dp_serdes; 1882 qmp->dp_tx = base + offs->dp_txa; 1883 qmp->dp_tx2 = base + offs->dp_txb; 1884 qmp->dp_dp_phy = base + offs->dp_dp_phy; 1885 } 1886 1887 qmp->serdes = base + offs->serdes; 1888 qmp->pcs = base + offs->pcs; 1889 if (offs->pcs_misc) 1890 qmp->pcs_misc = base + offs->pcs_misc; 1891 qmp->tx = base + offs->tx; 1892 qmp->rx = base + offs->rx; 1893 1894 qmp->tx2 = base + offs->tx2; 1895 qmp->rx2 = base + offs->rx2; 1896 1897 ret = qmp_usbc_clk_init(qmp); 1898 if (ret) 1899 return ret; 1900 1901 qmp->pipe_clk = devm_clk_get(dev, "pipe"); 1902 if (IS_ERR(qmp->pipe_clk)) { 1903 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 1904 "failed to get pipe clock\n"); 1905 } 1906 1907 ret = qmp_usbc_reset_init(qmp, cfg->reset_list, cfg->num_resets); 1908 if (ret) 1909 return ret; 1910 1911 return 0; 1912 } 1913 1914 static int qmp_usbc_parse_tcsr(struct qmp_usbc *qmp) 1915 { 1916 struct of_phandle_args tcsr_args; 1917 struct device *dev = qmp->dev; 1918 int ret, args_count; 1919 1920 args_count = of_property_count_u32_elems(dev->of_node, "qcom,tcsr-reg"); 1921 args_count = args_count - 1; 1922 ret = of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1923 args_count, 0, &tcsr_args); 1924 if (ret == -ENOENT) 1925 return 0; 1926 else if (ret < 0) 1927 return dev_err_probe(dev, ret, "Failed to parse qcom,tcsr-reg\n"); 1928 1929 qmp->tcsr_map = syscon_node_to_regmap(tcsr_args.np); 1930 of_node_put(tcsr_args.np); 1931 if (IS_ERR(qmp->tcsr_map)) 1932 return PTR_ERR(qmp->tcsr_map); 1933 1934 qmp->vls_clamp_reg = tcsr_args.args[0]; 1935 1936 if (args_count > 1) 1937 qmp->dp_phy_mode_reg = tcsr_args.args[1]; 1938 1939 return 0; 1940 } 1941 1942 static struct phy *qmp_usbc_phy_xlate(struct device *dev, const struct of_phandle_args *args) 1943 { 1944 struct qmp_usbc *qmp = dev_get_drvdata(dev); 1945 1946 if (args->args_count == 0) 1947 return qmp->usb_phy; 1948 1949 switch (args->args[0]) { 1950 case QMP_USB43DP_USB3_PHY: 1951 return qmp->usb_phy; 1952 case QMP_USB43DP_DP_PHY: 1953 return qmp->dp_phy ?: ERR_PTR(-ENODEV); 1954 } 1955 1956 return ERR_PTR(-EINVAL); 1957 } 1958 1959 static int qmp_usbc_probe(struct platform_device *pdev) 1960 { 1961 struct device *dev = &pdev->dev; 1962 struct phy_provider *phy_provider; 1963 struct device_node *np; 1964 struct qmp_usbc *qmp; 1965 int ret; 1966 1967 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 1968 if (!qmp) 1969 return -ENOMEM; 1970 1971 qmp->dev = dev; 1972 dev_set_drvdata(dev, qmp); 1973 1974 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 1975 1976 qmp->cfg = of_device_get_match_data(dev); 1977 if (!qmp->cfg) 1978 return -EINVAL; 1979 1980 mutex_init(&qmp->phy_mutex); 1981 1982 ret = devm_regulator_bulk_get_const(qmp->dev, qmp->cfg->num_vregs, 1983 qmp->cfg->vreg_list, &qmp->vregs); 1984 if (ret) 1985 return ret; 1986 1987 ret = qmp_usbc_typec_switch_register(qmp); 1988 if (ret) 1989 return ret; 1990 1991 ret = qmp_usbc_parse_tcsr(qmp); 1992 if (ret) 1993 return ret; 1994 1995 /* Check for legacy binding with child node. */ 1996 np = of_get_child_by_name(dev->of_node, "phy"); 1997 if (np) { 1998 ret = qmp_usbc_parse_dt_legacy(qmp, np); 1999 } else { 2000 np = of_node_get(dev->of_node); 2001 ret = qmp_usbc_parse_dt(qmp); 2002 } 2003 if (ret) 2004 goto err_node_put; 2005 2006 /* 2007 * Enable runtime PM before creating the PHYs, phy_create() only enables 2008 * it on the PHY devices if already enabled on the parent. Hold a usage 2009 * reference so callbacks cannot run until the PHY is ready. 2010 */ 2011 pm_runtime_get_noresume(dev); 2012 pm_runtime_set_active(dev); 2013 ret = devm_pm_runtime_enable(dev); 2014 if (ret) 2015 goto err_pm_put; 2016 /* 2017 * Prevent runtime pm from being ON by default. Users can enable 2018 * it using power/control in sysfs. 2019 */ 2020 pm_runtime_forbid(dev); 2021 2022 ret = qmp_usbc_register_clocks(qmp, np); 2023 if (ret) 2024 goto err_pm_put; 2025 2026 qmp->usb_phy = devm_phy_create(dev, np, &qmp_usbc_usb_phy_ops); 2027 if (IS_ERR(qmp->usb_phy)) { 2028 ret = PTR_ERR(qmp->usb_phy); 2029 dev_err(dev, "failed to create PHY: %d\n", ret); 2030 goto err_pm_put; 2031 } 2032 2033 phy_set_drvdata(qmp->usb_phy, qmp); 2034 2035 if (qmp->dp_serdes) { 2036 qmp->dp_phy = devm_phy_create(dev, np, &qmp_usbc_dp_phy_ops); 2037 if (IS_ERR(qmp->dp_phy)) { 2038 ret = PTR_ERR(qmp->dp_phy); 2039 dev_err(dev, "failed to create PHY: %d\n", ret); 2040 goto err_pm_put; 2041 } 2042 phy_set_drvdata(qmp->dp_phy, qmp); 2043 } 2044 2045 phy_provider = devm_of_phy_provider_register(dev, qmp_usbc_phy_xlate); 2046 if (IS_ERR(phy_provider)) { 2047 ret = PTR_ERR(phy_provider); 2048 goto err_pm_put; 2049 } 2050 2051 of_node_put(np); 2052 2053 pm_runtime_put(dev); 2054 2055 return 0; 2056 2057 err_pm_put: 2058 pm_runtime_put_noidle(dev); 2059 err_node_put: 2060 of_node_put(np); 2061 return ret; 2062 } 2063 2064 static const struct of_device_id qmp_usbc_of_match_table[] = { 2065 { 2066 .compatible = "qcom,msm8998-qmp-usb3-phy", 2067 .data = &msm8998_usb3phy_cfg, 2068 }, { 2069 .compatible = "qcom,qcm2290-qmp-usb3-phy", 2070 .data = &qcm2290_usb3phy_cfg, 2071 }, { 2072 .compatible = "qcom,qcs615-qmp-usb3-dp-phy", 2073 .data = &qcs615_usb3dp_phy_cfg, 2074 }, { 2075 .compatible = "qcom,qcs615-qmp-usb3-phy", 2076 .data = &qcs615_usb3phy_cfg, 2077 }, { 2078 .compatible = "qcom,sdm660-qmp-usb3-phy", 2079 .data = &sdm660_usb3phy_cfg, 2080 }, { 2081 .compatible = "qcom,shikra-qmp-usb3-dp-phy", 2082 .data = &shikra_usb3dp_phy_cfg, 2083 }, { 2084 .compatible = "qcom,sm6115-qmp-usb3-phy", 2085 .data = &qcm2290_usb3phy_cfg, 2086 }, 2087 { }, 2088 }; 2089 MODULE_DEVICE_TABLE(of, qmp_usbc_of_match_table); 2090 2091 static struct platform_driver qmp_usbc_driver = { 2092 .probe = qmp_usbc_probe, 2093 .driver = { 2094 .name = "qcom-qmp-usbc-phy", 2095 .pm = &qmp_usbc_pm_ops, 2096 .of_match_table = qmp_usbc_of_match_table, 2097 }, 2098 }; 2099 2100 module_platform_driver(qmp_usbc_driver); 2101 2102 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2103 MODULE_DESCRIPTION("Qualcomm QMP USB-C PHY driver"); 2104 MODULE_LICENSE("GPL"); 2105