xref: /linux/drivers/phy/qualcomm/phy-qcom-qmp-usb43-qserdes-com-v8.h (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e)
1*5b289913SWesley Cheng /* SPDX-License-Identifier: GPL-2.0 */
2*5b289913SWesley Cheng /*
3*5b289913SWesley Cheng  * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4*5b289913SWesley Cheng  */
5*5b289913SWesley Cheng 
6*5b289913SWesley Cheng #ifndef QCOM_PHY_QMP_USB43_QSERDES_COM_V8_H_
7*5b289913SWesley Cheng #define QCOM_PHY_QMP_USB43_QSERDES_COM_V8_H_
8*5b289913SWesley Cheng 
9*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE1		0x000
10*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE1		0x004
11*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE3_MODE1		0x008
12*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CLK_EP_DIV_MODE1			0x00c
13*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CP_CTRL_MODE1			0x010
14*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1			0x014
15*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1			0x018
16*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CORECLK_DIV_MODE1			0x01c
17*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP1_MODE1			0x020
18*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP2_MODE1			0x024
19*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEC_START_MODE1			0x028
20*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEC_START_MSB_MODE1		0x02c
21*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE1		0x030
22*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE1		0x034
23*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE1		0x038
24*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_HSCLK_SEL_1			0x03c
25*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE1		0x040
26*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE1		0x044
27*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE1_MODE1			0x048
28*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE2_MODE1			0x04c
29*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE1		0x050
30*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE1		0x054
31*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0		0x058
32*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0		0x05c
33*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0		0x060
34*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0		0x064
35*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE3_MODE0		0x068
36*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CLK_EP_DIV_MODE0			0x06c
37*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CP_CTRL_MODE0			0x070
38*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0			0x074
39*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0			0x078
40*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0			0x07c
41*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0			0x080
42*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0			0x084
43*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEC_START_MODE0			0x088
44*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEC_START_MSB_MODE0		0x08c
45*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0		0x090
46*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0		0x094
47*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0		0x098
48*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_HSCLK_HS_SWITCH_SEL_1		0x09c
49*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0		0x0a0
50*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE0		0x0a4
51*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0			0x0a8
52*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0			0x0ac
53*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ATB_SEL1				0x0b0
54*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ATB_SEL2				0x0b4
55*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_FREQ_UPDATE			0x0b8
56*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BG_TIMER				0x0bc
57*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_EN_CENTER			0x0c0
58*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_ADJ_PER1			0x0c4
59*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_ADJ_PER2			0x0c8
60*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_PER1				0x0cc
61*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_PER2				0x0d0
62*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_POST_DIV				0x0d4
63*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_POST_DIV_MUX			0x0d8
64*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN		0x0dc
65*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CLK_ENABLE1			0x0e0
66*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SYS_CLK_CTRL			0x0e4
67*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE			0x0e8
68*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_EN				0x0ec
69*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEBUG_BUS_OVRD			0x0f0
70*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_IVCO				0x0f4
71*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_IVCO_MODE1			0x0f8
72*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_IETRIM				0x0fc
73*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_IPTRIM				0x100
74*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_EP_CLOCK_DETECT_CTRL		0x104
75*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_CNTRL				0x108
76*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIAS_EN_CTRL_BY_PSM		0x10c
77*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SYSCLK_EN_SEL			0x110
78*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CML_SYSCLK_SEL			0x114
79*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_RESETSM_CNTRL			0x118
80*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_RESETSM_CNTRL2			0x11c
81*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP_EN			0x120
82*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP_CFG			0x124
83*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_INITVAL			0x128
84*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_EN			0x12c
85*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_P_PATH_GAIN0		0x130
86*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_P_PATH_GAIN1		0x134
87*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCOCAL_DEADMAN_CTRL		0x138
88*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE_CTRL			0x13c
89*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE_MAP			0x140
90*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE_INITVAL1			0x144
91*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE_INITVAL2			0x148
92*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE_MINVAL1			0x14c
93*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE_MINVAL2			0x150
94*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE_MAXVAL1			0x154
95*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE_MAXVAL2			0x158
96*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE_TIMER1			0x15c
97*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE_TIMER2			0x160
98*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CLK_SELECT				0x164
99*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_ANALOG				0x168
100*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SW_RESET				0x16c
101*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CORE_CLK_EN			0x170
102*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_CONFIG_1			0x174
103*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_CONFIG_3			0x178
104*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_RATE_OVERRIDE			0x17c
105*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL			0x180
106*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEBUG_BUS_SEL			0x184
107*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_MISC1				0x188
108*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_MODE				0x18c
109*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD			0x190
110*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD1			0x194
111*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD2			0x198
112*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_DC_LEVEL_CTRL			0x19c
113*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1		0x1a0
114*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ADDITIONAL_CTRL_1			0x1a4
115*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_1		0x1a8
116*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_2		0x1ac
117*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_3		0x1b0
118*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_AUTO_GAIN_ADJ_CTRL_4		0x1b4
119*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC			0x1b8
120*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_2			0x1bc
121*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_3			0x1c0
122*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_4			0x1c4
123*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_5			0x1c8
124*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE2		0x1cc
125*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE2		0x1d0
126*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SSC_STEP_SIZE3_MODE2		0x1d4
127*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CLK_EP_DIV_MODE2			0x1d8
128*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CP_CTRL_MODE2			0x1dc
129*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_RCTRL_MODE2			0x1e0
130*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_CCTRL_MODE2			0x1e4
131*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CORECLK_DIV_MODE2			0x1e8
132*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP1_MODE2			0x1ec
133*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP2_MODE2			0x1f0
134*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEC_START_MODE2			0x1f4
135*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEC_START_MSB_MODE2		0x1f8
136*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE2		0x1fc
137*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE2		0x200
138*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE2		0x204
139*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE2		0x208
140*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE2		0x20c
141*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE1_MODE2			0x210
142*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_TUNE2_MODE2			0x214
143*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_IVCO_MODE2			0x218
144*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_HSCLK_SEL_2			0x21c
145*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE2		0x220
146*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE2		0x224
147*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_HSCLK_HS_SWITCH_SEL_2		0x228
148*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_CONFIG_2			0x22c
149*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_2		0x230
150*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_0			0x234
151*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_1			0x238
152*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_2			0x23c
153*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_3			0x240
154*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_4			0x244
155*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_IVCOCAL_CONFIG_5			0x248
156*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP1_EARLY_MODE0		0x24c
157*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP2_EARLY_MODE0		0x250
158*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP1_EARLY_MODE1		0x254
159*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP2_EARLY_MODE1		0x258
160*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP1_EARLY_MODE2		0x25c
161*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LOCK_CMP2_EARLY_MODE2		0x260
162*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_EARLY_LOCK_CONFIG_0		0x264
163*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_EARLY_LOCK_CONFIG_1		0x268
164*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ADAPTIVE_ANALOG_CONFIG		0x26c
165*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CP_CTRL_ADAPTIVE_MODE0		0x270
166*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_RCCTRL_ADAPTIVE_MODE0		0x274
167*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_CCTRL_ADAPTIVE_MODE0		0x278
168*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CP_CTRL_ADAPTIVE_MODE1		0x27c
169*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_RCCTRL_ADAPTIVE_MODE1		0x280
170*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_CCTRL_ADAPTIVE_MODE1		0x284
171*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CP_CTRL_ADAPTIVE_MODE2		0x288
172*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_RCCTRL_ADAPTIVE_MODE2		0x28c
173*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_CCTRL_ADAPTIVE_MODE2		0x290
174*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD3			0x294
175*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD4			0x298
176*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD5			0x29c
177*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_MODE_CONTD6			0x2a0
178*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_6			0x2a4
179*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_ADDITIONAL_MISC_7			0x2a8
180*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_VCO_WAIT_CYCLES			0x2ac
181*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_BIAS_WAIT_CYCLES			0x2b0
182*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_AUX_CLK_PSM_ENABLE			0x2b4
183*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO			0x2b8
184*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO_1		0x2bc
185*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO_2		0x2c0
186*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LDO_CAL_1				0x2c4
187*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LDO_CAL_2				0x2c8
188*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LDO_CAL_3				0x2cc
189*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LDO_CAL_4				0x2d0
190*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_LDO_CAL_5				0x2d4
191*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DCC_CAL_1				0x2d8
192*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DCC_CAL_2				0x2dc
193*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DCC_CAL_3				0x2e0
194*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DCC_CAL_4				0x2e4
195*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DCC_CAL_5				0x2e8
196*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DCC_CAL_6				0x2ec
197*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PSM_CAL_EN				0x2f0
198*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1			0x2f4
199*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_2			0x2f8
200*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL			0x2fc
201*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DCC_CAL_7				0x300
202*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DCC_CAL_8				0x304
203*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DCC_CAL_9				0x308
204*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_MODE_OPERATION_STATUS		0x30c
205*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_SYSCLK_DET_COMP_STATUS		0x310
206*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_CMN_STATUS				0x314
207*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_RESET_SM_STATUS			0x318
208*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_RESTRIM_CODE_STATUS		0x31c
209*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLLCAL_CODE1_STATUS		0x320
210*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLLCAL_CODE2_STATUS		0x324
211*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_INTEGLOOP_BINCODE_STATUS		0x328
212*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEBUG_BUS0				0x32c
213*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEBUG_BUS1				0x330
214*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEBUG_BUS2				0x334
215*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_DEBUG_BUS3				0x338
216*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_C_READY_STATUS			0x33c
217*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_READ_DUMMY_1			0x340
218*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_READ_DUMMY_2			0x344
219*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_READ_DUMMY_3			0x348
220*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_IVCO_CAL_CODE_STATUS		0x34c
221*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_LDO_CAL_STATUS_2		0x350
222*5b289913SWesley Cheng #define QSERDES_V8_USB43_COM_PLL_LDO_CAL_STATUS_3		0x354
223*5b289913SWesley Cheng 
224*5b289913SWesley Cheng #endif
225