1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy.h> 24 25 #include "phy-qcom-qmp.h" 26 27 /* QPHY_SW_RESET bit */ 28 #define SW_RESET BIT(0) 29 /* QPHY_POWER_DOWN_CONTROL */ 30 #define SW_PWRDN BIT(0) 31 #define REFCLK_DRV_DSBL BIT(1) 32 /* QPHY_START_CONTROL bits */ 33 #define SERDES_START BIT(0) 34 #define PCS_START BIT(1) 35 #define PLL_READY_GATE_EN BIT(3) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ 40 #define PCS_READY BIT(0) 41 42 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 43 /* DP PHY soft reset */ 44 #define SW_DPPHY_RESET BIT(0) 45 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 46 #define SW_DPPHY_RESET_MUX BIT(1) 47 /* USB3 PHY soft reset */ 48 #define SW_USB3PHY_RESET BIT(2) 49 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 50 #define SW_USB3PHY_RESET_MUX BIT(3) 51 52 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 53 #define USB3_MODE BIT(0) /* enables USB3 mode */ 54 #define DP_MODE BIT(1) /* enables DP mode */ 55 56 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 57 #define ARCVR_DTCT_EN BIT(0) 58 #define ALFPS_DTCT_EN BIT(1) 59 #define ARCVR_DTCT_EVENT_SEL BIT(4) 60 61 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 62 #define IRQ_CLEAR BIT(0) 63 64 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 65 #define RCVR_DETECT BIT(0) 66 67 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 68 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 69 70 #define PHY_INIT_COMPLETE_TIMEOUT 10000 71 #define POWER_DOWN_DELAY_US_MIN 10 72 #define POWER_DOWN_DELAY_US_MAX 11 73 74 #define MAX_PROP_NAME 32 75 76 /* Define the assumed distance between lanes for underspecified device trees. */ 77 #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 78 79 struct qmp_phy_init_tbl { 80 unsigned int offset; 81 unsigned int val; 82 /* 83 * register part of layout ? 84 * if yes, then offset gives index in the reg-layout 85 */ 86 bool in_layout; 87 /* 88 * mask of lanes for which this register is written 89 * for cases when second lane needs different values 90 */ 91 u8 lane_mask; 92 }; 93 94 #define QMP_PHY_INIT_CFG(o, v) \ 95 { \ 96 .offset = o, \ 97 .val = v, \ 98 .lane_mask = 0xff, \ 99 } 100 101 #define QMP_PHY_INIT_CFG_L(o, v) \ 102 { \ 103 .offset = o, \ 104 .val = v, \ 105 .in_layout = true, \ 106 .lane_mask = 0xff, \ 107 } 108 109 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 110 { \ 111 .offset = o, \ 112 .val = v, \ 113 .lane_mask = l, \ 114 } 115 116 /* set of registers with offsets different per-PHY */ 117 enum qphy_reg_layout { 118 /* Common block control registers */ 119 QPHY_COM_SW_RESET, 120 QPHY_COM_POWER_DOWN_CONTROL, 121 QPHY_COM_START_CONTROL, 122 QPHY_COM_PCS_READY_STATUS, 123 /* PCS registers */ 124 QPHY_PLL_LOCK_CHK_DLY_TIME, 125 QPHY_FLL_CNTRL1, 126 QPHY_FLL_CNTRL2, 127 QPHY_FLL_CNT_VAL_L, 128 QPHY_FLL_CNT_VAL_H_TOL, 129 QPHY_FLL_MAN_CODE, 130 QPHY_SW_RESET, 131 QPHY_START_CTRL, 132 QPHY_PCS_READY_STATUS, 133 QPHY_PCS_STATUS, 134 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 135 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 136 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 137 QPHY_PCS_POWER_DOWN_CONTROL, 138 /* PCS_MISC registers */ 139 QPHY_PCS_MISC_TYPEC_CTRL, 140 /* Keep last to ensure regs_layout arrays are properly initialized */ 141 QPHY_LAYOUT_SIZE 142 }; 143 144 static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 145 [QPHY_FLL_CNTRL1] = 0xc0, 146 [QPHY_FLL_CNTRL2] = 0xc4, 147 [QPHY_FLL_CNT_VAL_L] = 0xc8, 148 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc, 149 [QPHY_FLL_MAN_CODE] = 0xd0, 150 [QPHY_SW_RESET] = 0x00, 151 [QPHY_START_CTRL] = 0x08, 152 [QPHY_PCS_STATUS] = 0x17c, 153 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, 154 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, 155 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, 156 }; 157 158 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 159 [QPHY_SW_RESET] = 0x00, 160 [QPHY_START_CTRL] = 0x08, 161 [QPHY_PCS_STATUS] = 0x174, 162 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 163 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 164 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, 165 }; 166 167 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 168 [QPHY_SW_RESET] = 0x00, 169 [QPHY_START_CTRL] = 0x44, 170 [QPHY_PCS_STATUS] = 0x14, 171 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 172 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308, 173 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314, 174 }; 175 176 static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { 177 [QPHY_SW_RESET] = 0x00, 178 [QPHY_START_CTRL] = 0x44, 179 [QPHY_PCS_STATUS] = 0x14, 180 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 181 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608, 182 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614, 183 }; 184 185 static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { 186 [QPHY_SW_RESET] = 0x00, 187 [QPHY_START_CTRL] = 0x44, 188 [QPHY_PCS_STATUS] = 0x14, 189 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 190 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008, 191 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014, 192 }; 193 194 static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 195 [QPHY_SW_RESET] = 0x00, 196 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 197 [QPHY_START_CTRL] = 0x08, 198 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, 199 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, 200 [QPHY_PCS_STATUS] = 0x174, 201 [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, 202 }; 203 204 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { 205 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), 206 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 207 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 208 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 209 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 210 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 211 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 212 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 213 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 214 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 215 /* PLL and Loop filter settings */ 216 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 217 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 218 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 219 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 220 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 221 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 222 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 223 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 224 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 225 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 226 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 227 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 228 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 229 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 230 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 231 /* SSC settings */ 232 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 233 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 234 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 235 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 236 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 237 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 238 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 239 }; 240 241 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { 242 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), 243 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 244 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 245 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 246 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 247 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 248 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 249 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 250 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), 251 }; 252 253 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { 254 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 255 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 256 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 257 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 258 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 259 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 260 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 261 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 262 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 263 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 264 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 265 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 266 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 267 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 268 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 269 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 270 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 271 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 272 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 273 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 274 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 275 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 277 }; 278 279 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { 280 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 281 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 282 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 283 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 284 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 285 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 286 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 287 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 288 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), 289 /* PLL and Loop filter settings */ 290 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 291 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 292 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 293 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 294 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 295 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 296 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 297 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 298 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 299 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 300 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 301 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 302 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 303 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 304 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 305 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 306 /* SSC settings */ 307 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 308 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 309 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 310 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 311 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 312 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 313 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 314 }; 315 316 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { 317 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 318 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 319 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 320 }; 321 322 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { 323 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 324 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 325 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 326 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 327 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), 328 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 329 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 330 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 331 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), 332 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 333 }; 334 335 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { 336 /* FLL settings */ 337 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03), 338 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02), 339 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09), 340 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42), 341 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85), 342 343 /* Lock Det settings */ 344 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1), 345 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f), 346 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47), 347 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08), 348 }; 349 350 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 351 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 352 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 353 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 354 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 355 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 356 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 357 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 358 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 359 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 360 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 361 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 362 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 363 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 364 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 365 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 366 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 367 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 368 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 369 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 370 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 371 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 372 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 373 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 374 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 375 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 376 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 377 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 378 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 379 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 380 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 381 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 382 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 383 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 384 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 385 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 386 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 387 }; 388 389 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 390 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 391 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 392 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 393 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 394 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 395 }; 396 397 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 398 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 399 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 400 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 401 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 402 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 403 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 404 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 405 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 406 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 407 }; 408 409 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 410 /* FLL settings */ 411 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 412 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 413 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 414 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 415 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 416 417 /* Lock Det settings */ 418 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 419 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 420 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 421 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 422 423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 429 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 434 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 437 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 442 443 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 444 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 454 }; 455 456 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { 457 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 458 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 459 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 460 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 461 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 462 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 463 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 464 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 465 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 466 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 467 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 468 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 469 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 470 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 471 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 472 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 473 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 474 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 475 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 476 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 477 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 478 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 479 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 480 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 481 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 482 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 483 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 484 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 485 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 486 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 487 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 488 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 489 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 490 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 491 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 492 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 493 }; 494 495 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { 496 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 497 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 498 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 499 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 500 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 501 }; 502 503 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { 504 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), 505 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), 506 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 507 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 508 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 509 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 510 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 511 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 512 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 513 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 514 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 515 }; 516 517 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 518 /* FLL settings */ 519 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 520 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 521 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 522 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 523 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 524 525 /* Lock Det settings */ 526 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 527 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 528 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 529 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 530 531 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 532 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 533 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 534 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), 535 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), 536 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), 537 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), 538 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 539 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 540 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 541 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 542 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 543 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 544 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 545 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 546 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 547 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 548 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 549 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 550 551 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 552 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 553 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 554 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 555 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 556 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 557 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 558 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 559 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 560 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 561 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 562 563 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 565 }; 566 567 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { 568 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 569 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 570 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 571 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), 572 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 573 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 574 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 575 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 576 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 577 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 578 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 579 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 580 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 581 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 582 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 583 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 584 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 585 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 586 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 587 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 588 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 589 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 590 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 591 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 592 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 593 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 594 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 595 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 596 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 597 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), 598 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 599 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 600 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 601 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 602 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 603 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 604 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 605 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 606 }; 607 608 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { 609 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 610 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 611 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 612 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 613 }; 614 615 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { 616 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 617 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 618 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 619 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 620 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), 621 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 622 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), 623 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 624 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 625 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 626 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 627 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 628 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 629 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 630 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 631 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), 632 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 633 }; 634 635 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { 636 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 637 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 638 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 639 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 640 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 641 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 642 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 643 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 644 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 645 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 646 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 647 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 648 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 649 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 650 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 651 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 652 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 653 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15), 654 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 655 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 656 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 657 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 658 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), 659 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 660 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 661 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 662 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 663 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 664 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 665 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 666 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 667 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 668 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 669 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 670 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), 671 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 672 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 673 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 674 }; 675 676 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 677 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 678 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 679 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 680 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 681 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 682 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 683 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 684 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 685 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 686 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 687 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 688 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 689 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 690 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 691 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 692 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 693 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 694 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 695 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 696 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 697 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 698 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 699 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 700 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 701 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 702 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 703 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 704 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 705 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 706 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 707 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 708 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 709 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 710 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 711 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 712 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 713 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 714 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 715 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 716 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 717 }; 718 719 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 720 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 721 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 722 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 723 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 724 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 725 }; 726 727 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 728 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 729 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 730 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 731 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 732 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 733 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 734 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 735 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 736 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 737 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 738 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 739 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 740 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 741 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 742 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 743 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 744 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 745 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 746 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 747 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 748 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 749 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 750 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 751 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 752 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 753 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 754 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 755 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 756 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 757 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 758 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 759 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 760 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 761 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 762 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 763 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 764 }; 765 766 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 767 /* Lock Det settings */ 768 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 769 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 770 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 771 772 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 773 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 774 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 775 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 776 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 777 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 778 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 779 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 780 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 781 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 782 }; 783 784 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { 785 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 786 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 787 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 788 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 789 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 790 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 791 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 792 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 793 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 794 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 795 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 796 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 797 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 798 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 799 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 800 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 801 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 802 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 803 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 804 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 805 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 806 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 807 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 808 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 809 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 810 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 811 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 812 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 813 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 814 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 815 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 816 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 817 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 818 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 819 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 820 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 821 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 822 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 825 }; 826 827 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { 828 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 829 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), 830 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 831 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), 832 }; 833 834 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { 835 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 836 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 837 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), 838 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), 839 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), 840 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 841 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 842 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 843 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 844 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 845 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 846 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 847 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 848 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 849 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 850 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 851 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 852 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 853 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 854 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), 855 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 856 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 857 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 858 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 859 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 860 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 868 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), 869 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 871 }; 872 873 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { 874 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 875 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 876 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 877 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 878 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 879 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 880 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 881 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), 882 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 883 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), 884 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 885 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 886 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 887 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 888 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 889 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 890 }; 891 892 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 893 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 894 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 895 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 896 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 897 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 898 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 899 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 900 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 901 }; 902 903 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 904 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 905 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 906 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 907 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 908 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 909 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 910 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 911 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 912 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 913 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 914 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 915 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 916 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 917 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 924 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 925 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 926 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 927 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 942 }; 943 944 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 945 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 946 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 947 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 948 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 949 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 950 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 951 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 952 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 953 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 954 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 955 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 956 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 957 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 958 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 959 }; 960 961 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { 962 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 963 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 964 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), 965 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 966 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 967 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 968 }; 969 970 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { 971 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 972 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), 973 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 974 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 975 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 976 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 977 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 978 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 979 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 980 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 981 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 982 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 983 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 984 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 985 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 986 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 987 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 988 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 989 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 990 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), 991 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 992 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 993 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 994 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 995 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 996 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 997 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 998 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 999 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1007 }; 1008 1009 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { 1010 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1011 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1012 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1013 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1014 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1015 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1016 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 1017 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1018 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), 1019 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1020 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1021 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1022 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1023 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1024 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1025 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1026 }; 1027 1028 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { 1029 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), 1034 }; 1035 1036 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { 1037 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 1041 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 1043 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1068 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1069 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 1071 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1072 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1073 }; 1074 1075 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { 1076 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1078 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1079 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1080 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1081 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1082 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), 1083 }; 1084 1085 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { 1086 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1117 }; 1118 1119 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 1120 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1130 }; 1131 1132 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 1133 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1141 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 1157 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 1158 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 1171 }; 1172 1173 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 1174 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1175 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1176 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1177 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1178 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1179 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1180 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1181 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1182 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1183 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1184 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1185 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1186 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1187 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1188 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1189 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1190 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1191 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1192 }; 1193 1194 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { 1195 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1202 }; 1203 1204 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { 1205 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1211 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1212 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1213 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1218 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1219 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1220 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1221 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1225 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1226 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1227 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1228 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1229 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1230 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1231 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1235 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1236 }; 1237 1238 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { 1239 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1240 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1241 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1242 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1243 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1244 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1245 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1246 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1247 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07), 1248 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1249 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1250 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1251 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1252 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1253 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1254 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1255 }; 1256 1257 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { 1258 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 1259 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 1260 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 1261 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 1262 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), 1263 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), 1264 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 1265 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 1266 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 1267 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 1268 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 1269 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 1270 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 1271 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 1272 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 1273 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 1274 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 1275 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1276 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 1277 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 1278 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 1279 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 1280 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), 1281 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 1282 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 1283 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 1284 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 1285 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 1286 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 1287 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 1288 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 1289 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 1290 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 1291 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 1292 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 1293 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 1294 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), 1295 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), 1296 }; 1297 1298 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { 1299 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 1300 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 1301 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 1302 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 1303 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), 1304 }; 1305 1306 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { 1307 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 1308 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), 1309 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 1310 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 1311 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 1312 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 1313 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 1314 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 1315 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 1316 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 1317 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 1318 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1319 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 1320 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 1321 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 1322 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 1323 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 1324 }; 1325 1326 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { 1327 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 1328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 1329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 1330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 1331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 1332 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 1333 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 1334 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 1335 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 1336 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 1337 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 1338 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 1339 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 1340 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 1341 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1342 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 1343 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1344 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1345 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 1346 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 1347 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 1348 }; 1349 1350 struct qmp_phy; 1351 1352 /* struct qmp_phy_cfg - per-PHY initialization config */ 1353 struct qmp_phy_cfg { 1354 /* phy-type - PCIE/UFS/USB */ 1355 unsigned int type; 1356 /* number of lanes provided by phy */ 1357 int nlanes; 1358 1359 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1360 const struct qmp_phy_init_tbl *serdes_tbl; 1361 int serdes_tbl_num; 1362 const struct qmp_phy_init_tbl *tx_tbl; 1363 int tx_tbl_num; 1364 const struct qmp_phy_init_tbl *rx_tbl; 1365 int rx_tbl_num; 1366 const struct qmp_phy_init_tbl *pcs_tbl; 1367 int pcs_tbl_num; 1368 1369 /* clock ids to be requested */ 1370 const char * const *clk_list; 1371 int num_clks; 1372 /* resets to be requested */ 1373 const char * const *reset_list; 1374 int num_resets; 1375 /* regulators to be requested */ 1376 const char * const *vreg_list; 1377 int num_vregs; 1378 1379 /* array of registers with different offsets */ 1380 const unsigned int *regs; 1381 1382 unsigned int start_ctrl; 1383 unsigned int pwrdn_ctrl; 1384 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1385 unsigned int phy_status; 1386 1387 /* true, if PHY needs delay after POWER_DOWN */ 1388 bool has_pwrdn_delay; 1389 /* power_down delay in usec */ 1390 int pwrdn_delay_min; 1391 int pwrdn_delay_max; 1392 1393 /* true, if PHY has a separate DP_COM control block */ 1394 bool has_phy_dp_com_ctrl; 1395 /* true, if PHY has secondary tx/rx lanes to be configured */ 1396 bool is_dual_lane_phy; 1397 }; 1398 1399 /** 1400 * struct qmp_phy - per-lane phy descriptor 1401 * 1402 * @phy: generic phy 1403 * @cfg: phy specific configuration 1404 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1405 * @tx: iomapped memory space for lane's tx 1406 * @rx: iomapped memory space for lane's rx 1407 * @pcs: iomapped memory space for lane's pcs 1408 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1409 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1410 * @pcs_misc: iomapped memory space for lane's pcs_misc 1411 * @pipe_clk: pipe clock 1412 * @index: lane index 1413 * @qmp: QMP phy to which this lane belongs 1414 * @mode: current PHY mode 1415 */ 1416 struct qmp_phy { 1417 struct phy *phy; 1418 const struct qmp_phy_cfg *cfg; 1419 void __iomem *serdes; 1420 void __iomem *tx; 1421 void __iomem *rx; 1422 void __iomem *pcs; 1423 void __iomem *tx2; 1424 void __iomem *rx2; 1425 void __iomem *pcs_misc; 1426 struct clk *pipe_clk; 1427 unsigned int index; 1428 struct qcom_qmp *qmp; 1429 enum phy_mode mode; 1430 }; 1431 1432 /** 1433 * struct qcom_qmp - structure holding QMP phy block attributes 1434 * 1435 * @dev: device 1436 * @dp_com: iomapped memory space for phy's dp_com control block 1437 * 1438 * @clks: array of clocks required by phy 1439 * @resets: array of resets required by phy 1440 * @vregs: regulator supplies bulk data 1441 * 1442 * @phys: array of per-lane phy descriptors 1443 */ 1444 struct qcom_qmp { 1445 struct device *dev; 1446 void __iomem *dp_com; 1447 1448 struct clk_bulk_data *clks; 1449 struct reset_control_bulk_data *resets; 1450 struct regulator_bulk_data *vregs; 1451 1452 struct qmp_phy **phys; 1453 }; 1454 1455 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1456 { 1457 u32 reg; 1458 1459 reg = readl(base + offset); 1460 reg |= val; 1461 writel(reg, base + offset); 1462 1463 /* ensure that above write is through */ 1464 readl(base + offset); 1465 } 1466 1467 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1468 { 1469 u32 reg; 1470 1471 reg = readl(base + offset); 1472 reg &= ~val; 1473 writel(reg, base + offset); 1474 1475 /* ensure that above write is through */ 1476 readl(base + offset); 1477 } 1478 1479 /* list of clocks required by phy */ 1480 static const char * const msm8996_phy_clk_l[] = { 1481 "aux", "cfg_ahb", "ref", 1482 }; 1483 1484 static const char * const qmp_v3_phy_clk_l[] = { 1485 "aux", "cfg_ahb", "ref", "com_aux", 1486 }; 1487 1488 static const char * const qmp_v4_phy_clk_l[] = { 1489 "aux", "ref_clk_src", "ref", "com_aux", 1490 }; 1491 1492 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 1493 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 1494 "aux", "ref_clk_src", "com_aux" 1495 }; 1496 1497 /* usb3 phy on sdx55 doesn't have com_aux clock */ 1498 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { 1499 "aux", "cfg_ahb", "ref" 1500 }; 1501 1502 static const char * const qcm2290_usb3phy_clk_l[] = { 1503 "cfg_ahb", "ref", "com_aux", 1504 }; 1505 1506 /* list of resets */ 1507 static const char * const msm8996_usb3phy_reset_l[] = { 1508 "phy", "common", 1509 }; 1510 1511 static const char * const sc7180_usb3phy_reset_l[] = { 1512 "phy", 1513 }; 1514 1515 static const char * const qcm2290_usb3phy_reset_l[] = { 1516 "phy_phy", "phy", 1517 }; 1518 1519 /* list of regulators */ 1520 static const char * const qmp_phy_vreg_l[] = { 1521 "vdda-phy", "vdda-pll", 1522 }; 1523 1524 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { 1525 .type = PHY_TYPE_USB3, 1526 .nlanes = 1, 1527 1528 .serdes_tbl = ipq8074_usb3_serdes_tbl, 1529 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), 1530 .tx_tbl = msm8996_usb3_tx_tbl, 1531 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1532 .rx_tbl = ipq8074_usb3_rx_tbl, 1533 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), 1534 .pcs_tbl = ipq8074_usb3_pcs_tbl, 1535 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), 1536 .clk_list = msm8996_phy_clk_l, 1537 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1538 .reset_list = msm8996_usb3phy_reset_l, 1539 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1540 .vreg_list = qmp_phy_vreg_l, 1541 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1542 .regs = usb3phy_regs_layout, 1543 1544 .start_ctrl = SERDES_START | PCS_START, 1545 .pwrdn_ctrl = SW_PWRDN, 1546 .phy_status = PHYSTATUS, 1547 }; 1548 1549 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 1550 .type = PHY_TYPE_USB3, 1551 .nlanes = 1, 1552 1553 .serdes_tbl = msm8996_usb3_serdes_tbl, 1554 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), 1555 .tx_tbl = msm8996_usb3_tx_tbl, 1556 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1557 .rx_tbl = msm8996_usb3_rx_tbl, 1558 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), 1559 .pcs_tbl = msm8996_usb3_pcs_tbl, 1560 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), 1561 .clk_list = msm8996_phy_clk_l, 1562 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1563 .reset_list = msm8996_usb3phy_reset_l, 1564 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1565 .vreg_list = qmp_phy_vreg_l, 1566 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1567 .regs = usb3phy_regs_layout, 1568 1569 .start_ctrl = SERDES_START | PCS_START, 1570 .pwrdn_ctrl = SW_PWRDN, 1571 .phy_status = PHYSTATUS, 1572 }; 1573 1574 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { 1575 .type = PHY_TYPE_USB3, 1576 .nlanes = 1, 1577 1578 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1579 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1580 .tx_tbl = qmp_v3_usb3_tx_tbl, 1581 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1582 .rx_tbl = qmp_v3_usb3_rx_tbl, 1583 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1584 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1585 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1586 .clk_list = qmp_v3_phy_clk_l, 1587 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1588 .reset_list = msm8996_usb3phy_reset_l, 1589 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1590 .vreg_list = qmp_phy_vreg_l, 1591 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1592 .regs = qmp_v3_usb3phy_regs_layout, 1593 1594 .start_ctrl = SERDES_START | PCS_START, 1595 .pwrdn_ctrl = SW_PWRDN, 1596 .phy_status = PHYSTATUS, 1597 1598 .has_pwrdn_delay = true, 1599 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1600 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1601 1602 .has_phy_dp_com_ctrl = true, 1603 .is_dual_lane_phy = true, 1604 }; 1605 1606 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { 1607 .type = PHY_TYPE_USB3, 1608 .nlanes = 1, 1609 1610 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1611 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1612 .tx_tbl = qmp_v3_usb3_tx_tbl, 1613 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1614 .rx_tbl = qmp_v3_usb3_rx_tbl, 1615 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1616 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1617 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1618 .clk_list = qmp_v3_phy_clk_l, 1619 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1620 .reset_list = sc7180_usb3phy_reset_l, 1621 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1622 .vreg_list = qmp_phy_vreg_l, 1623 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1624 .regs = qmp_v3_usb3phy_regs_layout, 1625 1626 .start_ctrl = SERDES_START | PCS_START, 1627 .pwrdn_ctrl = SW_PWRDN, 1628 .phy_status = PHYSTATUS, 1629 1630 .has_pwrdn_delay = true, 1631 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1632 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1633 1634 .has_phy_dp_com_ctrl = true, 1635 .is_dual_lane_phy = true, 1636 }; 1637 1638 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 1639 .type = PHY_TYPE_USB3, 1640 .nlanes = 1, 1641 1642 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, 1643 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), 1644 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, 1645 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), 1646 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, 1647 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), 1648 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, 1649 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), 1650 .clk_list = qmp_v3_phy_clk_l, 1651 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1652 .reset_list = msm8996_usb3phy_reset_l, 1653 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1654 .vreg_list = qmp_phy_vreg_l, 1655 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1656 .regs = qmp_v3_usb3phy_regs_layout, 1657 1658 .start_ctrl = SERDES_START | PCS_START, 1659 .pwrdn_ctrl = SW_PWRDN, 1660 .phy_status = PHYSTATUS, 1661 1662 .has_pwrdn_delay = true, 1663 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1664 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1665 }; 1666 1667 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { 1668 .type = PHY_TYPE_USB3, 1669 .nlanes = 1, 1670 1671 .serdes_tbl = msm8998_usb3_serdes_tbl, 1672 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), 1673 .tx_tbl = msm8998_usb3_tx_tbl, 1674 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), 1675 .rx_tbl = msm8998_usb3_rx_tbl, 1676 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), 1677 .pcs_tbl = msm8998_usb3_pcs_tbl, 1678 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), 1679 .clk_list = msm8996_phy_clk_l, 1680 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1681 .reset_list = msm8996_usb3phy_reset_l, 1682 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1683 .vreg_list = qmp_phy_vreg_l, 1684 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1685 .regs = qmp_v3_usb3phy_regs_layout, 1686 1687 .start_ctrl = SERDES_START | PCS_START, 1688 .pwrdn_ctrl = SW_PWRDN, 1689 .phy_status = PHYSTATUS, 1690 1691 .is_dual_lane_phy = true, 1692 }; 1693 1694 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { 1695 .type = PHY_TYPE_USB3, 1696 .nlanes = 1, 1697 1698 .serdes_tbl = sm8150_usb3_serdes_tbl, 1699 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1700 .tx_tbl = sm8150_usb3_tx_tbl, 1701 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1702 .rx_tbl = sm8150_usb3_rx_tbl, 1703 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1704 .pcs_tbl = sm8150_usb3_pcs_tbl, 1705 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1706 .clk_list = qmp_v4_phy_clk_l, 1707 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1708 .reset_list = msm8996_usb3phy_reset_l, 1709 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1710 .vreg_list = qmp_phy_vreg_l, 1711 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1712 .regs = qmp_v4_usb3phy_regs_layout, 1713 1714 .start_ctrl = SERDES_START | PCS_START, 1715 .pwrdn_ctrl = SW_PWRDN, 1716 .phy_status = PHYSTATUS, 1717 1718 1719 .has_pwrdn_delay = true, 1720 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1721 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1722 1723 .has_phy_dp_com_ctrl = true, 1724 .is_dual_lane_phy = true, 1725 }; 1726 1727 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { 1728 .type = PHY_TYPE_USB3, 1729 .nlanes = 1, 1730 1731 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1732 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1733 .tx_tbl = sm8150_usb3_uniphy_tx_tbl, 1734 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), 1735 .rx_tbl = sm8150_usb3_uniphy_rx_tbl, 1736 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), 1737 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, 1738 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), 1739 .clk_list = qmp_v4_phy_clk_l, 1740 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1741 .reset_list = msm8996_usb3phy_reset_l, 1742 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1743 .vreg_list = qmp_phy_vreg_l, 1744 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1745 .regs = qmp_v4_usb3_uniphy_regs_layout, 1746 1747 .start_ctrl = SERDES_START | PCS_START, 1748 .pwrdn_ctrl = SW_PWRDN, 1749 .phy_status = PHYSTATUS, 1750 1751 .has_pwrdn_delay = true, 1752 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1753 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1754 }; 1755 1756 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { 1757 .type = PHY_TYPE_USB3, 1758 .nlanes = 1, 1759 1760 .serdes_tbl = sm8150_usb3_serdes_tbl, 1761 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1762 .tx_tbl = sm8250_usb3_tx_tbl, 1763 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1764 .rx_tbl = sm8250_usb3_rx_tbl, 1765 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1766 .pcs_tbl = sm8250_usb3_pcs_tbl, 1767 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1768 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1769 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1770 .reset_list = msm8996_usb3phy_reset_l, 1771 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1772 .vreg_list = qmp_phy_vreg_l, 1773 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1774 .regs = qmp_v4_usb3phy_regs_layout, 1775 1776 .start_ctrl = SERDES_START | PCS_START, 1777 .pwrdn_ctrl = SW_PWRDN, 1778 .phy_status = PHYSTATUS, 1779 1780 .has_pwrdn_delay = true, 1781 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1782 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1783 1784 .has_phy_dp_com_ctrl = true, 1785 .is_dual_lane_phy = true, 1786 }; 1787 1788 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { 1789 .type = PHY_TYPE_USB3, 1790 .nlanes = 1, 1791 1792 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1793 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1794 .tx_tbl = sm8250_usb3_uniphy_tx_tbl, 1795 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), 1796 .rx_tbl = sm8250_usb3_uniphy_rx_tbl, 1797 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), 1798 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1799 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1800 .clk_list = qmp_v4_phy_clk_l, 1801 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1802 .reset_list = msm8996_usb3phy_reset_l, 1803 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1804 .vreg_list = qmp_phy_vreg_l, 1805 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1806 .regs = qmp_v4_usb3_uniphy_regs_layout, 1807 1808 .start_ctrl = SERDES_START | PCS_START, 1809 .pwrdn_ctrl = SW_PWRDN, 1810 .phy_status = PHYSTATUS, 1811 1812 .has_pwrdn_delay = true, 1813 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1814 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1815 }; 1816 1817 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { 1818 .type = PHY_TYPE_USB3, 1819 .nlanes = 1, 1820 1821 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1822 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1823 .tx_tbl = sdx55_usb3_uniphy_tx_tbl, 1824 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), 1825 .rx_tbl = sdx55_usb3_uniphy_rx_tbl, 1826 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), 1827 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1828 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1829 .clk_list = qmp_v4_sdx55_usbphy_clk_l, 1830 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 1831 .reset_list = msm8996_usb3phy_reset_l, 1832 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1833 .vreg_list = qmp_phy_vreg_l, 1834 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1835 .regs = qmp_v4_usb3_uniphy_regs_layout, 1836 1837 .start_ctrl = SERDES_START | PCS_START, 1838 .pwrdn_ctrl = SW_PWRDN, 1839 .phy_status = PHYSTATUS, 1840 1841 .has_pwrdn_delay = true, 1842 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1843 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1844 }; 1845 1846 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { 1847 .type = PHY_TYPE_USB3, 1848 .nlanes = 1, 1849 1850 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1851 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1852 .tx_tbl = sdx65_usb3_uniphy_tx_tbl, 1853 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), 1854 .rx_tbl = sdx65_usb3_uniphy_rx_tbl, 1855 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), 1856 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1857 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1858 .clk_list = qmp_v4_sdx55_usbphy_clk_l, 1859 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 1860 .reset_list = msm8996_usb3phy_reset_l, 1861 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1862 .vreg_list = qmp_phy_vreg_l, 1863 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1864 .regs = sm8350_usb3_uniphy_regs_layout, 1865 1866 .start_ctrl = SERDES_START | PCS_START, 1867 .pwrdn_ctrl = SW_PWRDN, 1868 .phy_status = PHYSTATUS, 1869 1870 .has_pwrdn_delay = true, 1871 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1872 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1873 }; 1874 1875 static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { 1876 .type = PHY_TYPE_USB3, 1877 .nlanes = 1, 1878 1879 .serdes_tbl = sm8150_usb3_serdes_tbl, 1880 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1881 .tx_tbl = sm8350_usb3_tx_tbl, 1882 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 1883 .rx_tbl = sm8350_usb3_rx_tbl, 1884 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 1885 .pcs_tbl = sm8350_usb3_pcs_tbl, 1886 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 1887 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1888 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1889 .reset_list = msm8996_usb3phy_reset_l, 1890 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1891 .vreg_list = qmp_phy_vreg_l, 1892 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1893 .regs = qmp_v4_usb3phy_regs_layout, 1894 1895 .start_ctrl = SERDES_START | PCS_START, 1896 .pwrdn_ctrl = SW_PWRDN, 1897 .phy_status = PHYSTATUS, 1898 1899 .has_pwrdn_delay = true, 1900 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1901 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1902 1903 .has_phy_dp_com_ctrl = true, 1904 .is_dual_lane_phy = true, 1905 }; 1906 1907 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { 1908 .type = PHY_TYPE_USB3, 1909 .nlanes = 1, 1910 1911 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1912 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1913 .tx_tbl = sm8350_usb3_uniphy_tx_tbl, 1914 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), 1915 .rx_tbl = sm8350_usb3_uniphy_rx_tbl, 1916 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), 1917 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1918 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1919 .clk_list = qmp_v4_phy_clk_l, 1920 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1921 .reset_list = msm8996_usb3phy_reset_l, 1922 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1923 .vreg_list = qmp_phy_vreg_l, 1924 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1925 .regs = sm8350_usb3_uniphy_regs_layout, 1926 1927 .start_ctrl = SERDES_START | PCS_START, 1928 .pwrdn_ctrl = SW_PWRDN, 1929 .phy_status = PHYSTATUS, 1930 1931 .has_pwrdn_delay = true, 1932 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1933 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1934 }; 1935 1936 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { 1937 .type = PHY_TYPE_USB3, 1938 .nlanes = 1, 1939 1940 .serdes_tbl = qcm2290_usb3_serdes_tbl, 1941 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 1942 .tx_tbl = qcm2290_usb3_tx_tbl, 1943 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 1944 .rx_tbl = qcm2290_usb3_rx_tbl, 1945 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 1946 .pcs_tbl = qcm2290_usb3_pcs_tbl, 1947 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 1948 .clk_list = qcm2290_usb3phy_clk_l, 1949 .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), 1950 .reset_list = qcm2290_usb3phy_reset_l, 1951 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1952 .vreg_list = qmp_phy_vreg_l, 1953 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1954 .regs = qcm2290_usb3phy_regs_layout, 1955 1956 .start_ctrl = SERDES_START | PCS_START, 1957 .pwrdn_ctrl = SW_PWRDN, 1958 .phy_status = PHYSTATUS, 1959 1960 .is_dual_lane_phy = true, 1961 }; 1962 1963 static void qcom_qmp_phy_usb_configure_lane(void __iomem *base, 1964 const unsigned int *regs, 1965 const struct qmp_phy_init_tbl tbl[], 1966 int num, 1967 u8 lane_mask) 1968 { 1969 int i; 1970 const struct qmp_phy_init_tbl *t = tbl; 1971 1972 if (!t) 1973 return; 1974 1975 for (i = 0; i < num; i++, t++) { 1976 if (!(t->lane_mask & lane_mask)) 1977 continue; 1978 1979 if (t->in_layout) 1980 writel(t->val, base + regs[t->offset]); 1981 else 1982 writel(t->val, base + t->offset); 1983 } 1984 } 1985 1986 static void qcom_qmp_phy_usb_configure(void __iomem *base, 1987 const unsigned int *regs, 1988 const struct qmp_phy_init_tbl tbl[], 1989 int num) 1990 { 1991 qcom_qmp_phy_usb_configure_lane(base, regs, tbl, num, 0xff); 1992 } 1993 1994 static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy) 1995 { 1996 const struct qmp_phy_cfg *cfg = qphy->cfg; 1997 void __iomem *serdes = qphy->serdes; 1998 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1999 int serdes_tbl_num = cfg->serdes_tbl_num; 2000 2001 qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 2002 2003 return 0; 2004 } 2005 2006 static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy) 2007 { 2008 struct qcom_qmp *qmp = qphy->qmp; 2009 const struct qmp_phy_cfg *cfg = qphy->cfg; 2010 void __iomem *pcs = qphy->pcs; 2011 void __iomem *dp_com = qmp->dp_com; 2012 int ret; 2013 2014 /* turn on regulator supplies */ 2015 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2016 if (ret) { 2017 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2018 return ret; 2019 } 2020 2021 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2022 if (ret) { 2023 dev_err(qmp->dev, "reset assert failed\n"); 2024 goto err_disable_regulators; 2025 } 2026 2027 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2028 if (ret) { 2029 dev_err(qmp->dev, "reset deassert failed\n"); 2030 goto err_disable_regulators; 2031 } 2032 2033 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2034 if (ret) 2035 goto err_assert_reset; 2036 2037 if (cfg->has_phy_dp_com_ctrl) { 2038 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 2039 SW_PWRDN); 2040 /* override hardware control for reset of qmp phy */ 2041 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2042 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2043 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2044 2045 /* Default type-c orientation, i.e CC1 */ 2046 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 2047 2048 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 2049 USB3_MODE | DP_MODE); 2050 2051 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2052 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2053 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2054 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2055 2056 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2057 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2058 } 2059 2060 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 2061 qphy_setbits(pcs, 2062 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2063 cfg->pwrdn_ctrl); 2064 else 2065 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 2066 cfg->pwrdn_ctrl); 2067 2068 return 0; 2069 2070 err_assert_reset: 2071 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2072 err_disable_regulators: 2073 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2074 2075 return ret; 2076 } 2077 2078 static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy) 2079 { 2080 struct qcom_qmp *qmp = qphy->qmp; 2081 const struct qmp_phy_cfg *cfg = qphy->cfg; 2082 2083 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2084 2085 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2086 2087 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2088 2089 return 0; 2090 } 2091 2092 static int qcom_qmp_phy_usb_init(struct phy *phy) 2093 { 2094 struct qmp_phy *qphy = phy_get_drvdata(phy); 2095 struct qcom_qmp *qmp = qphy->qmp; 2096 int ret; 2097 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 2098 2099 ret = qcom_qmp_phy_usb_com_init(qphy); 2100 if (ret) 2101 return ret; 2102 2103 return 0; 2104 } 2105 2106 static int qcom_qmp_phy_usb_power_on(struct phy *phy) 2107 { 2108 struct qmp_phy *qphy = phy_get_drvdata(phy); 2109 struct qcom_qmp *qmp = qphy->qmp; 2110 const struct qmp_phy_cfg *cfg = qphy->cfg; 2111 void __iomem *tx = qphy->tx; 2112 void __iomem *rx = qphy->rx; 2113 void __iomem *pcs = qphy->pcs; 2114 void __iomem *status; 2115 unsigned int mask, val, ready; 2116 int ret; 2117 2118 qcom_qmp_phy_usb_serdes_init(qphy); 2119 2120 ret = clk_prepare_enable(qphy->pipe_clk); 2121 if (ret) { 2122 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2123 return ret; 2124 } 2125 2126 /* Tx, Rx, and PCS configurations */ 2127 qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, 2128 cfg->tx_tbl, cfg->tx_tbl_num, 1); 2129 2130 /* Configuration for other LANE for USB-DP combo PHY */ 2131 if (cfg->is_dual_lane_phy) { 2132 qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs, 2133 cfg->tx_tbl, cfg->tx_tbl_num, 2); 2134 } 2135 2136 qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, 2137 cfg->rx_tbl, cfg->rx_tbl_num, 1); 2138 2139 if (cfg->is_dual_lane_phy) { 2140 qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs, 2141 cfg->rx_tbl, cfg->rx_tbl_num, 2); 2142 } 2143 2144 /* Configure link rate, swing, etc. */ 2145 qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2146 2147 if (cfg->has_pwrdn_delay) 2148 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2149 2150 /* Pull PHY out of reset state */ 2151 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2152 2153 /* start SerDes and Phy-Coding-Sublayer */ 2154 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2155 2156 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2157 mask = cfg->phy_status; 2158 ready = 0; 2159 2160 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2161 PHY_INIT_COMPLETE_TIMEOUT); 2162 if (ret) { 2163 dev_err(qmp->dev, "phy initialization timed-out\n"); 2164 goto err_disable_pipe_clk; 2165 } 2166 2167 return 0; 2168 2169 err_disable_pipe_clk: 2170 clk_disable_unprepare(qphy->pipe_clk); 2171 2172 return ret; 2173 } 2174 2175 static int qcom_qmp_phy_usb_power_off(struct phy *phy) 2176 { 2177 struct qmp_phy *qphy = phy_get_drvdata(phy); 2178 const struct qmp_phy_cfg *cfg = qphy->cfg; 2179 2180 clk_disable_unprepare(qphy->pipe_clk); 2181 2182 /* PHY reset */ 2183 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2184 2185 /* stop SerDes and Phy-Coding-Sublayer */ 2186 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2187 2188 /* Put PHY into POWER DOWN state: active low */ 2189 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2190 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2191 cfg->pwrdn_ctrl); 2192 } else { 2193 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, 2194 cfg->pwrdn_ctrl); 2195 } 2196 2197 return 0; 2198 } 2199 2200 static int qcom_qmp_phy_usb_exit(struct phy *phy) 2201 { 2202 struct qmp_phy *qphy = phy_get_drvdata(phy); 2203 2204 qcom_qmp_phy_usb_com_exit(qphy); 2205 2206 return 0; 2207 } 2208 2209 static int qcom_qmp_phy_usb_enable(struct phy *phy) 2210 { 2211 int ret; 2212 2213 ret = qcom_qmp_phy_usb_init(phy); 2214 if (ret) 2215 return ret; 2216 2217 ret = qcom_qmp_phy_usb_power_on(phy); 2218 if (ret) 2219 qcom_qmp_phy_usb_exit(phy); 2220 2221 return ret; 2222 } 2223 2224 static int qcom_qmp_phy_usb_disable(struct phy *phy) 2225 { 2226 int ret; 2227 2228 ret = qcom_qmp_phy_usb_power_off(phy); 2229 if (ret) 2230 return ret; 2231 return qcom_qmp_phy_usb_exit(phy); 2232 } 2233 2234 static int qcom_qmp_phy_usb_set_mode(struct phy *phy, 2235 enum phy_mode mode, int submode) 2236 { 2237 struct qmp_phy *qphy = phy_get_drvdata(phy); 2238 2239 qphy->mode = mode; 2240 2241 return 0; 2242 } 2243 2244 static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy) 2245 { 2246 const struct qmp_phy_cfg *cfg = qphy->cfg; 2247 void __iomem *pcs = qphy->pcs; 2248 void __iomem *pcs_misc = qphy->pcs_misc; 2249 u32 intr_mask; 2250 2251 if (qphy->mode == PHY_MODE_USB_HOST_SS || 2252 qphy->mode == PHY_MODE_USB_DEVICE_SS) 2253 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2254 else 2255 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2256 2257 /* Clear any pending interrupts status */ 2258 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2259 /* Writing 1 followed by 0 clears the interrupt */ 2260 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2261 2262 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2263 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2264 2265 /* Enable required PHY autonomous mode interrupts */ 2266 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2267 2268 /* Enable i/o clamp_n for autonomous mode */ 2269 if (pcs_misc) 2270 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2271 } 2272 2273 static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy) 2274 { 2275 const struct qmp_phy_cfg *cfg = qphy->cfg; 2276 void __iomem *pcs = qphy->pcs; 2277 void __iomem *pcs_misc = qphy->pcs_misc; 2278 2279 /* Disable i/o clamp_n on resume for normal mode */ 2280 if (pcs_misc) 2281 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2282 2283 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2284 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2285 2286 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2287 /* Writing 1 followed by 0 clears the interrupt */ 2288 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2289 } 2290 2291 static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev) 2292 { 2293 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2294 struct qmp_phy *qphy = qmp->phys[0]; 2295 const struct qmp_phy_cfg *cfg = qphy->cfg; 2296 2297 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); 2298 2299 /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 2300 if (cfg->type != PHY_TYPE_USB3) 2301 return 0; 2302 2303 if (!qphy->phy->init_count) { 2304 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2305 return 0; 2306 } 2307 2308 qcom_qmp_phy_usb_enable_autonomous_mode(qphy); 2309 2310 clk_disable_unprepare(qphy->pipe_clk); 2311 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2312 2313 return 0; 2314 } 2315 2316 static int __maybe_unused qcom_qmp_phy_usb_runtime_resume(struct device *dev) 2317 { 2318 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2319 struct qmp_phy *qphy = qmp->phys[0]; 2320 const struct qmp_phy_cfg *cfg = qphy->cfg; 2321 int ret = 0; 2322 2323 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); 2324 2325 /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 2326 if (cfg->type != PHY_TYPE_USB3) 2327 return 0; 2328 2329 if (!qphy->phy->init_count) { 2330 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2331 return 0; 2332 } 2333 2334 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2335 if (ret) 2336 return ret; 2337 2338 ret = clk_prepare_enable(qphy->pipe_clk); 2339 if (ret) { 2340 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2341 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2342 return ret; 2343 } 2344 2345 qcom_qmp_phy_usb_disable_autonomous_mode(qphy); 2346 2347 return 0; 2348 } 2349 2350 static int qcom_qmp_phy_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2351 { 2352 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2353 int num = cfg->num_vregs; 2354 int i; 2355 2356 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2357 if (!qmp->vregs) 2358 return -ENOMEM; 2359 2360 for (i = 0; i < num; i++) 2361 qmp->vregs[i].supply = cfg->vreg_list[i]; 2362 2363 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2364 } 2365 2366 static int qcom_qmp_phy_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2367 { 2368 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2369 int i; 2370 int ret; 2371 2372 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2373 sizeof(*qmp->resets), GFP_KERNEL); 2374 if (!qmp->resets) 2375 return -ENOMEM; 2376 2377 for (i = 0; i < cfg->num_resets; i++) 2378 qmp->resets[i].id = cfg->reset_list[i]; 2379 2380 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2381 if (ret) 2382 return dev_err_probe(dev, ret, "failed to get resets\n"); 2383 2384 return 0; 2385 } 2386 2387 static int qcom_qmp_phy_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2388 { 2389 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2390 int num = cfg->num_clks; 2391 int i; 2392 2393 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2394 if (!qmp->clks) 2395 return -ENOMEM; 2396 2397 for (i = 0; i < num; i++) 2398 qmp->clks[i].id = cfg->clk_list[i]; 2399 2400 return devm_clk_bulk_get(dev, num, qmp->clks); 2401 } 2402 2403 static void phy_clk_release_provider(void *res) 2404 { 2405 of_clk_del_provider(res); 2406 } 2407 2408 /* 2409 * Register a fixed rate pipe clock. 2410 * 2411 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2412 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2413 * by the PHY driver for its operations. 2414 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2415 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2416 * Below picture shows this relationship. 2417 * 2418 * +---------------+ 2419 * | PHY block |<<---------------------------------------+ 2420 * | | | 2421 * | +-------+ | +-----+ | 2422 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2423 * clk | +-------+ | +-----+ 2424 * +---------------+ 2425 */ 2426 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2427 { 2428 struct clk_fixed_rate *fixed; 2429 struct clk_init_data init = { }; 2430 int ret; 2431 2432 ret = of_property_read_string(np, "clock-output-names", &init.name); 2433 if (ret) { 2434 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2435 return ret; 2436 } 2437 2438 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2439 if (!fixed) 2440 return -ENOMEM; 2441 2442 init.ops = &clk_fixed_rate_ops; 2443 2444 /* controllers using QMP phys use 125MHz pipe clock interface */ 2445 fixed->fixed_rate = 125000000; 2446 fixed->hw.init = &init; 2447 2448 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2449 if (ret) 2450 return ret; 2451 2452 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2453 if (ret) 2454 return ret; 2455 2456 /* 2457 * Roll a devm action because the clock provider is the child node, but 2458 * the child node is not actually a device. 2459 */ 2460 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2461 } 2462 2463 static const struct phy_ops qcom_qmp_phy_usb_ops = { 2464 .init = qcom_qmp_phy_usb_enable, 2465 .exit = qcom_qmp_phy_usb_disable, 2466 .set_mode = qcom_qmp_phy_usb_set_mode, 2467 .owner = THIS_MODULE, 2468 }; 2469 2470 static 2471 int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, 2472 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2473 { 2474 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2475 struct phy *generic_phy; 2476 struct qmp_phy *qphy; 2477 char prop_name[MAX_PROP_NAME]; 2478 int ret; 2479 2480 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2481 if (!qphy) 2482 return -ENOMEM; 2483 2484 qphy->cfg = cfg; 2485 qphy->serdes = serdes; 2486 /* 2487 * Get memory resources for each phy lane: 2488 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2489 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2490 * For single lane PHYs: pcs_misc (optional) -> 3. 2491 */ 2492 qphy->tx = of_iomap(np, 0); 2493 if (!qphy->tx) 2494 return -ENOMEM; 2495 2496 qphy->rx = of_iomap(np, 1); 2497 if (!qphy->rx) 2498 return -ENOMEM; 2499 2500 qphy->pcs = of_iomap(np, 2); 2501 if (!qphy->pcs) 2502 return -ENOMEM; 2503 2504 /* 2505 * If this is a dual-lane PHY, then there should be registers for the 2506 * second lane. Some old device trees did not specify this, so fall 2507 * back to old legacy behavior of assuming they can be reached at an 2508 * offset from the first lane. 2509 */ 2510 if (cfg->is_dual_lane_phy) { 2511 qphy->tx2 = of_iomap(np, 3); 2512 qphy->rx2 = of_iomap(np, 4); 2513 if (!qphy->tx2 || !qphy->rx2) { 2514 dev_warn(dev, 2515 "Underspecified device tree, falling back to legacy register regions\n"); 2516 2517 /* In the old version, pcs_misc is at index 3. */ 2518 qphy->pcs_misc = qphy->tx2; 2519 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; 2520 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; 2521 2522 } else { 2523 qphy->pcs_misc = of_iomap(np, 5); 2524 } 2525 2526 } else { 2527 qphy->pcs_misc = of_iomap(np, 3); 2528 } 2529 2530 if (!qphy->pcs_misc) 2531 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2532 2533 /* 2534 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 2535 * based phys, so they essentially have pipe clock. So, 2536 * we return error in case phy is USB3 or PIPE type. 2537 * Otherwise, we initialize pipe clock to NULL for 2538 * all phys that don't need this. 2539 */ 2540 snprintf(prop_name, sizeof(prop_name), "pipe%d", id); 2541 qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); 2542 if (IS_ERR(qphy->pipe_clk)) { 2543 ret = PTR_ERR(qphy->pipe_clk); 2544 if (ret != -EPROBE_DEFER) 2545 dev_err(dev, 2546 "failed to get lane%d pipe_clk, %d\n", 2547 id, ret); 2548 return ret; 2549 } 2550 2551 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops); 2552 if (IS_ERR(generic_phy)) { 2553 ret = PTR_ERR(generic_phy); 2554 dev_err(dev, "failed to create qphy %d\n", ret); 2555 return ret; 2556 } 2557 2558 qphy->phy = generic_phy; 2559 qphy->index = id; 2560 qphy->qmp = qmp; 2561 qmp->phys[id] = qphy; 2562 phy_set_drvdata(generic_phy, qphy); 2563 2564 return 0; 2565 } 2566 2567 static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = { 2568 { 2569 .compatible = "qcom,ipq8074-qmp-usb3-phy", 2570 .data = &ipq8074_usb3phy_cfg, 2571 }, { 2572 .compatible = "qcom,msm8996-qmp-usb3-phy", 2573 .data = &msm8996_usb3phy_cfg, 2574 }, { 2575 .compatible = "qcom,ipq6018-qmp-usb3-phy", 2576 .data = &ipq8074_usb3phy_cfg, 2577 }, { 2578 .compatible = "qcom,sc7180-qmp-usb3-phy", 2579 .data = &sc7180_usb3phy_cfg, 2580 }, { 2581 .compatible = "qcom,sc8180x-qmp-usb3-phy", 2582 .data = &sm8150_usb3phy_cfg, 2583 }, { 2584 .compatible = "qcom,sdm845-qmp-usb3-phy", 2585 .data = &qmp_v3_usb3phy_cfg, 2586 }, { 2587 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 2588 .data = &qmp_v3_usb3_uniphy_cfg, 2589 }, { 2590 .compatible = "qcom,msm8998-qmp-usb3-phy", 2591 .data = &msm8998_usb3phy_cfg, 2592 }, { 2593 .compatible = "qcom,sm8150-qmp-usb3-phy", 2594 .data = &sm8150_usb3phy_cfg, 2595 }, { 2596 .compatible = "qcom,sm8150-qmp-usb3-uni-phy", 2597 .data = &sm8150_usb3_uniphy_cfg, 2598 }, { 2599 .compatible = "qcom,sm8250-qmp-usb3-phy", 2600 .data = &sm8250_usb3phy_cfg, 2601 }, { 2602 .compatible = "qcom,sm8250-qmp-usb3-uni-phy", 2603 .data = &sm8250_usb3_uniphy_cfg, 2604 }, { 2605 .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 2606 .data = &sdx55_usb3_uniphy_cfg, 2607 }, { 2608 .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 2609 .data = &sdx65_usb3_uniphy_cfg, 2610 }, { 2611 .compatible = "qcom,sm8350-qmp-usb3-phy", 2612 .data = &sm8350_usb3phy_cfg, 2613 }, { 2614 .compatible = "qcom,sm8350-qmp-usb3-uni-phy", 2615 .data = &sm8350_usb3_uniphy_cfg, 2616 }, { 2617 .compatible = "qcom,sm8450-qmp-usb3-phy", 2618 .data = &sm8350_usb3phy_cfg, 2619 }, { 2620 .compatible = "qcom,qcm2290-qmp-usb3-phy", 2621 .data = &qcm2290_usb3phy_cfg, 2622 }, 2623 { }, 2624 }; 2625 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_usb_of_match_table); 2626 2627 static const struct dev_pm_ops qcom_qmp_phy_usb_pm_ops = { 2628 SET_RUNTIME_PM_OPS(qcom_qmp_phy_usb_runtime_suspend, 2629 qcom_qmp_phy_usb_runtime_resume, NULL) 2630 }; 2631 2632 static int qcom_qmp_phy_usb_probe(struct platform_device *pdev) 2633 { 2634 struct qcom_qmp *qmp; 2635 struct device *dev = &pdev->dev; 2636 struct device_node *child; 2637 struct phy_provider *phy_provider; 2638 void __iomem *serdes; 2639 const struct qmp_phy_cfg *cfg = NULL; 2640 int num, id; 2641 int ret; 2642 2643 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2644 if (!qmp) 2645 return -ENOMEM; 2646 2647 qmp->dev = dev; 2648 dev_set_drvdata(dev, qmp); 2649 2650 /* Get the specific init parameters of QMP phy */ 2651 cfg = of_device_get_match_data(dev); 2652 if (!cfg) 2653 return -EINVAL; 2654 2655 /* per PHY serdes; usually located at base address */ 2656 serdes = devm_platform_ioremap_resource(pdev, 0); 2657 if (IS_ERR(serdes)) 2658 return PTR_ERR(serdes); 2659 2660 /* per PHY dp_com; if PHY has dp_com control block */ 2661 if (cfg->has_phy_dp_com_ctrl) { 2662 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2663 if (IS_ERR(qmp->dp_com)) 2664 return PTR_ERR(qmp->dp_com); 2665 } 2666 2667 ret = qcom_qmp_phy_usb_clk_init(dev, cfg); 2668 if (ret) 2669 return ret; 2670 2671 ret = qcom_qmp_phy_usb_reset_init(dev, cfg); 2672 if (ret) 2673 return ret; 2674 2675 ret = qcom_qmp_phy_usb_vreg_init(dev, cfg); 2676 if (ret) { 2677 if (ret != -EPROBE_DEFER) 2678 dev_err(dev, "failed to get regulator supplies: %d\n", 2679 ret); 2680 return ret; 2681 } 2682 2683 num = of_get_available_child_count(dev->of_node); 2684 /* do we have a rogue child node ? */ 2685 if (num > 1) 2686 return -EINVAL; 2687 2688 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2689 if (!qmp->phys) 2690 return -ENOMEM; 2691 2692 pm_runtime_set_active(dev); 2693 pm_runtime_enable(dev); 2694 /* 2695 * Prevent runtime pm from being ON by default. Users can enable 2696 * it using power/control in sysfs. 2697 */ 2698 pm_runtime_forbid(dev); 2699 2700 id = 0; 2701 for_each_available_child_of_node(dev->of_node, child) { 2702 /* Create per-lane phy */ 2703 ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg); 2704 if (ret) { 2705 dev_err(dev, "failed to create lane%d phy, %d\n", 2706 id, ret); 2707 goto err_node_put; 2708 } 2709 2710 /* 2711 * Register the pipe clock provided by phy. 2712 * See function description to see details of this pipe clock. 2713 */ 2714 ret = phy_pipe_clk_register(qmp, child); 2715 if (ret) { 2716 dev_err(qmp->dev, 2717 "failed to register pipe clock source\n"); 2718 goto err_node_put; 2719 } 2720 2721 id++; 2722 } 2723 2724 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2725 if (!IS_ERR(phy_provider)) 2726 dev_info(dev, "Registered Qcom-QMP phy\n"); 2727 else 2728 pm_runtime_disable(dev); 2729 2730 return PTR_ERR_OR_ZERO(phy_provider); 2731 2732 err_node_put: 2733 pm_runtime_disable(dev); 2734 of_node_put(child); 2735 return ret; 2736 } 2737 2738 static struct platform_driver qcom_qmp_phy_usb_driver = { 2739 .probe = qcom_qmp_phy_usb_probe, 2740 .driver = { 2741 .name = "qcom-qmp-usb-phy", 2742 .pm = &qcom_qmp_phy_usb_pm_ops, 2743 .of_match_table = qcom_qmp_phy_usb_of_match_table, 2744 }, 2745 }; 2746 2747 module_platform_driver(qcom_qmp_phy_usb_driver); 2748 2749 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2750 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); 2751 MODULE_LICENSE("GPL v2"); 2752