1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 22 #include "phy-qcom-qmp.h" 23 #include "phy-qcom-qmp-pcs-misc-v3.h" 24 #include "phy-qcom-qmp-pcs-misc-v4.h" 25 #include "phy-qcom-qmp-pcs-usb-v4.h" 26 #include "phy-qcom-qmp-pcs-usb-v5.h" 27 #include "phy-qcom-qmp-pcs-usb-v6.h" 28 #include "phy-qcom-qmp-pcs-usb-v7.h" 29 30 /* QPHY_SW_RESET bit */ 31 #define SW_RESET BIT(0) 32 /* QPHY_POWER_DOWN_CONTROL */ 33 #define SW_PWRDN BIT(0) 34 /* QPHY_START_CONTROL bits */ 35 #define SERDES_START BIT(0) 36 #define PCS_START BIT(1) 37 /* QPHY_PCS_STATUS bit */ 38 #define PHYSTATUS BIT(6) 39 40 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 41 /* DP PHY soft reset */ 42 #define SW_DPPHY_RESET BIT(0) 43 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 44 #define SW_DPPHY_RESET_MUX BIT(1) 45 /* USB3 PHY soft reset */ 46 #define SW_USB3PHY_RESET BIT(2) 47 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 48 #define SW_USB3PHY_RESET_MUX BIT(3) 49 50 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 51 #define USB3_MODE BIT(0) /* enables USB3 mode */ 52 #define DP_MODE BIT(1) /* enables DP mode */ 53 54 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 55 #define ARCVR_DTCT_EN BIT(0) 56 #define ALFPS_DTCT_EN BIT(1) 57 #define ARCVR_DTCT_EVENT_SEL BIT(4) 58 59 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 60 #define IRQ_CLEAR BIT(0) 61 62 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 63 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 64 65 #define PHY_INIT_COMPLETE_TIMEOUT 10000 66 67 struct qmp_phy_init_tbl { 68 unsigned int offset; 69 unsigned int val; 70 /* 71 * mask of lanes for which this register is written 72 * for cases when second lane needs different values 73 */ 74 u8 lane_mask; 75 }; 76 77 #define QMP_PHY_INIT_CFG(o, v) \ 78 { \ 79 .offset = o, \ 80 .val = v, \ 81 .lane_mask = 0xff, \ 82 } 83 84 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 85 { \ 86 .offset = o, \ 87 .val = v, \ 88 .lane_mask = l, \ 89 } 90 91 /* set of registers with offsets different per-PHY */ 92 enum qphy_reg_layout { 93 /* PCS registers */ 94 QPHY_SW_RESET, 95 QPHY_START_CTRL, 96 QPHY_PCS_STATUS, 97 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 98 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 99 QPHY_PCS_POWER_DOWN_CONTROL, 100 QPHY_PCS_MISC_CLAMP_ENABLE, 101 /* Keep last to ensure regs_layout arrays are properly initialized */ 102 QPHY_LAYOUT_SIZE 103 }; 104 105 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 106 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 107 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 108 [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS, 109 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL, 110 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR, 111 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 112 }; 113 114 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 115 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 116 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 117 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 118 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 119 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 120 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 121 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE, 122 }; 123 124 static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = { 125 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 126 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 127 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 128 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 129 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 130 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 131 }; 132 133 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 134 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 135 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 136 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 137 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 138 139 /* In PCS_USB */ 140 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 141 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 142 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V4_PCS_MISC_CLAMP_ENABLE, 143 }; 144 145 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 146 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 147 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 148 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 149 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 150 151 /* In PCS_USB */ 152 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 153 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 154 }; 155 156 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 157 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 158 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 159 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 160 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 161 162 /* In PCS_USB */ 163 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 164 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 165 }; 166 167 static const unsigned int qmp_v7_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 168 [QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET, 169 [QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL, 170 [QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1, 171 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL, 172 173 /* In PCS_USB */ 174 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL, 175 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 176 }; 177 178 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = { 179 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), 180 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 181 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 182 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 183 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 184 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 185 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 186 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 187 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 188 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 189 /* PLL and Loop filter settings */ 190 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68), 191 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab), 192 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa), 193 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02), 194 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09), 195 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 196 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 197 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0), 198 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa), 199 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29), 200 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 201 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 202 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 203 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 204 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 205 /* SSC settings */ 206 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 207 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d), 208 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 209 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 210 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 211 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a), 212 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05), 213 }; 214 215 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = { 216 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 217 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 218 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 219 }; 220 221 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = { 222 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), 223 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 224 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c), 225 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 226 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 227 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 228 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 229 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 230 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 231 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c), 232 }; 233 234 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = { 235 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 236 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 237 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 238 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 239 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 240 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 241 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 242 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 243 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 244 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 245 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 246 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 247 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 248 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 249 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 250 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 251 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 252 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 253 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 254 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 255 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 256 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 257 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 258 }; 259 260 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { 261 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), 262 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 263 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 264 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 265 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 266 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 267 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 268 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 269 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 270 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 271 /* PLL and Loop filter settings */ 272 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 273 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 274 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 275 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 276 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 277 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 278 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 279 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 280 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 281 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 282 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 284 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 285 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 286 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 287 /* SSC settings */ 288 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 289 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 290 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 291 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 292 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 293 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 294 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 295 }; 296 297 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { 298 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), 299 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 300 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 301 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 302 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 303 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 304 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 305 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 306 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), 307 }; 308 309 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { 310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 326 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 327 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 332 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 333 }; 334 335 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { 336 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 337 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 338 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 339 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 340 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 341 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 342 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 343 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 344 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), 345 /* PLL and Loop filter settings */ 346 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 347 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 348 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 349 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 350 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 351 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 352 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 353 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 354 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 355 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 356 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 357 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 358 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 359 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 360 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 361 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 362 /* SSC settings */ 363 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 364 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 365 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 366 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 367 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 368 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 369 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 370 }; 371 372 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { 373 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 374 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 375 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 376 }; 377 378 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { 379 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 380 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 381 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 382 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 383 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), 384 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 385 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 386 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 387 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), 388 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 389 }; 390 391 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { 392 /* FLL settings */ 393 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03), 394 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02), 395 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09), 396 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42), 397 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85), 398 399 /* Lock Det settings */ 400 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1), 401 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f), 402 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47), 403 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08), 404 }; 405 406 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { 407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 443 }; 444 445 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { 446 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 447 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 448 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 449 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 450 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 451 }; 452 453 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { 454 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), 455 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), 456 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 457 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 458 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 459 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 460 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 461 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 462 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 463 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 464 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 465 }; 466 467 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 468 /* FLL settings */ 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 474 475 /* Lock Det settings */ 476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 480 481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), 485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), 486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), 487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), 488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 500 501 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 504 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 506 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 507 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 508 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 509 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 510 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 511 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 512 513 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 514 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 515 }; 516 517 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 556 }; 557 558 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { 559 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 560 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 561 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 562 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 563 }; 564 565 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { 566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), 571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), 573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 579 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), 582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 583 }; 584 585 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { 586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), 609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 613 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 618 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 619 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 620 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), 621 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 622 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 623 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 624 }; 625 626 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { 627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 653 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 655 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 656 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 657 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 658 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 659 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 660 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 661 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 662 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 663 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 664 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 665 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 666 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 667 }; 668 669 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { 670 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 671 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), 672 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 673 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), 674 }; 675 676 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { 677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), 680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), 681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), 682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), 697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 708 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 709 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), 711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 712 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 713 }; 714 715 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { 716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), 724 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 725 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 726 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 727 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 728 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 729 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 730 }; 731 732 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = { 733 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 734 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 735 }; 736 737 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { 738 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 739 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 740 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), 741 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 742 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 743 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 744 }; 745 746 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { 747 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 748 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), 749 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 750 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 751 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 752 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 753 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 754 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 755 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 756 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 757 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 758 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 759 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 760 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 761 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 762 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 763 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 764 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 765 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 766 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), 767 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 768 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 769 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 770 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 771 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 772 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 773 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 774 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 775 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 776 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 777 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 778 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 783 }; 784 785 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { 786 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 787 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 788 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 789 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 790 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 791 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 792 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 793 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 794 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 795 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 796 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 797 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 798 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 799 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 800 }; 801 802 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = { 803 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 804 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 805 }; 806 807 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { 808 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 809 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 810 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), 811 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 812 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), 813 }; 814 815 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), 817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 824 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 825 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 826 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 827 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), 828 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 829 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), 830 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), 831 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 832 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 833 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 834 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 835 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), 836 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 837 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 838 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 839 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 840 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 841 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 842 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 843 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 844 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 845 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 846 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 847 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 848 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 849 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 850 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 851 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 852 }; 853 854 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { 855 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 856 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 857 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 858 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 859 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 860 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 861 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), 862 }; 863 864 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { 865 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 866 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 867 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 868 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 869 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 870 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 871 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 872 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 873 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 874 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 875 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 876 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 877 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 878 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 879 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 880 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 881 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 882 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 883 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 884 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 885 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 886 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 887 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 888 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 889 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 890 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 891 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 892 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 893 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 894 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 895 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 896 }; 897 898 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_serdes_tbl[] = { 899 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x9e), 900 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06), 901 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 902 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 903 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 904 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 905 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e), 906 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82), 907 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 908 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 909 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xea), 910 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 911 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 912 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 913 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 914 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7), 915 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 916 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7), 917 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 918 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x9e), 919 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06), 920 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 921 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 922 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 923 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12), 924 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34), 925 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 926 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 927 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea), 928 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02), 929 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 930 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 931 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 932 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 933 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 934 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 935 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 936 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 937 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 938 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 939 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 940 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 941 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 942 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 943 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 944 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 945 }; 946 947 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_tx_tbl[] = { 948 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 949 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 950 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 951 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 952 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 953 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 954 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 955 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 956 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 957 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x21), 958 }; 959 960 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_rx_tbl[] = { 961 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 962 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 963 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 964 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 965 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 966 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 967 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 968 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 969 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 970 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 971 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 972 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 973 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 974 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 975 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 976 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 977 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 978 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 979 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 980 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 981 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 982 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 983 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 984 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 985 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 986 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff), 987 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf), 988 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed), 989 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 990 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 991 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 992 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 993 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 994 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 995 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 996 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 997 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 998 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 999 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 1000 }; 1001 1002 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_tbl[] = { 1003 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1004 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 1005 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 1006 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 1007 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 1008 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0xaa), 1009 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1010 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1011 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 1012 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1013 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1014 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 1015 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 1016 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 1017 }; 1018 1019 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_usb_tbl[] = { 1020 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1021 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1022 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1023 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1024 }; 1025 1026 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { 1027 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1028 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1029 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1030 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1031 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1032 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1033 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1034 }; 1035 1036 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { 1037 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1038 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1039 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1040 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1041 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1042 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1043 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1044 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1045 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1046 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1047 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1048 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1049 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1050 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1060 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1061 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1062 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1063 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1064 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1065 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1066 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1067 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1068 }; 1069 1070 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { 1071 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1072 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1073 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1074 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1075 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1076 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1077 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1078 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1079 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1080 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1081 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1082 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1083 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1084 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1085 }; 1086 1087 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = { 1088 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1089 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1090 }; 1091 1092 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { 1093 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 1094 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 1095 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 1096 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 1097 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), 1098 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), 1099 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 1100 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 1101 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 1102 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 1103 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 1104 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 1105 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 1106 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 1107 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 1108 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 1109 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 1110 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1111 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 1112 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 1113 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 1114 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 1115 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), 1116 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 1117 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 1118 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 1119 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 1120 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 1121 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 1122 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 1123 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 1124 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 1125 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 1126 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 1127 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 1128 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 1129 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), 1130 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), 1131 }; 1132 1133 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { 1134 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 1135 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 1136 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 1137 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 1138 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), 1139 }; 1140 1141 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { 1142 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 1143 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 1144 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 1145 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 1146 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 1147 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 1148 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 1149 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 1150 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 1151 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 1152 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 1153 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1154 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 1155 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 1156 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 1157 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 1158 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 1159 }; 1160 1161 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { 1162 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 1163 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 1164 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 1165 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 1166 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 1167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 1168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 1169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 1170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 1171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 1172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 1173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 1174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 1175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 1176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1177 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 1178 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1179 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1180 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 1181 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 1182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 1183 }; 1184 1185 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = { 1186 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab), 1191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea), 1192 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02), 1193 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde), 1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1225 }; 1226 1227 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = { 1228 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1229 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1230 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1231 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1235 }; 1236 1237 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = { 1238 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1239 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1240 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1258 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1262 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1263 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1264 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1265 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1266 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1267 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1269 }; 1270 1271 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = { 1272 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1273 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1274 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1275 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1276 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1277 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1278 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1279 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1280 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1281 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1282 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1283 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1284 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1285 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1286 }; 1287 1288 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = { 1289 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1290 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1291 }; 1292 1293 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = { 1294 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1295 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89), 1296 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1297 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1298 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1299 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1300 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1301 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1302 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1303 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1304 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1305 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1306 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1307 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1308 }; 1309 1310 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = { 1311 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1312 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1313 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f), 1314 }; 1315 1316 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_serdes_tbl[] = { 1317 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 1318 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1319 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02), 1320 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16), 1321 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36), 1322 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04), 1323 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x16), 1324 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x41), 1325 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x41), 1326 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55), 1327 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x75), 1328 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01), 1329 QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01), 1330 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE1, 0x25), 1331 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE1, 0x02), 1332 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 1333 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 1334 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 1335 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 1336 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 1337 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1338 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02), 1339 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16), 1340 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36), 1341 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x08), 1342 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x1a), 1343 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41), 1344 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0x55), 1345 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0x75), 1346 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01), 1347 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE0, 0x25), 1348 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE0, 0x02), 1349 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a), 1350 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x01), 1351 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62), 1352 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02), 1353 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_BUF_ENABLE, 0x0a), 1354 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x1a), 1355 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_CFG, 0x14), 1356 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x04), 1357 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0x20), 1358 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16), 1359 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 1360 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 1361 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 1362 QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC, 0x0c), 1363 }; 1364 1365 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_tx_tbl[] = { 1366 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_TX, 0x00), 1367 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_RX, 0x00), 1368 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1369 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 1370 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0xf5), 1371 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x3f), 1372 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x3f), 1373 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x5f), 1374 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RCV_DETECT_LVL_2, 0x12), 1375 QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x21), 1376 }; 1377 1378 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_rx_tbl[] = { 1379 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x0a), 1380 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x06), 1381 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1382 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1383 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1384 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1385 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_PI_CONTROLS, 0x99), 1386 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08), 1387 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08), 1388 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN1, 0x00), 1389 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN2, 0x0a), 1390 QMP_PHY_INIT_CFG(QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1391 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL1, 0x54), 1392 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x0f), 1393 QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x13), 1394 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1395 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1396 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1397 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1398 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1399 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1400 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x04), 1401 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1402 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3f), 1403 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xbf), 1404 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xff), 1405 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xdf), 1406 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xed), 1407 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xdc), 1408 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x5c), 1409 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x9c), 1410 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1d), 1411 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x09), 1412 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_EN_TIMER, 0x04), 1413 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1414 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DCC_CTRL1, 0x0c), 1415 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VTH_CODE, 0x10), 1416 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_CTRL1, 0x14), 1417 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08), 1418 }; 1419 1420 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_tbl[] = { 1421 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1422 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG2, 0x89), 1423 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG3, 0x20), 1424 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG6, 0x13), 1425 QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x21), 1426 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0xaa), 1427 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1428 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1429 QMP_PHY_INIT_CFG(QPHY_V7_PCS_CDR_RESET_TIME, 0x0a), 1430 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1431 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1432 QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x0c), 1433 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG1, 0x4b), 1434 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG5, 0x10), 1435 }; 1436 1437 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_usb_tbl[] = { 1438 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1439 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1440 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1441 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1442 }; 1443 1444 struct qmp_usb_offsets { 1445 u16 serdes; 1446 u16 pcs; 1447 u16 pcs_misc; 1448 u16 pcs_usb; 1449 u16 tx; 1450 u16 rx; 1451 /* for PHYs with >= 2 lanes */ 1452 u16 tx2; 1453 u16 rx2; 1454 }; 1455 1456 /* struct qmp_phy_cfg - per-PHY initialization config */ 1457 struct qmp_phy_cfg { 1458 int lanes; 1459 1460 const struct qmp_usb_offsets *offsets; 1461 1462 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1463 const struct qmp_phy_init_tbl *serdes_tbl; 1464 int serdes_tbl_num; 1465 const struct qmp_phy_init_tbl *tx_tbl; 1466 int tx_tbl_num; 1467 const struct qmp_phy_init_tbl *rx_tbl; 1468 int rx_tbl_num; 1469 const struct qmp_phy_init_tbl *pcs_tbl; 1470 int pcs_tbl_num; 1471 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1472 int pcs_usb_tbl_num; 1473 1474 /* regulators to be requested */ 1475 const char * const *vreg_list; 1476 int num_vregs; 1477 1478 /* array of registers with different offsets */ 1479 const unsigned int *regs; 1480 1481 /* true, if PHY needs delay after POWER_DOWN */ 1482 bool has_pwrdn_delay; 1483 1484 /* Offset from PCS to PCS_USB region */ 1485 unsigned int pcs_usb_offset; 1486 }; 1487 1488 struct qmp_usb { 1489 struct device *dev; 1490 1491 const struct qmp_phy_cfg *cfg; 1492 1493 void __iomem *serdes; 1494 void __iomem *pcs; 1495 void __iomem *pcs_misc; 1496 void __iomem *pcs_usb; 1497 void __iomem *tx; 1498 void __iomem *rx; 1499 void __iomem *tx2; 1500 void __iomem *rx2; 1501 1502 struct clk *pipe_clk; 1503 struct clk_bulk_data *clks; 1504 int num_clks; 1505 int num_resets; 1506 struct reset_control_bulk_data *resets; 1507 struct regulator_bulk_data *vregs; 1508 1509 enum phy_mode mode; 1510 1511 struct phy *phy; 1512 1513 struct clk_fixed_rate pipe_clk_fixed; 1514 }; 1515 1516 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1517 { 1518 u32 reg; 1519 1520 reg = readl(base + offset); 1521 reg |= val; 1522 writel(reg, base + offset); 1523 1524 /* ensure that above write is through */ 1525 readl(base + offset); 1526 } 1527 1528 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1529 { 1530 u32 reg; 1531 1532 reg = readl(base + offset); 1533 reg &= ~val; 1534 writel(reg, base + offset); 1535 1536 /* ensure that above write is through */ 1537 readl(base + offset); 1538 } 1539 1540 /* list of clocks required by phy */ 1541 static const char * const qmp_usb_phy_clk_l[] = { 1542 "aux", "cfg_ahb", "ref", "com_aux", 1543 }; 1544 1545 /* list of resets */ 1546 static const char * const usb3phy_legacy_reset_l[] = { 1547 "phy", "common", 1548 }; 1549 1550 static const char * const usb3phy_reset_l[] = { 1551 "phy_phy", "phy", 1552 }; 1553 1554 /* list of regulators */ 1555 static const char * const qmp_phy_vreg_l[] = { 1556 "vdda-phy", "vdda-pll", 1557 }; 1558 1559 static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = { 1560 .serdes = 0, 1561 .pcs = 0x800, 1562 .pcs_usb = 0x800, 1563 .tx = 0x200, 1564 .rx = 0x400, 1565 }; 1566 1567 static const struct qmp_usb_offsets qmp_usb_offsets_v3 = { 1568 .serdes = 0, 1569 .pcs = 0x600, 1570 .tx = 0x200, 1571 .rx = 0x400, 1572 }; 1573 1574 static const struct qmp_usb_offsets qmp_usb_offsets_v3_qcm2290 = { 1575 .serdes = 0x0, 1576 .pcs = 0xc00, 1577 .pcs_misc = 0xa00, 1578 .tx = 0x200, 1579 .rx = 0x400, 1580 .tx2 = 0x600, 1581 .rx2 = 0x800, 1582 }; 1583 1584 static const struct qmp_usb_offsets qmp_usb_offsets_v4 = { 1585 .serdes = 0, 1586 .pcs = 0x0800, 1587 .pcs_usb = 0x0e00, 1588 .tx = 0x0200, 1589 .rx = 0x0400, 1590 }; 1591 1592 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { 1593 .serdes = 0, 1594 .pcs = 0x0200, 1595 .pcs_usb = 0x1200, 1596 .tx = 0x0e00, 1597 .rx = 0x1000, 1598 }; 1599 1600 static const struct qmp_usb_offsets qmp_usb_offsets_v6 = { 1601 .serdes = 0, 1602 .pcs = 0x0200, 1603 .pcs_usb = 0x1200, 1604 .tx = 0x0e00, 1605 .rx = 0x1000, 1606 }; 1607 1608 static const struct qmp_usb_offsets qmp_usb_offsets_v7 = { 1609 .serdes = 0, 1610 .pcs = 0x0200, 1611 .pcs_usb = 0x1200, 1612 .tx = 0x0e00, 1613 .rx = 0x1000, 1614 }; 1615 1616 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { 1617 .lanes = 1, 1618 1619 .offsets = &qmp_usb_offsets_v3, 1620 1621 .serdes_tbl = ipq8074_usb3_serdes_tbl, 1622 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), 1623 .tx_tbl = msm8996_usb3_tx_tbl, 1624 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1625 .rx_tbl = ipq8074_usb3_rx_tbl, 1626 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), 1627 .pcs_tbl = ipq8074_usb3_pcs_tbl, 1628 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), 1629 .vreg_list = qmp_phy_vreg_l, 1630 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1631 .regs = qmp_v3_usb3phy_regs_layout, 1632 }; 1633 1634 static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { 1635 .lanes = 1, 1636 1637 .offsets = &qmp_usb_offsets_ipq9574, 1638 1639 .serdes_tbl = ipq9574_usb3_serdes_tbl, 1640 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl), 1641 .tx_tbl = ipq9574_usb3_tx_tbl, 1642 .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl), 1643 .rx_tbl = ipq9574_usb3_rx_tbl, 1644 .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl), 1645 .pcs_tbl = ipq9574_usb3_pcs_tbl, 1646 .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl), 1647 .vreg_list = qmp_phy_vreg_l, 1648 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1649 .regs = qmp_v3_usb3phy_regs_layout, 1650 }; 1651 1652 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 1653 .lanes = 1, 1654 1655 .offsets = &qmp_usb_offsets_v3, 1656 1657 .serdes_tbl = msm8996_usb3_serdes_tbl, 1658 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), 1659 .tx_tbl = msm8996_usb3_tx_tbl, 1660 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1661 .rx_tbl = msm8996_usb3_rx_tbl, 1662 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), 1663 .pcs_tbl = msm8996_usb3_pcs_tbl, 1664 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), 1665 .vreg_list = qmp_phy_vreg_l, 1666 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1667 .regs = qmp_v2_usb3phy_regs_layout, 1668 }; 1669 1670 static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = { 1671 .lanes = 1, 1672 1673 .offsets = &qmp_usb_offsets_v5, 1674 1675 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1676 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1677 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, 1678 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), 1679 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, 1680 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1681 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl, 1682 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl), 1683 .pcs_usb_tbl = sa8775p_usb3_uniphy_pcs_usb_tbl, 1684 .pcs_usb_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl), 1685 .vreg_list = qmp_phy_vreg_l, 1686 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1687 .regs = qmp_v5_usb3phy_regs_layout, 1688 }; 1689 1690 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { 1691 .lanes = 1, 1692 1693 .offsets = &qmp_usb_offsets_v5, 1694 1695 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1696 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1697 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, 1698 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), 1699 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, 1700 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1701 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl, 1702 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl), 1703 .pcs_usb_tbl = sc8280xp_usb3_uniphy_pcs_usb_tbl, 1704 .pcs_usb_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl), 1705 .vreg_list = qmp_phy_vreg_l, 1706 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1707 .regs = qmp_v5_usb3phy_regs_layout, 1708 }; 1709 1710 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 1711 .lanes = 1, 1712 1713 .offsets = &qmp_usb_offsets_v3, 1714 1715 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, 1716 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), 1717 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, 1718 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), 1719 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, 1720 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), 1721 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, 1722 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), 1723 .vreg_list = qmp_phy_vreg_l, 1724 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1725 .regs = qmp_v3_usb3phy_regs_layout, 1726 1727 .has_pwrdn_delay = true, 1728 }; 1729 1730 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { 1731 .lanes = 2, 1732 1733 .offsets = &qmp_usb_offsets_v3_qcm2290, 1734 1735 .serdes_tbl = msm8998_usb3_serdes_tbl, 1736 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), 1737 .tx_tbl = msm8998_usb3_tx_tbl, 1738 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), 1739 .rx_tbl = msm8998_usb3_rx_tbl, 1740 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), 1741 .pcs_tbl = msm8998_usb3_pcs_tbl, 1742 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), 1743 .vreg_list = qmp_phy_vreg_l, 1744 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1745 .regs = qmp_v3_usb3phy_regs_layout, 1746 }; 1747 1748 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { 1749 .lanes = 1, 1750 1751 .offsets = &qmp_usb_offsets_v4, 1752 1753 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1754 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1755 .tx_tbl = sm8150_usb3_uniphy_tx_tbl, 1756 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), 1757 .rx_tbl = sm8150_usb3_uniphy_rx_tbl, 1758 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), 1759 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, 1760 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), 1761 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl, 1762 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl), 1763 .vreg_list = qmp_phy_vreg_l, 1764 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1765 .regs = qmp_v4_usb3phy_regs_layout, 1766 .pcs_usb_offset = 0x600, 1767 1768 .has_pwrdn_delay = true, 1769 }; 1770 1771 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { 1772 .lanes = 1, 1773 1774 .offsets = &qmp_usb_offsets_v4, 1775 1776 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1777 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1778 .tx_tbl = sm8250_usb3_uniphy_tx_tbl, 1779 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), 1780 .rx_tbl = sm8250_usb3_uniphy_rx_tbl, 1781 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), 1782 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1783 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1784 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1785 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1786 .vreg_list = qmp_phy_vreg_l, 1787 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1788 .regs = qmp_v4_usb3phy_regs_layout, 1789 .pcs_usb_offset = 0x600, 1790 1791 .has_pwrdn_delay = true, 1792 }; 1793 1794 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { 1795 .lanes = 1, 1796 1797 .offsets = &qmp_usb_offsets_v4, 1798 1799 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1800 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1801 .tx_tbl = sdx55_usb3_uniphy_tx_tbl, 1802 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), 1803 .rx_tbl = sdx55_usb3_uniphy_rx_tbl, 1804 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), 1805 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1806 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1807 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1808 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1809 .vreg_list = qmp_phy_vreg_l, 1810 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1811 .regs = qmp_v4_usb3phy_regs_layout, 1812 .pcs_usb_offset = 0x600, 1813 1814 .has_pwrdn_delay = true, 1815 }; 1816 1817 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { 1818 .lanes = 1, 1819 1820 .offsets = &qmp_usb_offsets_v5, 1821 1822 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1823 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1824 .tx_tbl = sdx65_usb3_uniphy_tx_tbl, 1825 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), 1826 .rx_tbl = sdx65_usb3_uniphy_rx_tbl, 1827 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), 1828 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1829 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1830 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1831 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1832 .vreg_list = qmp_phy_vreg_l, 1833 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1834 .regs = qmp_v5_usb3phy_regs_layout, 1835 .pcs_usb_offset = 0x1000, 1836 1837 .has_pwrdn_delay = true, 1838 }; 1839 1840 static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = { 1841 .lanes = 1, 1842 .offsets = &qmp_usb_offsets_v6, 1843 1844 .serdes_tbl = sdx75_usb3_uniphy_serdes_tbl, 1845 .serdes_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl), 1846 .tx_tbl = sdx75_usb3_uniphy_tx_tbl, 1847 .tx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl), 1848 .rx_tbl = sdx75_usb3_uniphy_rx_tbl, 1849 .rx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl), 1850 .pcs_tbl = sdx75_usb3_uniphy_pcs_tbl, 1851 .pcs_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl), 1852 .pcs_usb_tbl = sdx75_usb3_uniphy_pcs_usb_tbl, 1853 .pcs_usb_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl), 1854 .vreg_list = qmp_phy_vreg_l, 1855 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1856 .regs = qmp_v6_usb3phy_regs_layout, 1857 .pcs_usb_offset = 0x1000, 1858 1859 .has_pwrdn_delay = true, 1860 }; 1861 1862 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { 1863 .lanes = 1, 1864 1865 .offsets = &qmp_usb_offsets_v5, 1866 1867 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1868 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1869 .tx_tbl = sm8350_usb3_uniphy_tx_tbl, 1870 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), 1871 .rx_tbl = sm8350_usb3_uniphy_rx_tbl, 1872 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), 1873 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1874 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1875 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1876 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1877 .vreg_list = qmp_phy_vreg_l, 1878 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1879 .regs = qmp_v5_usb3phy_regs_layout, 1880 .pcs_usb_offset = 0x1000, 1881 1882 .has_pwrdn_delay = true, 1883 }; 1884 1885 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { 1886 .lanes = 2, 1887 1888 .offsets = &qmp_usb_offsets_v3_qcm2290, 1889 1890 .serdes_tbl = qcm2290_usb3_serdes_tbl, 1891 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 1892 .tx_tbl = qcm2290_usb3_tx_tbl, 1893 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 1894 .rx_tbl = qcm2290_usb3_rx_tbl, 1895 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 1896 .pcs_tbl = qcm2290_usb3_pcs_tbl, 1897 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 1898 .vreg_list = qmp_phy_vreg_l, 1899 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1900 .regs = qmp_v3_usb3phy_regs_layout_qcm2290, 1901 }; 1902 1903 static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = { 1904 .lanes = 1, 1905 1906 .offsets = &qmp_usb_offsets_v7, 1907 1908 .serdes_tbl = x1e80100_usb3_uniphy_serdes_tbl, 1909 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_serdes_tbl), 1910 .tx_tbl = x1e80100_usb3_uniphy_tx_tbl, 1911 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_tx_tbl), 1912 .rx_tbl = x1e80100_usb3_uniphy_rx_tbl, 1913 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_rx_tbl), 1914 .pcs_tbl = x1e80100_usb3_uniphy_pcs_tbl, 1915 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_tbl), 1916 .pcs_usb_tbl = x1e80100_usb3_uniphy_pcs_usb_tbl, 1917 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_usb_tbl), 1918 .vreg_list = qmp_phy_vreg_l, 1919 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1920 .regs = qmp_v7_usb3phy_regs_layout, 1921 }; 1922 1923 static void qmp_usb_configure_lane(void __iomem *base, 1924 const struct qmp_phy_init_tbl tbl[], 1925 int num, 1926 u8 lane_mask) 1927 { 1928 int i; 1929 const struct qmp_phy_init_tbl *t = tbl; 1930 1931 if (!t) 1932 return; 1933 1934 for (i = 0; i < num; i++, t++) { 1935 if (!(t->lane_mask & lane_mask)) 1936 continue; 1937 1938 writel(t->val, base + t->offset); 1939 } 1940 } 1941 1942 static void qmp_usb_configure(void __iomem *base, 1943 const struct qmp_phy_init_tbl tbl[], 1944 int num) 1945 { 1946 qmp_usb_configure_lane(base, tbl, num, 0xff); 1947 } 1948 1949 static int qmp_usb_serdes_init(struct qmp_usb *qmp) 1950 { 1951 const struct qmp_phy_cfg *cfg = qmp->cfg; 1952 void __iomem *serdes = qmp->serdes; 1953 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1954 int serdes_tbl_num = cfg->serdes_tbl_num; 1955 1956 qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num); 1957 1958 return 0; 1959 } 1960 1961 static int qmp_usb_init(struct phy *phy) 1962 { 1963 struct qmp_usb *qmp = phy_get_drvdata(phy); 1964 const struct qmp_phy_cfg *cfg = qmp->cfg; 1965 void __iomem *pcs = qmp->pcs; 1966 int ret; 1967 1968 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1969 if (ret) { 1970 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1971 return ret; 1972 } 1973 1974 ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets); 1975 if (ret) { 1976 dev_err(qmp->dev, "reset assert failed\n"); 1977 goto err_disable_regulators; 1978 } 1979 1980 ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets); 1981 if (ret) { 1982 dev_err(qmp->dev, "reset deassert failed\n"); 1983 goto err_disable_regulators; 1984 } 1985 1986 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 1987 if (ret) 1988 goto err_assert_reset; 1989 1990 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1991 1992 return 0; 1993 1994 err_assert_reset: 1995 reset_control_bulk_assert(qmp->num_resets, qmp->resets); 1996 err_disable_regulators: 1997 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1998 1999 return ret; 2000 } 2001 2002 static int qmp_usb_exit(struct phy *phy) 2003 { 2004 struct qmp_usb *qmp = phy_get_drvdata(phy); 2005 const struct qmp_phy_cfg *cfg = qmp->cfg; 2006 2007 reset_control_bulk_assert(qmp->num_resets, qmp->resets); 2008 2009 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2010 2011 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2012 2013 return 0; 2014 } 2015 2016 static int qmp_usb_power_on(struct phy *phy) 2017 { 2018 struct qmp_usb *qmp = phy_get_drvdata(phy); 2019 const struct qmp_phy_cfg *cfg = qmp->cfg; 2020 void __iomem *tx = qmp->tx; 2021 void __iomem *rx = qmp->rx; 2022 void __iomem *pcs = qmp->pcs; 2023 void __iomem *pcs_usb = qmp->pcs_usb; 2024 void __iomem *status; 2025 unsigned int val; 2026 int ret; 2027 2028 qmp_usb_serdes_init(qmp); 2029 2030 ret = clk_prepare_enable(qmp->pipe_clk); 2031 if (ret) { 2032 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2033 return ret; 2034 } 2035 2036 /* Tx, Rx, and PCS configurations */ 2037 qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2038 qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2039 2040 if (cfg->lanes >= 2) { 2041 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2042 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2043 } 2044 2045 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2046 2047 if (pcs_usb) 2048 qmp_usb_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num); 2049 2050 if (cfg->has_pwrdn_delay) 2051 usleep_range(10, 20); 2052 2053 /* Pull PHY out of reset state */ 2054 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2055 2056 /* start SerDes and Phy-Coding-Sublayer */ 2057 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2058 2059 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2060 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2061 PHY_INIT_COMPLETE_TIMEOUT); 2062 if (ret) { 2063 dev_err(qmp->dev, "phy initialization timed-out\n"); 2064 goto err_disable_pipe_clk; 2065 } 2066 2067 return 0; 2068 2069 err_disable_pipe_clk: 2070 clk_disable_unprepare(qmp->pipe_clk); 2071 2072 return ret; 2073 } 2074 2075 static int qmp_usb_power_off(struct phy *phy) 2076 { 2077 struct qmp_usb *qmp = phy_get_drvdata(phy); 2078 const struct qmp_phy_cfg *cfg = qmp->cfg; 2079 2080 clk_disable_unprepare(qmp->pipe_clk); 2081 2082 /* PHY reset */ 2083 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2084 2085 /* stop SerDes and Phy-Coding-Sublayer */ 2086 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2087 SERDES_START | PCS_START); 2088 2089 /* Put PHY into POWER DOWN state: active low */ 2090 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2091 SW_PWRDN); 2092 2093 return 0; 2094 } 2095 2096 static int qmp_usb_enable(struct phy *phy) 2097 { 2098 int ret; 2099 2100 ret = qmp_usb_init(phy); 2101 if (ret) 2102 return ret; 2103 2104 ret = qmp_usb_power_on(phy); 2105 if (ret) 2106 qmp_usb_exit(phy); 2107 2108 return ret; 2109 } 2110 2111 static int qmp_usb_disable(struct phy *phy) 2112 { 2113 int ret; 2114 2115 ret = qmp_usb_power_off(phy); 2116 if (ret) 2117 return ret; 2118 return qmp_usb_exit(phy); 2119 } 2120 2121 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2122 { 2123 struct qmp_usb *qmp = phy_get_drvdata(phy); 2124 2125 qmp->mode = mode; 2126 2127 return 0; 2128 } 2129 2130 static const struct phy_ops qmp_usb_phy_ops = { 2131 .init = qmp_usb_enable, 2132 .exit = qmp_usb_disable, 2133 .set_mode = qmp_usb_set_mode, 2134 .owner = THIS_MODULE, 2135 }; 2136 2137 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp) 2138 { 2139 const struct qmp_phy_cfg *cfg = qmp->cfg; 2140 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2141 void __iomem *pcs_misc = qmp->pcs_misc; 2142 u32 intr_mask; 2143 2144 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2145 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2146 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2147 else 2148 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2149 2150 /* Clear any pending interrupts status */ 2151 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2152 /* Writing 1 followed by 0 clears the interrupt */ 2153 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2154 2155 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2156 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2157 2158 /* Enable required PHY autonomous mode interrupts */ 2159 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2160 2161 /* Enable i/o clamp_n for autonomous mode */ 2162 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE]) 2163 qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN); 2164 } 2165 2166 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp) 2167 { 2168 const struct qmp_phy_cfg *cfg = qmp->cfg; 2169 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2170 void __iomem *pcs_misc = qmp->pcs_misc; 2171 2172 /* Disable i/o clamp_n on resume for normal mode */ 2173 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE]) 2174 qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN); 2175 2176 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2177 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2178 2179 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2180 /* Writing 1 followed by 0 clears the interrupt */ 2181 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2182 } 2183 2184 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev) 2185 { 2186 struct qmp_usb *qmp = dev_get_drvdata(dev); 2187 2188 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2189 2190 if (!qmp->phy->init_count) { 2191 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2192 return 0; 2193 } 2194 2195 qmp_usb_enable_autonomous_mode(qmp); 2196 2197 clk_disable_unprepare(qmp->pipe_clk); 2198 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2199 2200 return 0; 2201 } 2202 2203 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev) 2204 { 2205 struct qmp_usb *qmp = dev_get_drvdata(dev); 2206 int ret = 0; 2207 2208 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2209 2210 if (!qmp->phy->init_count) { 2211 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2212 return 0; 2213 } 2214 2215 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2216 if (ret) 2217 return ret; 2218 2219 ret = clk_prepare_enable(qmp->pipe_clk); 2220 if (ret) { 2221 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2222 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2223 return ret; 2224 } 2225 2226 qmp_usb_disable_autonomous_mode(qmp); 2227 2228 return 0; 2229 } 2230 2231 static const struct dev_pm_ops qmp_usb_pm_ops = { 2232 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend, 2233 qmp_usb_runtime_resume, NULL) 2234 }; 2235 2236 static int qmp_usb_vreg_init(struct qmp_usb *qmp) 2237 { 2238 const struct qmp_phy_cfg *cfg = qmp->cfg; 2239 struct device *dev = qmp->dev; 2240 int num = cfg->num_vregs; 2241 int i; 2242 2243 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2244 if (!qmp->vregs) 2245 return -ENOMEM; 2246 2247 for (i = 0; i < num; i++) 2248 qmp->vregs[i].supply = cfg->vreg_list[i]; 2249 2250 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2251 } 2252 2253 static int qmp_usb_reset_init(struct qmp_usb *qmp, 2254 const char *const *reset_list, 2255 int num_resets) 2256 { 2257 struct device *dev = qmp->dev; 2258 int i; 2259 int ret; 2260 2261 qmp->resets = devm_kcalloc(dev, num_resets, 2262 sizeof(*qmp->resets), GFP_KERNEL); 2263 if (!qmp->resets) 2264 return -ENOMEM; 2265 2266 for (i = 0; i < num_resets; i++) 2267 qmp->resets[i].id = reset_list[i]; 2268 2269 qmp->num_resets = num_resets; 2270 2271 ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets); 2272 if (ret) 2273 return dev_err_probe(dev, ret, "failed to get resets\n"); 2274 2275 return 0; 2276 } 2277 2278 static int qmp_usb_clk_init(struct qmp_usb *qmp) 2279 { 2280 struct device *dev = qmp->dev; 2281 int num = ARRAY_SIZE(qmp_usb_phy_clk_l); 2282 int i; 2283 2284 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2285 if (!qmp->clks) 2286 return -ENOMEM; 2287 2288 for (i = 0; i < num; i++) 2289 qmp->clks[i].id = qmp_usb_phy_clk_l[i]; 2290 2291 qmp->num_clks = num; 2292 2293 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 2294 } 2295 2296 static void phy_clk_release_provider(void *res) 2297 { 2298 of_clk_del_provider(res); 2299 } 2300 2301 /* 2302 * Register a fixed rate pipe clock. 2303 * 2304 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2305 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2306 * by the PHY driver for its operations. 2307 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2308 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2309 * Below picture shows this relationship. 2310 * 2311 * +---------------+ 2312 * | PHY block |<<---------------------------------------+ 2313 * | | | 2314 * | +-------+ | +-----+ | 2315 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2316 * clk | +-------+ | +-----+ 2317 * +---------------+ 2318 */ 2319 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np) 2320 { 2321 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2322 struct clk_init_data init = { }; 2323 int ret; 2324 2325 ret = of_property_read_string(np, "clock-output-names", &init.name); 2326 if (ret) { 2327 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2328 return ret; 2329 } 2330 2331 init.ops = &clk_fixed_rate_ops; 2332 2333 /* controllers using QMP phys use 125MHz pipe clock interface */ 2334 fixed->fixed_rate = 125000000; 2335 fixed->hw.init = &init; 2336 2337 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2338 if (ret) 2339 return ret; 2340 2341 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2342 if (ret) 2343 return ret; 2344 2345 /* 2346 * Roll a devm action because the clock provider is the child node, but 2347 * the child node is not actually a device. 2348 */ 2349 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2350 } 2351 2352 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np, 2353 int index, bool exclusive) 2354 { 2355 struct resource res; 2356 2357 if (!exclusive) { 2358 if (of_address_to_resource(np, index, &res)) 2359 return IOMEM_ERR_PTR(-EINVAL); 2360 2361 return devm_ioremap(dev, res.start, resource_size(&res)); 2362 } 2363 2364 return devm_of_iomap(dev, np, index, NULL); 2365 } 2366 2367 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np) 2368 { 2369 struct platform_device *pdev = to_platform_device(qmp->dev); 2370 const struct qmp_phy_cfg *cfg = qmp->cfg; 2371 struct device *dev = qmp->dev; 2372 bool exclusive = true; 2373 int ret; 2374 2375 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2376 if (IS_ERR(qmp->serdes)) 2377 return PTR_ERR(qmp->serdes); 2378 2379 /* 2380 * FIXME: These bindings should be fixed to not rely on overlapping 2381 * mappings for PCS. 2382 */ 2383 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy")) 2384 exclusive = false; 2385 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy")) 2386 exclusive = false; 2387 2388 /* 2389 * Get memory resources for the PHY: 2390 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2391 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2392 * For single lane PHYs: pcs_misc (optional) -> 3. 2393 */ 2394 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2395 if (IS_ERR(qmp->tx)) 2396 return PTR_ERR(qmp->tx); 2397 2398 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2399 if (IS_ERR(qmp->rx)) 2400 return PTR_ERR(qmp->rx); 2401 2402 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive); 2403 if (IS_ERR(qmp->pcs)) 2404 return PTR_ERR(qmp->pcs); 2405 2406 if (cfg->pcs_usb_offset) 2407 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 2408 2409 if (cfg->lanes >= 2) { 2410 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2411 if (IS_ERR(qmp->tx2)) 2412 return PTR_ERR(qmp->tx2); 2413 2414 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2415 if (IS_ERR(qmp->rx2)) 2416 return PTR_ERR(qmp->rx2); 2417 2418 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2419 } else { 2420 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2421 } 2422 2423 if (IS_ERR(qmp->pcs_misc)) { 2424 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2425 qmp->pcs_misc = NULL; 2426 } 2427 2428 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2429 if (IS_ERR(qmp->pipe_clk)) { 2430 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2431 "failed to get pipe clock\n"); 2432 } 2433 2434 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 2435 if (ret < 0) 2436 return ret; 2437 2438 qmp->num_clks = ret; 2439 2440 ret = qmp_usb_reset_init(qmp, usb3phy_legacy_reset_l, 2441 ARRAY_SIZE(usb3phy_legacy_reset_l)); 2442 if (ret) 2443 return ret; 2444 2445 return 0; 2446 } 2447 2448 static int qmp_usb_parse_dt(struct qmp_usb *qmp) 2449 { 2450 struct platform_device *pdev = to_platform_device(qmp->dev); 2451 const struct qmp_phy_cfg *cfg = qmp->cfg; 2452 const struct qmp_usb_offsets *offs = cfg->offsets; 2453 struct device *dev = qmp->dev; 2454 void __iomem *base; 2455 int ret; 2456 2457 if (!offs) 2458 return -EINVAL; 2459 2460 base = devm_platform_ioremap_resource(pdev, 0); 2461 if (IS_ERR(base)) 2462 return PTR_ERR(base); 2463 2464 qmp->serdes = base + offs->serdes; 2465 qmp->pcs = base + offs->pcs; 2466 if (offs->pcs_usb) 2467 qmp->pcs_usb = base + offs->pcs_usb; 2468 if (offs->pcs_misc) 2469 qmp->pcs_misc = base + offs->pcs_misc; 2470 qmp->tx = base + offs->tx; 2471 qmp->rx = base + offs->rx; 2472 2473 if (cfg->lanes >= 2) { 2474 qmp->tx2 = base + offs->tx2; 2475 qmp->rx2 = base + offs->rx2; 2476 } 2477 2478 ret = qmp_usb_clk_init(qmp); 2479 if (ret) 2480 return ret; 2481 2482 qmp->pipe_clk = devm_clk_get(dev, "pipe"); 2483 if (IS_ERR(qmp->pipe_clk)) { 2484 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2485 "failed to get pipe clock\n"); 2486 } 2487 2488 ret = qmp_usb_reset_init(qmp, usb3phy_reset_l, 2489 ARRAY_SIZE(usb3phy_reset_l)); 2490 if (ret) 2491 return ret; 2492 2493 return 0; 2494 } 2495 2496 static int qmp_usb_probe(struct platform_device *pdev) 2497 { 2498 struct device *dev = &pdev->dev; 2499 struct phy_provider *phy_provider; 2500 struct device_node *np; 2501 struct qmp_usb *qmp; 2502 int ret; 2503 2504 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2505 if (!qmp) 2506 return -ENOMEM; 2507 2508 qmp->dev = dev; 2509 2510 qmp->cfg = of_device_get_match_data(dev); 2511 if (!qmp->cfg) 2512 return -EINVAL; 2513 2514 ret = qmp_usb_vreg_init(qmp); 2515 if (ret) 2516 return ret; 2517 2518 /* Check for legacy binding with child node. */ 2519 np = of_get_next_available_child(dev->of_node, NULL); 2520 if (np) { 2521 ret = qmp_usb_parse_dt_legacy(qmp, np); 2522 } else { 2523 np = of_node_get(dev->of_node); 2524 ret = qmp_usb_parse_dt(qmp); 2525 } 2526 if (ret) 2527 goto err_node_put; 2528 2529 pm_runtime_set_active(dev); 2530 ret = devm_pm_runtime_enable(dev); 2531 if (ret) 2532 goto err_node_put; 2533 /* 2534 * Prevent runtime pm from being ON by default. Users can enable 2535 * it using power/control in sysfs. 2536 */ 2537 pm_runtime_forbid(dev); 2538 2539 ret = phy_pipe_clk_register(qmp, np); 2540 if (ret) 2541 goto err_node_put; 2542 2543 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops); 2544 if (IS_ERR(qmp->phy)) { 2545 ret = PTR_ERR(qmp->phy); 2546 dev_err(dev, "failed to create PHY: %d\n", ret); 2547 goto err_node_put; 2548 } 2549 2550 phy_set_drvdata(qmp->phy, qmp); 2551 2552 of_node_put(np); 2553 2554 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2555 2556 return PTR_ERR_OR_ZERO(phy_provider); 2557 2558 err_node_put: 2559 of_node_put(np); 2560 return ret; 2561 } 2562 2563 static const struct of_device_id qmp_usb_of_match_table[] = { 2564 { 2565 .compatible = "qcom,ipq6018-qmp-usb3-phy", 2566 .data = &ipq8074_usb3phy_cfg, 2567 }, { 2568 .compatible = "qcom,ipq8074-qmp-usb3-phy", 2569 .data = &ipq8074_usb3phy_cfg, 2570 }, { 2571 .compatible = "qcom,ipq9574-qmp-usb3-phy", 2572 .data = &ipq9574_usb3phy_cfg, 2573 }, { 2574 .compatible = "qcom,msm8996-qmp-usb3-phy", 2575 .data = &msm8996_usb3phy_cfg, 2576 }, { 2577 .compatible = "qcom,msm8998-qmp-usb3-phy", 2578 .data = &msm8998_usb3phy_cfg, 2579 }, { 2580 .compatible = "qcom,qcm2290-qmp-usb3-phy", 2581 .data = &qcm2290_usb3phy_cfg, 2582 }, { 2583 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy", 2584 .data = &sa8775p_usb3_uniphy_cfg, 2585 }, { 2586 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy", 2587 .data = &sc8280xp_usb3_uniphy_cfg, 2588 }, { 2589 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 2590 .data = &qmp_v3_usb3_uniphy_cfg, 2591 }, { 2592 .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 2593 .data = &sdx55_usb3_uniphy_cfg, 2594 }, { 2595 .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 2596 .data = &sdx65_usb3_uniphy_cfg, 2597 }, { 2598 .compatible = "qcom,sdx75-qmp-usb3-uni-phy", 2599 .data = &sdx75_usb3_uniphy_cfg, 2600 }, { 2601 .compatible = "qcom,sm6115-qmp-usb3-phy", 2602 .data = &qcm2290_usb3phy_cfg, 2603 }, { 2604 .compatible = "qcom,sm8150-qmp-usb3-uni-phy", 2605 .data = &sm8150_usb3_uniphy_cfg, 2606 }, { 2607 .compatible = "qcom,sm8250-qmp-usb3-uni-phy", 2608 .data = &sm8250_usb3_uniphy_cfg, 2609 }, { 2610 .compatible = "qcom,sm8350-qmp-usb3-uni-phy", 2611 .data = &sm8350_usb3_uniphy_cfg, 2612 }, { 2613 .compatible = "qcom,x1e80100-qmp-usb3-uni-phy", 2614 .data = &x1e80100_usb3_uniphy_cfg, 2615 }, 2616 { }, 2617 }; 2618 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table); 2619 2620 static struct platform_driver qmp_usb_driver = { 2621 .probe = qmp_usb_probe, 2622 .driver = { 2623 .name = "qcom-qmp-usb-phy", 2624 .pm = &qmp_usb_pm_ops, 2625 .of_match_table = qmp_usb_of_match_table, 2626 }, 2627 }; 2628 2629 module_platform_driver(qmp_usb_driver); 2630 2631 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2632 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); 2633 MODULE_LICENSE("GPL v2"); 2634