1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 22 #include "phy-qcom-qmp-common.h" 23 24 #include "phy-qcom-qmp.h" 25 #include "phy-qcom-qmp-pcs-misc-v3.h" 26 #include "phy-qcom-qmp-pcs-misc-v4.h" 27 #include "phy-qcom-qmp-pcs-usb-v4.h" 28 #include "phy-qcom-qmp-pcs-usb-v5.h" 29 #include "phy-qcom-qmp-pcs-usb-v6.h" 30 #include "phy-qcom-qmp-pcs-usb-v7.h" 31 #include "phy-qcom-qmp-pcs-usb-v8.h" 32 33 #define PHY_INIT_COMPLETE_TIMEOUT 10000 34 35 /* set of registers with offsets different per-PHY */ 36 enum qphy_reg_layout { 37 /* PCS registers */ 38 QPHY_SW_RESET, 39 QPHY_START_CTRL, 40 QPHY_PCS_STATUS, 41 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 42 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 43 QPHY_PCS_POWER_DOWN_CONTROL, 44 QPHY_PCS_MISC_CLAMP_ENABLE, 45 /* Keep last to ensure regs_layout arrays are properly initialized */ 46 QPHY_LAYOUT_SIZE 47 }; 48 49 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 50 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 51 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 52 [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS, 53 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL, 54 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR, 55 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 56 }; 57 58 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 59 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 60 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 61 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 62 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 63 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 64 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 65 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE, 66 }; 67 68 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 69 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 70 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 71 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 72 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 73 74 /* In PCS_USB */ 75 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 76 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 77 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V4_PCS_MISC_CLAMP_ENABLE, 78 }; 79 80 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 81 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 82 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 83 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 84 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 85 86 /* In PCS_USB */ 87 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 88 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 89 }; 90 91 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 92 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 93 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 94 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 95 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 96 97 /* In PCS_USB */ 98 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 99 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 100 }; 101 102 static const unsigned int qmp_v7_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 103 [QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET, 104 [QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL, 105 [QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1, 106 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL, 107 108 /* In PCS_USB */ 109 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL, 110 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 111 }; 112 113 static const struct qmp_phy_init_tbl glymur_usb3_uniphy_serdes_tbl[] = { 114 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 115 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01), 116 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02), 117 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16), 118 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36), 119 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04), 120 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16), 121 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41), 122 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41), 123 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00), 124 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55), 125 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75), 126 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01), 127 QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01), 128 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25), 129 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02), 130 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 131 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 132 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 133 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 134 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 135 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01), 136 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02), 137 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16), 138 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36), 139 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08), 140 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a), 141 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41), 142 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00), 143 144 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55), 145 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75), 146 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01), 147 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25), 148 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02), 149 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a), 150 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01), 151 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62), 152 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02), 153 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c), 154 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a), 155 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14), 156 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04), 157 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20), 158 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16), 159 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 160 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a), 161 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36), 162 QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c), 163 }; 164 165 static const struct qmp_phy_init_tbl glymur_usb3_uniphy_pcs_tbl[] = { 166 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4), 167 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89), 168 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20), 169 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13), 170 QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21), 171 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55), 172 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 173 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 174 QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a), 175 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 176 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x30), 177 QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c), 178 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b), 179 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10), 180 }; 181 182 static const struct qmp_phy_init_tbl glymur_usb3_uniphy_tx_tbl[] = { 183 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00), 184 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00), 185 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 186 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 187 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5), 188 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11), 189 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x30), 190 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f), 191 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12), 192 QMP_PHY_INIT_CFG(QSERDES_V8_TX_PI_QEC_CTRL, 0x21), 193 }; 194 195 static const struct qmp_phy_init_tbl glymur_usb3_uniphy_rx_tbl[] = { 196 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x09), 197 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x04), 198 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 199 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 200 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 201 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 202 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99), 203 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08), 204 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08), 205 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00), 206 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a), 207 QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20), 208 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54), 209 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f), 210 QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x1b), 211 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 212 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 213 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 214 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07), 215 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 216 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 217 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c), 218 219 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04), 220 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 221 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0xbf), 222 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf), 223 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff), 224 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf), 225 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed), 226 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19), 227 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09), 228 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91), 229 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7), 230 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa), 231 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04), 232 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 233 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c), 234 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10), 235 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14), 236 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08), 237 }; 238 239 static const struct qmp_phy_init_tbl glymur_usb3_uniphy_pcs_usb_tbl[] = { 240 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 241 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), 242 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME, 0x75), 243 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40), 244 }; 245 246 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = { 247 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x1a), 248 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 249 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), 250 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), 251 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 252 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), 253 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), 254 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), 255 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), 256 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x06), 257 /* PLL and Loop filter settings */ 258 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x68), 259 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0xab), 260 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0xaa), 261 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x02), 262 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x09), 263 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), 264 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), 265 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0xa0), 266 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0xaa), 267 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x29), 268 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), 269 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), 270 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00), 271 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), 272 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a), 273 /* SSC settings */ 274 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x01), 275 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x7d), 276 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x01), 277 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x00), 278 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x00), 279 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0x0a), 280 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x05), 281 }; 282 283 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = { 284 QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 285 QMP_PHY_INIT_CFG(QSERDES_V2_TX_RCV_DETECT_LVL_2, 0x12), 286 QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x06), 287 }; 288 289 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = { 290 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x06), 291 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 292 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c), 293 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 294 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 295 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 296 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 297 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_CNTRL, 0x03), 298 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 299 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_ENABLES, 0x0c), 300 }; 301 302 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = { 303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 326 }; 327 328 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { 329 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x1a), 330 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 331 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), 332 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), 333 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 334 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), 335 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), 336 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), 337 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), 338 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x06), 339 /* PLL and Loop filter settings */ 340 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), 341 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), 342 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), 343 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x03), 344 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), 345 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), 346 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), 347 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 348 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x15), 349 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x34), 350 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), 351 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), 352 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00), 353 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), 354 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a), 355 /* SSC settings */ 356 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x01), 357 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), 358 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x01), 359 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x00), 360 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x00), 361 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0xde), 362 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x07), 363 }; 364 365 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { 366 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x06), 367 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 368 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 369 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 370 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 371 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 372 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_CNTRL, 0x03), 373 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 374 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_ENABLES, 0x0), 375 }; 376 377 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { 378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 399 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 401 }; 402 403 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { 404 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x14), 405 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 406 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), 407 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), 408 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), 409 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), 410 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), 411 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), 412 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x04), 413 /* PLL and Loop filter settings */ 414 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), 415 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), 416 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), 417 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x03), 418 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), 419 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), 420 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), 421 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 422 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_CTRL, 0x00), 423 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x15), 424 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x34), 425 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), 426 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), 427 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00), 428 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), 429 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a), 430 /* SSC settings */ 431 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x01), 432 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), 433 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x01), 434 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x00), 435 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x00), 436 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0xde), 437 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x07), 438 }; 439 440 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { 441 QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 442 QMP_PHY_INIT_CFG(QSERDES_V2_TX_RCV_DETECT_LVL_2, 0x12), 443 QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x06), 444 }; 445 446 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { 447 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 448 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x04), 449 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 450 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 451 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), 452 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 453 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 454 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_CNTRL, 0x03), 455 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_LVL, 0x18), 456 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 457 }; 458 459 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { 460 /* FLL settings */ 461 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03), 462 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02), 463 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09), 464 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42), 465 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85), 466 467 /* Lock Det settings */ 468 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1), 469 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f), 470 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47), 471 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08), 472 }; 473 474 static const struct qmp_phy_init_tbl qdu1000_usb3_uniphy_pcs_tbl[] = { 475 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xc4), 476 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x89), 477 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 478 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 479 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 489 }; 490 491 static const struct qmp_phy_init_tbl qdu1000_usb3_uniphy_pcs_usb_tbl[] = { 492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1, 0x6f), 495 }; 496 497 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { 498 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 499 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 500 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 501 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 502 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 534 }; 535 536 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { 537 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 538 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 539 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 540 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 541 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 542 }; 543 544 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { 545 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), 546 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), 547 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 548 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 549 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 550 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 551 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 552 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 553 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 554 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 555 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 556 }; 557 558 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 559 /* FLL settings */ 560 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 561 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 562 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 563 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 565 566 /* Lock Det settings */ 567 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 568 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 569 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 570 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 571 572 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), 576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), 577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), 578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), 579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 591 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 603 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 606 }; 607 608 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { 609 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 610 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 611 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 612 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 613 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 614 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 615 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 616 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 617 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 618 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 620 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 624 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 625 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 626 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 649 }; 650 651 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { 652 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 653 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), 654 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 655 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), 656 }; 657 658 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { 659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), 662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), 663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), 664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), 679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), 693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 695 }; 696 697 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { 698 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 699 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 700 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 701 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 702 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 703 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 704 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 705 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), 706 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 707 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 708 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 709 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 712 }; 713 714 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = { 715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 717 }; 718 719 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { 720 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 721 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 722 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), 723 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 724 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 725 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 726 }; 727 728 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { 729 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 730 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), 731 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 732 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 733 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 734 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 735 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 736 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 737 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 738 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 739 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 740 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 741 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 742 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 743 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 744 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 745 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 746 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 747 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 748 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), 749 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 750 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 751 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 752 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 753 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 754 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 755 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 756 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 757 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 758 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 759 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 760 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 761 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 762 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 763 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 764 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 765 }; 766 767 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { 768 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 769 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 770 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 771 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 772 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 773 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 774 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 775 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 776 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 777 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 778 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 779 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 780 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 781 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 782 }; 783 784 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = { 785 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 786 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 787 }; 788 789 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { 790 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 791 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 792 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), 793 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 794 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), 795 }; 796 797 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), 818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 824 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 825 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 826 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 827 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 828 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 829 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 830 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 831 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 832 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 833 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 834 }; 835 836 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { 837 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 838 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 839 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 840 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 841 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 842 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 843 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), 844 }; 845 846 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { 847 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 848 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 849 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 850 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 851 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 852 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 853 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 854 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 855 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 856 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 857 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 858 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 859 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 860 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 861 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 862 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 863 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 864 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 865 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 866 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 867 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 868 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 869 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 870 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 871 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 872 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 873 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 874 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 875 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 876 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 877 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 878 }; 879 880 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_serdes_tbl[] = { 881 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x9e), 882 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06), 883 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 884 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 885 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 886 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 887 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e), 888 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82), 889 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 890 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 891 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xea), 892 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 893 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 894 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 895 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 896 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7), 897 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 898 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7), 899 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 900 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x9e), 901 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06), 902 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 903 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 904 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 905 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12), 906 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34), 907 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 908 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 909 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea), 910 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02), 911 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 912 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 913 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 914 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 915 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 916 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 917 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 918 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 919 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 920 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 921 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 922 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 923 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 924 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 925 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 926 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 927 }; 928 929 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_tx_tbl[] = { 930 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 931 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 932 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 933 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 934 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 935 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 936 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 937 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 938 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 939 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x21), 940 }; 941 942 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_rx_tbl[] = { 943 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 944 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 945 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 946 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 947 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 948 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 949 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 950 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 951 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 952 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 953 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 954 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 955 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 956 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 957 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 958 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 959 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 960 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 961 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 962 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 963 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 964 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 965 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 966 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 967 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 968 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff), 969 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf), 970 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed), 971 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 972 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 973 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 974 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 975 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 976 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 977 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 978 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 979 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 980 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 981 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 982 }; 983 984 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_tbl[] = { 985 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 986 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 987 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 988 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 989 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 990 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0xaa), 991 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 992 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 993 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 994 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 995 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 996 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 997 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 998 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 999 }; 1000 1001 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_usb_tbl[] = { 1002 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1003 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1004 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1005 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1006 }; 1007 1008 static const struct qmp_phy_init_tbl qcs8300_usb3_uniphy_tx_tbl[] = { 1009 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1010 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0xf2), 1011 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1012 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1013 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1014 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1015 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1016 }; 1017 1018 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { 1019 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1020 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1021 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1022 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1023 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1024 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1025 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1026 }; 1027 1028 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { 1029 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1030 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1031 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1032 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1033 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1034 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1035 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1036 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1037 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1038 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1039 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1040 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1041 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1042 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1043 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1044 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1045 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1046 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1047 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1048 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1049 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1050 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1060 }; 1061 1062 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { 1063 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1064 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1065 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1066 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1067 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1068 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1069 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1070 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1071 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1072 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1073 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1074 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1075 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1076 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1077 }; 1078 1079 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = { 1080 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1081 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1082 }; 1083 1084 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = { 1085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1124 }; 1125 1126 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = { 1127 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1134 }; 1135 1136 static const struct qmp_phy_init_tbl qcs8300_usb3_uniphy_rx_tbl[] = { 1137 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xec), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x3f), 1141 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x3f), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x06), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x19), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1168 }; 1169 1170 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = { 1171 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1185 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1189 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1190 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1191 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1192 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1193 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1195 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1202 }; 1203 1204 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = { 1205 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1206 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1207 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1208 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1209 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1210 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1211 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1212 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1213 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1214 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1215 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1216 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1217 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1218 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1219 }; 1220 1221 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = { 1222 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1223 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1224 }; 1225 1226 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = { 1227 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1228 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89), 1229 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1230 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1231 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1232 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1233 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1234 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1235 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1236 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1237 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1238 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1239 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1240 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1241 }; 1242 1243 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = { 1244 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1245 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1246 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f), 1247 }; 1248 1249 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_serdes_tbl[] = { 1250 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 1251 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1252 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02), 1253 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16), 1254 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36), 1255 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04), 1256 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x16), 1257 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x41), 1258 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x41), 1259 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55), 1260 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x75), 1261 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01), 1262 QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01), 1263 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE1, 0x25), 1264 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE1, 0x02), 1265 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 1266 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 1267 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 1268 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 1269 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 1270 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1271 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02), 1272 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16), 1273 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36), 1274 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x08), 1275 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x1a), 1276 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41), 1277 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0x55), 1278 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0x75), 1279 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01), 1280 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE0, 0x25), 1281 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE0, 0x02), 1282 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a), 1283 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x01), 1284 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62), 1285 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02), 1286 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_BUF_ENABLE, 0x0a), 1287 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x1a), 1288 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_CFG, 0x14), 1289 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x04), 1290 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0x20), 1291 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16), 1292 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 1293 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 1294 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 1295 QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC, 0x0c), 1296 }; 1297 1298 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_tx_tbl[] = { 1299 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_TX, 0x00), 1300 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_RX, 0x00), 1301 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1302 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 1303 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0xf5), 1304 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x3f), 1305 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x3f), 1306 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x5f), 1307 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RCV_DETECT_LVL_2, 0x12), 1308 QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x21), 1309 }; 1310 1311 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_rx_tbl[] = { 1312 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x0a), 1313 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x06), 1314 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1315 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1316 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1317 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1318 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_PI_CONTROLS, 0x99), 1319 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08), 1320 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08), 1321 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN1, 0x00), 1322 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN2, 0x0a), 1323 QMP_PHY_INIT_CFG(QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1324 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL1, 0x54), 1325 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x0f), 1326 QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x13), 1327 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1328 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1329 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1330 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1331 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1332 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1333 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x04), 1334 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1335 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3f), 1336 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xbf), 1337 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xff), 1338 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xdf), 1339 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xed), 1340 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xdc), 1341 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x5c), 1342 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x9c), 1343 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1d), 1344 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x09), 1345 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_EN_TIMER, 0x04), 1346 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1347 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DCC_CTRL1, 0x0c), 1348 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VTH_CODE, 0x10), 1349 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_CTRL1, 0x14), 1350 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08), 1351 }; 1352 1353 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_tbl[] = { 1354 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1355 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG2, 0x89), 1356 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG3, 0x20), 1357 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG6, 0x13), 1358 QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x21), 1359 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0xaa), 1360 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1361 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1362 QMP_PHY_INIT_CFG(QPHY_V7_PCS_CDR_RESET_TIME, 0x0a), 1363 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1364 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1365 QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x0c), 1366 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG1, 0x4b), 1367 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG5, 0x10), 1368 }; 1369 1370 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_usb_tbl[] = { 1371 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1372 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1373 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1374 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1375 }; 1376 1377 struct qmp_usb_offsets { 1378 u16 serdes; 1379 u16 pcs; 1380 u16 pcs_misc; 1381 u16 pcs_usb; 1382 u16 tx; 1383 u16 rx; 1384 }; 1385 1386 /* struct qmp_phy_cfg - per-PHY initialization config */ 1387 struct qmp_phy_cfg { 1388 const struct qmp_usb_offsets *offsets; 1389 1390 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1391 const struct qmp_phy_init_tbl *serdes_tbl; 1392 int serdes_tbl_num; 1393 const struct qmp_phy_init_tbl *tx_tbl; 1394 int tx_tbl_num; 1395 const struct qmp_phy_init_tbl *rx_tbl; 1396 int rx_tbl_num; 1397 const struct qmp_phy_init_tbl *pcs_tbl; 1398 int pcs_tbl_num; 1399 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1400 int pcs_usb_tbl_num; 1401 1402 /* regulators to be requested */ 1403 const struct regulator_bulk_data *vreg_list; 1404 int num_vregs; 1405 1406 /* array of registers with different offsets */ 1407 const unsigned int *regs; 1408 1409 /* true, if PHY needs delay after POWER_DOWN */ 1410 bool has_pwrdn_delay; 1411 1412 /* Offset from PCS to PCS_USB region */ 1413 unsigned int pcs_usb_offset; 1414 }; 1415 1416 struct qmp_usb { 1417 struct device *dev; 1418 1419 const struct qmp_phy_cfg *cfg; 1420 1421 void __iomem *serdes; 1422 void __iomem *pcs; 1423 void __iomem *pcs_misc; 1424 void __iomem *pcs_usb; 1425 void __iomem *tx; 1426 void __iomem *rx; 1427 1428 struct clk *pipe_clk; 1429 struct clk_bulk_data *clks; 1430 int num_clks; 1431 int num_resets; 1432 struct reset_control_bulk_data *resets; 1433 struct regulator_bulk_data *vregs; 1434 1435 enum phy_mode mode; 1436 1437 bool phy_initialized; 1438 1439 struct phy *phy; 1440 1441 struct clk_fixed_rate pipe_clk_fixed; 1442 }; 1443 1444 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1445 { 1446 u32 reg; 1447 1448 reg = readl(base + offset); 1449 reg |= val; 1450 writel(reg, base + offset); 1451 1452 /* ensure that above write is through */ 1453 readl(base + offset); 1454 } 1455 1456 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1457 { 1458 u32 reg; 1459 1460 reg = readl(base + offset); 1461 reg &= ~val; 1462 writel(reg, base + offset); 1463 1464 /* ensure that above write is through */ 1465 readl(base + offset); 1466 } 1467 1468 /* list of clocks required by phy */ 1469 static const char * const qmp_usb_phy_clk_l[] = { 1470 "aux", "cfg_ahb", "ref", "com_aux", 1471 }; 1472 1473 /* list of resets */ 1474 static const char * const usb3phy_legacy_reset_l[] = { 1475 "phy", "common", 1476 }; 1477 1478 static const char * const usb3phy_reset_l[] = { 1479 "phy_phy", "phy", 1480 }; 1481 1482 /* list of regulators */ 1483 static const struct regulator_bulk_data qmp_phy_vreg_l[] = { 1484 { .supply = "vdda-phy", .init_load_uA = 21800, }, 1485 { .supply = "vdda-pll", .init_load_uA = 36000, }, 1486 }; 1487 1488 static const struct qmp_usb_offsets qmp_usb_offsets_v3 = { 1489 .serdes = 0, 1490 .pcs = 0x800, 1491 .pcs_misc = 0x600, 1492 .tx = 0x200, 1493 .rx = 0x400, 1494 }; 1495 1496 static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = { 1497 .serdes = 0, 1498 .pcs = 0x800, 1499 .pcs_usb = 0x800, 1500 .tx = 0x200, 1501 .rx = 0x400, 1502 }; 1503 1504 static const struct qmp_usb_offsets qmp_usb_offsets_v3_msm8996 = { 1505 .serdes = 0, 1506 .pcs = 0x600, 1507 .tx = 0x200, 1508 .rx = 0x400, 1509 }; 1510 1511 static const struct qmp_usb_offsets qmp_usb_offsets_v4 = { 1512 .serdes = 0, 1513 .pcs = 0x0800, 1514 .pcs_usb = 0x0e00, 1515 .tx = 0x0200, 1516 .rx = 0x0400, 1517 }; 1518 1519 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { 1520 .serdes = 0, 1521 .pcs = 0x0200, 1522 .pcs_usb = 0x1200, 1523 .tx = 0x0e00, 1524 .rx = 0x1000, 1525 }; 1526 1527 static const struct qmp_usb_offsets qmp_usb_offsets_v6 = { 1528 .serdes = 0, 1529 .pcs = 0x0200, 1530 .pcs_usb = 0x1200, 1531 .tx = 0x0e00, 1532 .rx = 0x1000, 1533 }; 1534 1535 static const struct qmp_usb_offsets qmp_usb_offsets_v7 = { 1536 .serdes = 0, 1537 .pcs = 0x0200, 1538 .pcs_usb = 0x1200, 1539 .tx = 0x0e00, 1540 .rx = 0x1000, 1541 }; 1542 1543 static const struct qmp_usb_offsets qmp_usb_offsets_v8 = { 1544 .serdes = 0, 1545 .pcs = 0x0400, 1546 .pcs_usb = 0x1200, 1547 .tx = 0x0e00, 1548 .rx = 0x1000, 1549 }; 1550 1551 static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = { 1552 .offsets = &qmp_usb_offsets_v3, 1553 1554 .serdes_tbl = ipq9574_usb3_serdes_tbl, 1555 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl), 1556 .tx_tbl = msm8996_usb3_tx_tbl, 1557 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1558 .rx_tbl = ipq8074_usb3_rx_tbl, 1559 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), 1560 .pcs_tbl = ipq8074_usb3_pcs_tbl, 1561 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), 1562 .vreg_list = qmp_phy_vreg_l, 1563 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1564 .regs = qmp_v3_usb3phy_regs_layout, 1565 }; 1566 1567 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { 1568 .offsets = &qmp_usb_offsets_v3, 1569 1570 .serdes_tbl = ipq8074_usb3_serdes_tbl, 1571 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), 1572 .tx_tbl = msm8996_usb3_tx_tbl, 1573 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1574 .rx_tbl = ipq8074_usb3_rx_tbl, 1575 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), 1576 .pcs_tbl = ipq8074_usb3_pcs_tbl, 1577 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), 1578 .vreg_list = qmp_phy_vreg_l, 1579 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1580 .regs = qmp_v3_usb3phy_regs_layout, 1581 }; 1582 1583 static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { 1584 .offsets = &qmp_usb_offsets_ipq9574, 1585 1586 .serdes_tbl = ipq9574_usb3_serdes_tbl, 1587 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl), 1588 .tx_tbl = ipq9574_usb3_tx_tbl, 1589 .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl), 1590 .rx_tbl = ipq9574_usb3_rx_tbl, 1591 .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl), 1592 .pcs_tbl = ipq9574_usb3_pcs_tbl, 1593 .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl), 1594 .vreg_list = qmp_phy_vreg_l, 1595 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1596 .regs = qmp_v3_usb3phy_regs_layout, 1597 }; 1598 1599 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 1600 .offsets = &qmp_usb_offsets_v3_msm8996, 1601 1602 .serdes_tbl = msm8996_usb3_serdes_tbl, 1603 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), 1604 .tx_tbl = msm8996_usb3_tx_tbl, 1605 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1606 .rx_tbl = msm8996_usb3_rx_tbl, 1607 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), 1608 .pcs_tbl = msm8996_usb3_pcs_tbl, 1609 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), 1610 .vreg_list = qmp_phy_vreg_l, 1611 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1612 .regs = qmp_v2_usb3phy_regs_layout, 1613 }; 1614 1615 static const struct qmp_phy_cfg qdu1000_usb3_uniphy_cfg = { 1616 .offsets = &qmp_usb_offsets_v5, 1617 1618 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1619 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1620 .tx_tbl = sm8350_usb3_uniphy_tx_tbl, 1621 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), 1622 .rx_tbl = sm8350_usb3_uniphy_rx_tbl, 1623 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), 1624 .pcs_tbl = qdu1000_usb3_uniphy_pcs_tbl, 1625 .pcs_tbl_num = ARRAY_SIZE(qdu1000_usb3_uniphy_pcs_tbl), 1626 .pcs_usb_tbl = qdu1000_usb3_uniphy_pcs_usb_tbl, 1627 .pcs_usb_tbl_num = ARRAY_SIZE(qdu1000_usb3_uniphy_pcs_usb_tbl), 1628 .vreg_list = qmp_phy_vreg_l, 1629 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1630 .regs = qmp_v4_usb3phy_regs_layout, 1631 .pcs_usb_offset = 0x1000, 1632 1633 .has_pwrdn_delay = true, 1634 }; 1635 1636 static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = { 1637 .offsets = &qmp_usb_offsets_v5, 1638 1639 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1640 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1641 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, 1642 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), 1643 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, 1644 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1645 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl, 1646 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl), 1647 .pcs_usb_tbl = sa8775p_usb3_uniphy_pcs_usb_tbl, 1648 .pcs_usb_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl), 1649 .vreg_list = qmp_phy_vreg_l, 1650 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1651 .regs = qmp_v5_usb3phy_regs_layout, 1652 }; 1653 1654 static const struct qmp_phy_cfg qcs8300_usb3_uniphy_cfg = { 1655 .offsets = &qmp_usb_offsets_v5, 1656 1657 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1658 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1659 .tx_tbl = qcs8300_usb3_uniphy_tx_tbl, 1660 .tx_tbl_num = ARRAY_SIZE(qcs8300_usb3_uniphy_tx_tbl), 1661 .rx_tbl = qcs8300_usb3_uniphy_rx_tbl, 1662 .rx_tbl_num = ARRAY_SIZE(qcs8300_usb3_uniphy_rx_tbl), 1663 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl, 1664 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl), 1665 .pcs_usb_tbl = sa8775p_usb3_uniphy_pcs_usb_tbl, 1666 .pcs_usb_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl), 1667 .vreg_list = qmp_phy_vreg_l, 1668 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1669 .regs = qmp_v5_usb3phy_regs_layout, 1670 }; 1671 1672 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { 1673 .offsets = &qmp_usb_offsets_v5, 1674 1675 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1676 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1677 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, 1678 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), 1679 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, 1680 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1681 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl, 1682 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl), 1683 .pcs_usb_tbl = sc8280xp_usb3_uniphy_pcs_usb_tbl, 1684 .pcs_usb_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl), 1685 .vreg_list = qmp_phy_vreg_l, 1686 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1687 .regs = qmp_v5_usb3phy_regs_layout, 1688 }; 1689 1690 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 1691 .offsets = &qmp_usb_offsets_v3, 1692 1693 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, 1694 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), 1695 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, 1696 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), 1697 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, 1698 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), 1699 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, 1700 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), 1701 .vreg_list = qmp_phy_vreg_l, 1702 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1703 .regs = qmp_v3_usb3phy_regs_layout, 1704 1705 .has_pwrdn_delay = true, 1706 }; 1707 1708 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { 1709 .offsets = &qmp_usb_offsets_v4, 1710 1711 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1712 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1713 .tx_tbl = sm8150_usb3_uniphy_tx_tbl, 1714 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), 1715 .rx_tbl = sm8150_usb3_uniphy_rx_tbl, 1716 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), 1717 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, 1718 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), 1719 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl, 1720 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl), 1721 .vreg_list = qmp_phy_vreg_l, 1722 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1723 .regs = qmp_v4_usb3phy_regs_layout, 1724 .pcs_usb_offset = 0x600, 1725 1726 .has_pwrdn_delay = true, 1727 }; 1728 1729 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { 1730 .offsets = &qmp_usb_offsets_v4, 1731 1732 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1733 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1734 .tx_tbl = sm8250_usb3_uniphy_tx_tbl, 1735 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), 1736 .rx_tbl = sm8250_usb3_uniphy_rx_tbl, 1737 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), 1738 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1739 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1740 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1741 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1742 .vreg_list = qmp_phy_vreg_l, 1743 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1744 .regs = qmp_v4_usb3phy_regs_layout, 1745 .pcs_usb_offset = 0x600, 1746 1747 .has_pwrdn_delay = true, 1748 }; 1749 1750 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { 1751 .offsets = &qmp_usb_offsets_v4, 1752 1753 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1754 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1755 .tx_tbl = sdx55_usb3_uniphy_tx_tbl, 1756 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), 1757 .rx_tbl = sdx55_usb3_uniphy_rx_tbl, 1758 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), 1759 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1760 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1761 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1762 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1763 .vreg_list = qmp_phy_vreg_l, 1764 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1765 .regs = qmp_v4_usb3phy_regs_layout, 1766 .pcs_usb_offset = 0x600, 1767 1768 .has_pwrdn_delay = true, 1769 }; 1770 1771 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { 1772 .offsets = &qmp_usb_offsets_v5, 1773 1774 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1775 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1776 .tx_tbl = sdx65_usb3_uniphy_tx_tbl, 1777 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), 1778 .rx_tbl = sdx65_usb3_uniphy_rx_tbl, 1779 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), 1780 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1781 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1782 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1783 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1784 .vreg_list = qmp_phy_vreg_l, 1785 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1786 .regs = qmp_v5_usb3phy_regs_layout, 1787 .pcs_usb_offset = 0x1000, 1788 1789 .has_pwrdn_delay = true, 1790 }; 1791 1792 static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = { 1793 .offsets = &qmp_usb_offsets_v6, 1794 1795 .serdes_tbl = sdx75_usb3_uniphy_serdes_tbl, 1796 .serdes_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl), 1797 .tx_tbl = sdx75_usb3_uniphy_tx_tbl, 1798 .tx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl), 1799 .rx_tbl = sdx75_usb3_uniphy_rx_tbl, 1800 .rx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl), 1801 .pcs_tbl = sdx75_usb3_uniphy_pcs_tbl, 1802 .pcs_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl), 1803 .pcs_usb_tbl = sdx75_usb3_uniphy_pcs_usb_tbl, 1804 .pcs_usb_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl), 1805 .vreg_list = qmp_phy_vreg_l, 1806 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1807 .regs = qmp_v6_usb3phy_regs_layout, 1808 .pcs_usb_offset = 0x1000, 1809 1810 .has_pwrdn_delay = true, 1811 }; 1812 1813 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { 1814 .offsets = &qmp_usb_offsets_v5, 1815 1816 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1817 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1818 .tx_tbl = sm8350_usb3_uniphy_tx_tbl, 1819 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), 1820 .rx_tbl = sm8350_usb3_uniphy_rx_tbl, 1821 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), 1822 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1823 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1824 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1825 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1826 .vreg_list = qmp_phy_vreg_l, 1827 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1828 .regs = qmp_v5_usb3phy_regs_layout, 1829 .pcs_usb_offset = 0x1000, 1830 1831 .has_pwrdn_delay = true, 1832 }; 1833 1834 static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = { 1835 .offsets = &qmp_usb_offsets_v7, 1836 1837 .serdes_tbl = x1e80100_usb3_uniphy_serdes_tbl, 1838 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_serdes_tbl), 1839 .tx_tbl = x1e80100_usb3_uniphy_tx_tbl, 1840 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_tx_tbl), 1841 .rx_tbl = x1e80100_usb3_uniphy_rx_tbl, 1842 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_rx_tbl), 1843 .pcs_tbl = x1e80100_usb3_uniphy_pcs_tbl, 1844 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_tbl), 1845 .pcs_usb_tbl = x1e80100_usb3_uniphy_pcs_usb_tbl, 1846 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_usb_tbl), 1847 .vreg_list = qmp_phy_vreg_l, 1848 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1849 .regs = qmp_v7_usb3phy_regs_layout, 1850 }; 1851 1852 static const struct qmp_phy_cfg glymur_usb3_uniphy_cfg = { 1853 .offsets = &qmp_usb_offsets_v8, 1854 1855 .serdes_tbl = glymur_usb3_uniphy_serdes_tbl, 1856 .serdes_tbl_num = ARRAY_SIZE(glymur_usb3_uniphy_serdes_tbl), 1857 .tx_tbl = glymur_usb3_uniphy_tx_tbl, 1858 .tx_tbl_num = ARRAY_SIZE(glymur_usb3_uniphy_tx_tbl), 1859 .rx_tbl = glymur_usb3_uniphy_rx_tbl, 1860 .rx_tbl_num = ARRAY_SIZE(glymur_usb3_uniphy_rx_tbl), 1861 .pcs_tbl = glymur_usb3_uniphy_pcs_tbl, 1862 .pcs_tbl_num = ARRAY_SIZE(glymur_usb3_uniphy_pcs_tbl), 1863 .pcs_usb_tbl = glymur_usb3_uniphy_pcs_usb_tbl, 1864 .pcs_usb_tbl_num = ARRAY_SIZE(glymur_usb3_uniphy_pcs_usb_tbl), 1865 .vreg_list = qmp_phy_vreg_l, 1866 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1867 .regs = qmp_v7_usb3phy_regs_layout, 1868 }; 1869 1870 static int qmp_usb_serdes_init(struct qmp_usb *qmp) 1871 { 1872 const struct qmp_phy_cfg *cfg = qmp->cfg; 1873 void __iomem *serdes = qmp->serdes; 1874 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1875 int serdes_tbl_num = cfg->serdes_tbl_num; 1876 1877 qmp_configure(qmp->dev, serdes, serdes_tbl, serdes_tbl_num); 1878 1879 return 0; 1880 } 1881 1882 static int qmp_usb_init(struct phy *phy) 1883 { 1884 struct qmp_usb *qmp = phy_get_drvdata(phy); 1885 const struct qmp_phy_cfg *cfg = qmp->cfg; 1886 void __iomem *pcs = qmp->pcs; 1887 int ret; 1888 1889 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1890 if (ret) { 1891 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1892 return ret; 1893 } 1894 1895 ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets); 1896 if (ret) { 1897 dev_err(qmp->dev, "reset assert failed\n"); 1898 goto err_disable_regulators; 1899 } 1900 1901 ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets); 1902 if (ret) { 1903 dev_err(qmp->dev, "reset deassert failed\n"); 1904 goto err_disable_regulators; 1905 } 1906 1907 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 1908 if (ret) 1909 goto err_assert_reset; 1910 1911 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1912 1913 return 0; 1914 1915 err_assert_reset: 1916 reset_control_bulk_assert(qmp->num_resets, qmp->resets); 1917 err_disable_regulators: 1918 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1919 1920 return ret; 1921 } 1922 1923 static int qmp_usb_exit(struct phy *phy) 1924 { 1925 struct qmp_usb *qmp = phy_get_drvdata(phy); 1926 const struct qmp_phy_cfg *cfg = qmp->cfg; 1927 1928 reset_control_bulk_assert(qmp->num_resets, qmp->resets); 1929 1930 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 1931 1932 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1933 1934 return 0; 1935 } 1936 1937 static int qmp_usb_power_on(struct phy *phy) 1938 { 1939 struct qmp_usb *qmp = phy_get_drvdata(phy); 1940 const struct qmp_phy_cfg *cfg = qmp->cfg; 1941 void __iomem *tx = qmp->tx; 1942 void __iomem *rx = qmp->rx; 1943 void __iomem *pcs = qmp->pcs; 1944 void __iomem *pcs_usb = qmp->pcs_usb; 1945 void __iomem *status; 1946 unsigned int val; 1947 int ret; 1948 1949 qmp_usb_serdes_init(qmp); 1950 1951 ret = clk_prepare_enable(qmp->pipe_clk); 1952 if (ret) { 1953 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1954 return ret; 1955 } 1956 1957 /* Tx, Rx, and PCS configurations */ 1958 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 1959 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 1960 1961 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1962 1963 if (pcs_usb) 1964 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num); 1965 1966 if (cfg->has_pwrdn_delay) 1967 usleep_range(10, 20); 1968 1969 /* Pull PHY out of reset state */ 1970 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1971 1972 /* start SerDes and Phy-Coding-Sublayer */ 1973 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 1974 1975 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 1976 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 1977 PHY_INIT_COMPLETE_TIMEOUT); 1978 if (ret) { 1979 dev_err(qmp->dev, "phy initialization timed-out\n"); 1980 goto err_disable_pipe_clk; 1981 } 1982 1983 return 0; 1984 1985 err_disable_pipe_clk: 1986 clk_disable_unprepare(qmp->pipe_clk); 1987 1988 return ret; 1989 } 1990 1991 static int qmp_usb_power_off(struct phy *phy) 1992 { 1993 struct qmp_usb *qmp = phy_get_drvdata(phy); 1994 const struct qmp_phy_cfg *cfg = qmp->cfg; 1995 1996 clk_disable_unprepare(qmp->pipe_clk); 1997 1998 /* PHY reset */ 1999 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2000 2001 /* stop SerDes and Phy-Coding-Sublayer */ 2002 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2003 SERDES_START | PCS_START); 2004 2005 /* Put PHY into POWER DOWN state: active low */ 2006 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2007 SW_PWRDN); 2008 2009 return 0; 2010 } 2011 2012 static int qmp_usb_enable(struct phy *phy) 2013 { 2014 struct qmp_usb *qmp = phy_get_drvdata(phy); 2015 int ret; 2016 2017 ret = qmp_usb_init(phy); 2018 if (ret) 2019 return ret; 2020 2021 ret = qmp_usb_power_on(phy); 2022 if (ret) 2023 qmp_usb_exit(phy); 2024 else 2025 qmp->phy_initialized = true; 2026 2027 return ret; 2028 } 2029 2030 static int qmp_usb_disable(struct phy *phy) 2031 { 2032 struct qmp_usb *qmp = phy_get_drvdata(phy); 2033 int ret; 2034 2035 qmp->phy_initialized = false; 2036 2037 ret = qmp_usb_power_off(phy); 2038 if (ret) 2039 return ret; 2040 return qmp_usb_exit(phy); 2041 } 2042 2043 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2044 { 2045 struct qmp_usb *qmp = phy_get_drvdata(phy); 2046 2047 qmp->mode = mode; 2048 2049 return 0; 2050 } 2051 2052 static const struct phy_ops qmp_usb_phy_ops = { 2053 .init = qmp_usb_enable, 2054 .exit = qmp_usb_disable, 2055 .set_mode = qmp_usb_set_mode, 2056 .owner = THIS_MODULE, 2057 }; 2058 2059 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp) 2060 { 2061 const struct qmp_phy_cfg *cfg = qmp->cfg; 2062 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2063 void __iomem *pcs_misc = qmp->pcs_misc; 2064 u32 intr_mask; 2065 2066 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2067 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2068 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2069 else 2070 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2071 2072 /* Clear any pending interrupts status */ 2073 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2074 /* Writing 1 followed by 0 clears the interrupt */ 2075 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2076 2077 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2078 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2079 2080 /* Enable required PHY autonomous mode interrupts */ 2081 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2082 2083 /* Enable i/o clamp_n for autonomous mode */ 2084 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE]) 2085 qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN); 2086 } 2087 2088 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp) 2089 { 2090 const struct qmp_phy_cfg *cfg = qmp->cfg; 2091 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2092 void __iomem *pcs_misc = qmp->pcs_misc; 2093 2094 /* Disable i/o clamp_n on resume for normal mode */ 2095 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE]) 2096 qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN); 2097 2098 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2099 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2100 2101 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2102 /* Writing 1 followed by 0 clears the interrupt */ 2103 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2104 } 2105 2106 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev) 2107 { 2108 struct qmp_usb *qmp = dev_get_drvdata(dev); 2109 2110 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2111 2112 if (!qmp->phy_initialized) { 2113 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2114 return 0; 2115 } 2116 2117 qmp_usb_enable_autonomous_mode(qmp); 2118 2119 clk_disable_unprepare(qmp->pipe_clk); 2120 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2121 2122 return 0; 2123 } 2124 2125 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev) 2126 { 2127 struct qmp_usb *qmp = dev_get_drvdata(dev); 2128 int ret = 0; 2129 2130 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2131 2132 if (!qmp->phy_initialized) { 2133 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2134 return 0; 2135 } 2136 2137 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2138 if (ret) 2139 return ret; 2140 2141 ret = clk_prepare_enable(qmp->pipe_clk); 2142 if (ret) { 2143 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2144 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2145 return ret; 2146 } 2147 2148 qmp_usb_disable_autonomous_mode(qmp); 2149 2150 return 0; 2151 } 2152 2153 static const struct dev_pm_ops qmp_usb_pm_ops = { 2154 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend, 2155 qmp_usb_runtime_resume, NULL) 2156 }; 2157 2158 static int qmp_usb_reset_init(struct qmp_usb *qmp, 2159 const char *const *reset_list, 2160 int num_resets) 2161 { 2162 struct device *dev = qmp->dev; 2163 int i; 2164 int ret; 2165 2166 qmp->resets = devm_kcalloc(dev, num_resets, 2167 sizeof(*qmp->resets), GFP_KERNEL); 2168 if (!qmp->resets) 2169 return -ENOMEM; 2170 2171 for (i = 0; i < num_resets; i++) 2172 qmp->resets[i].id = reset_list[i]; 2173 2174 qmp->num_resets = num_resets; 2175 2176 ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets); 2177 if (ret) 2178 return dev_err_probe(dev, ret, "failed to get resets\n"); 2179 2180 return 0; 2181 } 2182 2183 static int qmp_usb_clk_init(struct qmp_usb *qmp) 2184 { 2185 struct device *dev = qmp->dev; 2186 int num = ARRAY_SIZE(qmp_usb_phy_clk_l); 2187 int i; 2188 2189 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2190 if (!qmp->clks) 2191 return -ENOMEM; 2192 2193 for (i = 0; i < num; i++) 2194 qmp->clks[i].id = qmp_usb_phy_clk_l[i]; 2195 2196 qmp->num_clks = num; 2197 2198 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 2199 } 2200 2201 static void phy_clk_release_provider(void *res) 2202 { 2203 of_clk_del_provider(res); 2204 } 2205 2206 /* 2207 * Register a fixed rate pipe clock. 2208 * 2209 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2210 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2211 * by the PHY driver for its operations. 2212 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2213 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2214 * Below picture shows this relationship. 2215 * 2216 * +---------------+ 2217 * | PHY block |<<---------------------------------------+ 2218 * | | | 2219 * | +-------+ | +-----+ | 2220 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2221 * clk | +-------+ | +-----+ 2222 * +---------------+ 2223 */ 2224 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np) 2225 { 2226 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2227 struct clk_init_data init = { }; 2228 int ret; 2229 2230 ret = of_property_read_string(np, "clock-output-names", &init.name); 2231 if (ret) { 2232 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2233 return ret; 2234 } 2235 2236 init.ops = &clk_fixed_rate_ops; 2237 2238 /* controllers using QMP phys use 125MHz pipe clock interface */ 2239 fixed->fixed_rate = 125000000; 2240 fixed->hw.init = &init; 2241 2242 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2243 if (ret) 2244 return ret; 2245 2246 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2247 if (ret) 2248 return ret; 2249 2250 /* 2251 * Roll a devm action because the clock provider is the child node, but 2252 * the child node is not actually a device. 2253 */ 2254 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2255 } 2256 2257 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np, 2258 int index, bool exclusive) 2259 { 2260 struct resource res; 2261 void __iomem *mem; 2262 2263 if (!exclusive) { 2264 if (of_address_to_resource(np, index, &res)) 2265 return IOMEM_ERR_PTR(-EINVAL); 2266 2267 mem = devm_ioremap(dev, res.start, resource_size(&res)); 2268 if (!mem) 2269 return IOMEM_ERR_PTR(-ENOMEM); 2270 return mem; 2271 } 2272 2273 return devm_of_iomap(dev, np, index, NULL); 2274 } 2275 2276 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np) 2277 { 2278 struct platform_device *pdev = to_platform_device(qmp->dev); 2279 const struct qmp_phy_cfg *cfg = qmp->cfg; 2280 struct device *dev = qmp->dev; 2281 bool exclusive = true; 2282 int ret; 2283 2284 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2285 if (IS_ERR(qmp->serdes)) 2286 return PTR_ERR(qmp->serdes); 2287 2288 /* 2289 * FIXME: These bindings should be fixed to not rely on overlapping 2290 * mappings for PCS. 2291 */ 2292 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy")) 2293 exclusive = false; 2294 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy")) 2295 exclusive = false; 2296 2297 /* 2298 * Get memory resources for the PHY: 2299 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2300 * For single lane PHYs: pcs_misc (optional) -> 3. 2301 */ 2302 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2303 if (IS_ERR(qmp->tx)) 2304 return PTR_ERR(qmp->tx); 2305 2306 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2307 if (IS_ERR(qmp->rx)) 2308 return PTR_ERR(qmp->rx); 2309 2310 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive); 2311 if (IS_ERR(qmp->pcs)) 2312 return PTR_ERR(qmp->pcs); 2313 2314 if (cfg->pcs_usb_offset) 2315 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 2316 2317 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2318 2319 if (IS_ERR(qmp->pcs_misc)) { 2320 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2321 qmp->pcs_misc = NULL; 2322 } 2323 2324 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2325 if (IS_ERR(qmp->pipe_clk)) { 2326 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2327 "failed to get pipe clock\n"); 2328 } 2329 2330 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 2331 if (ret < 0) 2332 return ret; 2333 2334 qmp->num_clks = ret; 2335 2336 ret = qmp_usb_reset_init(qmp, usb3phy_legacy_reset_l, 2337 ARRAY_SIZE(usb3phy_legacy_reset_l)); 2338 if (ret) 2339 return ret; 2340 2341 return 0; 2342 } 2343 2344 static int qmp_usb_parse_dt(struct qmp_usb *qmp) 2345 { 2346 struct platform_device *pdev = to_platform_device(qmp->dev); 2347 const struct qmp_phy_cfg *cfg = qmp->cfg; 2348 const struct qmp_usb_offsets *offs = cfg->offsets; 2349 struct device *dev = qmp->dev; 2350 void __iomem *base; 2351 int ret; 2352 2353 if (!offs) 2354 return -EINVAL; 2355 2356 base = devm_platform_ioremap_resource(pdev, 0); 2357 if (IS_ERR(base)) 2358 return PTR_ERR(base); 2359 2360 qmp->serdes = base + offs->serdes; 2361 qmp->pcs = base + offs->pcs; 2362 if (offs->pcs_usb) 2363 qmp->pcs_usb = base + offs->pcs_usb; 2364 if (offs->pcs_misc) 2365 qmp->pcs_misc = base + offs->pcs_misc; 2366 qmp->tx = base + offs->tx; 2367 qmp->rx = base + offs->rx; 2368 2369 ret = qmp_usb_clk_init(qmp); 2370 if (ret) 2371 return ret; 2372 2373 qmp->pipe_clk = devm_clk_get(dev, "pipe"); 2374 if (IS_ERR(qmp->pipe_clk)) { 2375 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2376 "failed to get pipe clock\n"); 2377 } 2378 2379 ret = qmp_usb_reset_init(qmp, usb3phy_reset_l, 2380 ARRAY_SIZE(usb3phy_reset_l)); 2381 if (ret) 2382 return ret; 2383 2384 return 0; 2385 } 2386 2387 static int qmp_usb_probe(struct platform_device *pdev) 2388 { 2389 struct device *dev = &pdev->dev; 2390 struct phy_provider *phy_provider; 2391 struct device_node *np; 2392 struct qmp_usb *qmp; 2393 int ret; 2394 2395 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2396 if (!qmp) 2397 return -ENOMEM; 2398 2399 qmp->dev = dev; 2400 dev_set_drvdata(dev, qmp); 2401 2402 qmp->cfg = of_device_get_match_data(dev); 2403 if (!qmp->cfg) 2404 return -EINVAL; 2405 2406 ret = devm_regulator_bulk_get_const(dev, qmp->cfg->num_vregs, 2407 qmp->cfg->vreg_list, &qmp->vregs); 2408 if (ret) 2409 return ret; 2410 2411 /* Check for legacy binding with child node. */ 2412 np = of_get_next_available_child(dev->of_node, NULL); 2413 if (np) { 2414 ret = qmp_usb_parse_dt_legacy(qmp, np); 2415 } else { 2416 np = of_node_get(dev->of_node); 2417 ret = qmp_usb_parse_dt(qmp); 2418 } 2419 if (ret) 2420 goto err_node_put; 2421 2422 /* 2423 * Enable runtime PM before creating the PHY, phy_create() only enables 2424 * it on the PHY device if already enabled on the parent. Hold a usage 2425 * reference so callbacks cannot run before qmp->phy is assigned. 2426 */ 2427 pm_runtime_get_noresume(dev); 2428 pm_runtime_set_active(dev); 2429 ret = devm_pm_runtime_enable(dev); 2430 if (ret) 2431 goto err_pm_put; 2432 /* 2433 * Prevent runtime pm from being ON by default. Users can enable 2434 * it using power/control in sysfs. 2435 */ 2436 pm_runtime_forbid(dev); 2437 2438 ret = phy_pipe_clk_register(qmp, np); 2439 if (ret) 2440 goto err_pm_put; 2441 2442 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops); 2443 if (IS_ERR(qmp->phy)) { 2444 ret = PTR_ERR(qmp->phy); 2445 dev_err(dev, "failed to create PHY: %d\n", ret); 2446 goto err_pm_put; 2447 } 2448 2449 phy_set_drvdata(qmp->phy, qmp); 2450 2451 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2452 if (IS_ERR(phy_provider)) { 2453 ret = PTR_ERR(phy_provider); 2454 goto err_pm_put; 2455 } 2456 2457 of_node_put(np); 2458 2459 pm_runtime_put(dev); 2460 2461 return 0; 2462 2463 err_pm_put: 2464 pm_runtime_put_noidle(dev); 2465 err_node_put: 2466 of_node_put(np); 2467 return ret; 2468 } 2469 2470 static const struct of_device_id qmp_usb_of_match_table[] = { 2471 { 2472 .compatible = "qcom,glymur-qmp-usb3-uni-phy", 2473 .data = &glymur_usb3_uniphy_cfg, 2474 }, { 2475 .compatible = "qcom,ipq5424-qmp-usb3-phy", 2476 .data = &ipq9574_usb3phy_cfg, 2477 }, { 2478 .compatible = "qcom,ipq6018-qmp-usb3-phy", 2479 .data = &ipq6018_usb3phy_cfg, 2480 }, { 2481 .compatible = "qcom,ipq8074-qmp-usb3-phy", 2482 .data = &ipq8074_usb3phy_cfg, 2483 }, { 2484 .compatible = "qcom,ipq9574-qmp-usb3-phy", 2485 .data = &ipq9574_usb3phy_cfg, 2486 }, { 2487 .compatible = "qcom,msm8996-qmp-usb3-phy", 2488 .data = &msm8996_usb3phy_cfg, 2489 }, { 2490 .compatible = "qcom,qcs8300-qmp-usb3-uni-phy", 2491 .data = &qcs8300_usb3_uniphy_cfg, 2492 }, { 2493 .compatible = "qcom,qdu1000-qmp-usb3-uni-phy", 2494 .data = &qdu1000_usb3_uniphy_cfg, 2495 }, { 2496 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy", 2497 .data = &sa8775p_usb3_uniphy_cfg, 2498 }, { 2499 .compatible = "qcom,sc8180x-qmp-usb3-uni-phy", 2500 .data = &sm8150_usb3_uniphy_cfg, 2501 }, { 2502 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy", 2503 .data = &sc8280xp_usb3_uniphy_cfg, 2504 }, { 2505 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 2506 .data = &qmp_v3_usb3_uniphy_cfg, 2507 }, { 2508 .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 2509 .data = &sdx55_usb3_uniphy_cfg, 2510 }, { 2511 .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 2512 .data = &sdx65_usb3_uniphy_cfg, 2513 }, { 2514 .compatible = "qcom,sdx75-qmp-usb3-uni-phy", 2515 .data = &sdx75_usb3_uniphy_cfg, 2516 }, { 2517 .compatible = "qcom,sm8150-qmp-usb3-uni-phy", 2518 .data = &sm8150_usb3_uniphy_cfg, 2519 }, { 2520 .compatible = "qcom,sm8250-qmp-usb3-uni-phy", 2521 .data = &sm8250_usb3_uniphy_cfg, 2522 }, { 2523 .compatible = "qcom,sm8350-qmp-usb3-uni-phy", 2524 .data = &sm8350_usb3_uniphy_cfg, 2525 }, { 2526 .compatible = "qcom,x1e80100-qmp-usb3-uni-phy", 2527 .data = &x1e80100_usb3_uniphy_cfg, 2528 }, 2529 { }, 2530 }; 2531 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table); 2532 2533 static struct platform_driver qmp_usb_driver = { 2534 .probe = qmp_usb_probe, 2535 .driver = { 2536 .name = "qcom-qmp-usb-phy", 2537 .pm = &qmp_usb_pm_ops, 2538 .of_match_table = qmp_usb_of_match_table, 2539 }, 2540 }; 2541 2542 module_platform_driver(qmp_usb_driver); 2543 2544 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2545 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); 2546 MODULE_LICENSE("GPL v2"); 2547