1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 22 #include <ufs/unipro.h> 23 24 #include "phy-qcom-qmp-common.h" 25 26 #include "phy-qcom-qmp.h" 27 #include "phy-qcom-qmp-pcs-ufs-v2.h" 28 #include "phy-qcom-qmp-pcs-ufs-v3.h" 29 #include "phy-qcom-qmp-pcs-ufs-v4.h" 30 #include "phy-qcom-qmp-pcs-ufs-v5.h" 31 #include "phy-qcom-qmp-pcs-ufs-v6.h" 32 33 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" 34 #include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h" 35 36 /* QPHY_PCS_READY_STATUS bit */ 37 #define PCS_READY BIT(0) 38 39 #define PHY_INIT_COMPLETE_TIMEOUT 10000 40 41 #define NUM_OVERLAY 2 42 43 /* set of registers with offsets different per-PHY */ 44 enum qphy_reg_layout { 45 /* PCS registers */ 46 QPHY_SW_RESET, 47 QPHY_START_CTRL, 48 QPHY_PCS_READY_STATUS, 49 QPHY_PCS_POWER_DOWN_CONTROL, 50 /* Keep last to ensure regs_layout arrays are properly initialized */ 51 QPHY_LAYOUT_SIZE 52 }; 53 54 static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 55 [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, 56 [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, 57 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, 58 }; 59 60 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 61 [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, 62 [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, 63 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL, 64 }; 65 66 static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 67 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, 68 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, 69 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, 70 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, 71 }; 72 73 static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 74 [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START, 75 [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS, 76 [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET, 77 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, 78 }; 79 80 static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 81 [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, 82 [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, 83 [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET, 84 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, 85 }; 86 87 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { 88 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 89 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), 90 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 91 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 92 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 93 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 94 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), 95 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 96 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 97 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 98 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), 99 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 100 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 101 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 102 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 103 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 104 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), 105 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 106 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 107 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 108 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 109 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 110 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 111 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 112 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 113 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 114 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 115 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 116 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 117 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 118 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 119 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 120 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 121 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 122 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 123 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 124 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 125 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 126 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 127 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 128 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 129 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 130 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 131 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 132 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 133 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 134 }; 135 136 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = { 137 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 138 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), 139 }; 140 141 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = { 142 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 143 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), 144 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), 145 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), 146 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 147 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), 148 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), 149 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), 150 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), 151 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), 152 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), 153 }; 154 155 static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = { 156 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 157 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 158 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 159 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 160 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 161 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 162 }; 163 164 static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = { 165 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 166 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 167 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 168 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 169 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 170 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 171 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 172 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 173 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 174 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 175 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 176 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 177 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 178 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 179 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 180 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 181 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 182 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 183 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 184 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d), 185 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d), 186 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed), 187 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 188 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c), 189 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 190 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 191 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 192 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 193 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 194 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 195 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 196 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 197 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 198 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 199 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 200 }; 201 202 static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = { 203 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 204 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 205 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 206 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 207 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 208 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 209 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 210 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03), 211 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), 212 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), 213 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), 214 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06), 215 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), 216 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), 217 }; 218 219 static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = { 220 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 221 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 222 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 223 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 224 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 225 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 226 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 227 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 228 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 229 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 230 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 231 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 232 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 233 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 234 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), 235 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 236 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 237 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 238 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 239 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 240 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), 246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), 258 }; 259 260 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = { 261 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 262 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 263 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 264 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 265 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 266 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 267 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 268 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 269 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 270 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 271 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 272 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 273 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 274 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 275 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 276 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 277 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), 278 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 279 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 280 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 281 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 282 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 284 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 285 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 286 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 287 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 288 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 289 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 290 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 291 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 292 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 293 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 294 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 295 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 296 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 297 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 298 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 299 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 300 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 301 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 302 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 303 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 304 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 305 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 306 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 307 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 308 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 309 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), 310 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), 311 }; 312 313 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = { 314 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), 315 }; 316 317 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = { 318 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 319 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 320 }; 321 322 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = { 323 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 324 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), 325 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), 326 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), 327 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 328 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), 329 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), 330 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), 331 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), 332 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), 333 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), 334 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 335 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 336 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), 337 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), 338 }; 339 340 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = { 341 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15), 342 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 343 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 344 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 345 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), 346 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 347 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12), 348 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), 349 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ 350 }; 351 352 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = { 353 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 354 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 355 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 356 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 357 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 358 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), 359 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 360 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 361 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 362 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 363 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 364 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 365 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), 366 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), 367 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), 368 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), 369 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 370 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 371 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 372 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 373 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 374 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 375 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), 376 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 377 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), 378 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), 379 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), 380 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), 381 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), 382 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), 383 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 384 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 385 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), 386 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), 387 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), 388 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), 389 }; 390 391 static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = { 392 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), 393 }; 394 395 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = { 396 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 397 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), 398 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 399 }; 400 401 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = { 402 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 403 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 404 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 405 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 406 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 407 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 408 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 409 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 410 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 411 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 412 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 413 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 414 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 415 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 416 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 417 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 418 }; 419 420 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = { 421 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), 422 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), 427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), 428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 429 }; 430 431 static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = { 432 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 433 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 434 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 435 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 436 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 437 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 438 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 439 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 440 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 441 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 442 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 443 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 444 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b), 445 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 446 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 447 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 448 }; 449 450 static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = { 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 459 }; 460 461 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = { 462 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), 463 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), 464 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 465 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), 466 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 467 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 468 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), 469 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 470 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 471 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 472 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), 475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), 476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), 479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), 483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), 484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 486 }; 487 488 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = { 489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), 490 }; 491 492 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { 493 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 494 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 495 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 496 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 497 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), 498 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 499 }; 500 501 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = { 502 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), 503 }; 504 505 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { 506 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 507 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 508 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 509 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 510 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 511 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 512 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 513 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 514 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 515 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 516 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 517 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 518 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 519 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 520 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 521 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 522 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 523 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), 526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), 527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), 528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), 530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 540 }; 541 542 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = { 543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), 555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 559 }; 560 561 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { 562 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 563 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 564 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 565 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 566 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 567 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 568 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 569 }; 570 571 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { 572 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), 573 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 574 }; 575 576 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = { 577 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), 578 }; 579 580 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = { 581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), 588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 602 }; 603 604 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { 605 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), 606 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), 607 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 608 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 609 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 610 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 611 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 612 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 613 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 614 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), 615 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), 616 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), 617 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 618 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), 619 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 620 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 621 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), 622 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), 623 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), 624 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), 625 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), 626 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), 627 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 628 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 629 }; 630 631 static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = { 632 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), 633 }; 634 635 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = { 636 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 637 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 638 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 639 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 640 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), 641 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 642 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), 643 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 644 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), 645 }; 646 647 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = { 648 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), 649 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), 650 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 651 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), 652 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 653 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 654 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), 655 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 656 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), 657 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), 658 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), 659 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), 660 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 661 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 662 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 663 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 664 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 665 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 666 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), 667 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 668 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), 670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), 671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), 672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), 673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), 674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), 675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), 676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), 677 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), 678 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), 679 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), 680 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), 681 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), 682 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), 683 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), 684 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 685 }; 686 687 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = { 688 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 689 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 690 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 691 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 692 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 693 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 694 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), 695 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 696 }; 697 698 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = { 699 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), 700 }; 701 702 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = { 703 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), 704 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), 705 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 706 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 707 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 708 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), 709 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), 710 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 711 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), 712 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), 713 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 714 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), 715 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), 716 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), 717 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), 718 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), 719 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), 720 }; 721 722 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { 723 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 724 }; 725 726 static const struct qmp_phy_init_tbl sm8475_ufsphy_serdes[] = { 727 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 728 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 729 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 730 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 731 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 732 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 733 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18), 736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff), 737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c), 738 }; 739 740 static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_serdes[] = { 741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14), 744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98), 745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14), 746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18), 748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32), 749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f), 750 }; 751 752 static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_pcs[] = { 753 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b), 754 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 755 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 756 }; 757 758 static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { 759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 770 }; 771 772 static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { 773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), 774 }; 775 776 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = { 777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), 780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), 782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 785 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 786 }; 787 788 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = { 789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b), 791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c), 792 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 793 }; 794 795 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { 796 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), 797 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 798 }; 799 800 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = { 801 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c), 802 }; 803 804 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { 805 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 806 807 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), 808 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), 809 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 810 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 811 812 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 813 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 814 815 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 816 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 817 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 818 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 819 }; 820 821 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = { 822 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), 823 }; 824 825 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = { 826 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), 827 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), 828 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 829 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), 830 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 831 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 832 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 833 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 834 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08), 835 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), 836 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), 837 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff), 838 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), 839 }; 840 841 static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { 842 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), 843 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 844 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 845 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 846 }; 847 848 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = { 849 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), 850 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 851 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 852 }; 853 854 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = { 855 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 856 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f), 857 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), 858 }; 859 860 static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = { 861 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 862 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 863 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 864 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 865 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 866 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 867 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f), 868 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a), 869 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17), 870 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 871 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 872 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 873 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 874 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 875 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 876 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 877 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 878 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 879 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 880 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 881 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 882 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 883 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 884 }; 885 886 static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = { 887 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x01), 888 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 889 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 890 }; 891 892 static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = { 893 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 894 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), 895 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), 896 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 897 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), 898 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 899 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 900 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 901 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 902 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e), 903 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 904 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce), 905 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce), 906 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18), 907 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 908 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f), 909 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 910 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 911 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 912 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 913 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 914 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 915 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 916 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B0, 0x24), 917 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B1, 0x24), 918 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B2, 0x20), 919 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), 920 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), 921 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f), 922 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94), 923 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa), 924 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), 925 }; 926 927 static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = { 928 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 929 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 930 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1), 931 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 932 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), 933 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e), 934 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12), 935 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15), 936 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19), 937 }; 938 939 static const struct qmp_phy_init_tbl sm8650_ufsphy_g4_pcs[] = { 940 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x13), 941 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 942 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 943 }; 944 945 static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = { 946 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 947 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05), 948 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05), 949 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d), 950 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), 951 }; 952 953 static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = { 954 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 955 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 956 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 957 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 958 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 959 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60), 960 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 961 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f), 962 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07), 963 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20), 964 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 965 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40), 966 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06), 967 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 968 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 969 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 970 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 971 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06), 972 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18), 973 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14), 974 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 975 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 976 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92), 977 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 978 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 979 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 980 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 981 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 982 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06), 983 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18), 984 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14), 985 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 986 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 987 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe), 988 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 989 }; 990 991 static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = { 992 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00), 993 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 994 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17), 995 }; 996 997 static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = { 998 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0c), 999 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0c), 1000 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04), 1001 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 1002 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07), 1003 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 1004 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 1005 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 1006 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 1007 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8e), 1008 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1009 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xce), 1010 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xce), 1011 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18), 1012 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1a), 1013 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0f), 1014 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60), 1015 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62), 1016 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9a), 1017 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xe2), 1018 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06), 1019 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1b), 1020 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1b), 1021 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98), 1022 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9b), 1023 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2a), 1024 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12), 1025 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06), 1026 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01), 1027 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93), 1028 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93), 1029 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60), 1030 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99), 1031 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5f), 1032 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92), 1033 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xe3), 1034 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06), 1035 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9b), 1036 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9b), 1037 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60), 1038 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99), 1039 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5f), 1040 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92), 1041 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xfb), 1042 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06), 1043 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1f), 1044 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94), 1045 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xfa), 1046 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30), 1047 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77), 1048 }; 1049 1050 static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = { 1051 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 1052 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 1053 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40), 1054 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 1055 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), 1056 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e), 1057 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12), 1058 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15), 1059 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19), 1060 }; 1061 1062 static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = { 1063 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 1064 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 1065 }; 1066 1067 static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = { 1068 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41), 1069 }; 1070 1071 struct qmp_ufs_offsets { 1072 u16 serdes; 1073 u16 pcs; 1074 u16 tx; 1075 u16 rx; 1076 u16 tx2; 1077 u16 rx2; 1078 }; 1079 1080 struct qmp_phy_cfg_tbls { 1081 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1082 const struct qmp_phy_init_tbl *serdes; 1083 int serdes_num; 1084 const struct qmp_phy_init_tbl *tx; 1085 int tx_num; 1086 const struct qmp_phy_init_tbl *rx; 1087 int rx_num; 1088 const struct qmp_phy_init_tbl *pcs; 1089 int pcs_num; 1090 /* Maximum supported Gear of this tbls */ 1091 u32 max_gear; 1092 }; 1093 1094 /* struct qmp_phy_cfg - per-PHY initialization config */ 1095 struct qmp_phy_cfg { 1096 int lanes; 1097 1098 const struct qmp_ufs_offsets *offsets; 1099 /* Maximum supported Gear of this config */ 1100 u32 max_supported_gear; 1101 1102 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1103 const struct qmp_phy_cfg_tbls tbls; 1104 /* Additional sequence for HS Series B */ 1105 const struct qmp_phy_cfg_tbls tbls_hs_b; 1106 /* Additional sequence for different HS Gears */ 1107 const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY]; 1108 1109 /* regulators to be requested */ 1110 const struct regulator_bulk_data *vreg_list; 1111 int num_vregs; 1112 1113 /* array of registers with different offsets */ 1114 const unsigned int *regs; 1115 1116 /* true, if PCS block has no separate SW_RESET register */ 1117 bool no_pcs_sw_reset; 1118 }; 1119 1120 struct qmp_ufs { 1121 struct device *dev; 1122 1123 const struct qmp_phy_cfg *cfg; 1124 1125 void __iomem *serdes; 1126 void __iomem *pcs; 1127 void __iomem *pcs_misc; 1128 void __iomem *tx; 1129 void __iomem *rx; 1130 void __iomem *tx2; 1131 void __iomem *rx2; 1132 1133 struct clk_bulk_data *clks; 1134 int num_clks; 1135 struct regulator_bulk_data *vregs; 1136 struct reset_control *ufs_reset; 1137 1138 struct phy *phy; 1139 u32 mode; 1140 u32 submode; 1141 }; 1142 1143 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1144 { 1145 u32 reg; 1146 1147 reg = readl(base + offset); 1148 reg |= val; 1149 writel(reg, base + offset); 1150 1151 /* ensure that above write is through */ 1152 readl(base + offset); 1153 } 1154 1155 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1156 { 1157 u32 reg; 1158 1159 reg = readl(base + offset); 1160 reg &= ~val; 1161 writel(reg, base + offset); 1162 1163 /* ensure that above write is through */ 1164 readl(base + offset); 1165 } 1166 1167 /* Regulator bulk data with load values for specific configurations */ 1168 static const struct regulator_bulk_data msm8996_ufsphy_vreg_l[] = { 1169 { .supply = "vdda-phy", .init_load_uA = 51400 }, 1170 { .supply = "vdda-pll", .init_load_uA = 14600 }, 1171 }; 1172 1173 static const struct regulator_bulk_data sa8775p_ufsphy_vreg_l[] = { 1174 { .supply = "vdda-phy", .init_load_uA = 137000 }, 1175 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1176 }; 1177 1178 static const struct regulator_bulk_data sc7280_ufsphy_vreg_l[] = { 1179 { .supply = "vdda-phy", .init_load_uA = 97500 }, 1180 { .supply = "vdda-pll", .init_load_uA = 18400 }, 1181 }; 1182 1183 static const struct regulator_bulk_data sc8280xp_ufsphy_vreg_l[] = { 1184 { .supply = "vdda-phy", .init_load_uA = 85700 }, 1185 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1186 }; 1187 1188 static const struct regulator_bulk_data sdm845_ufsphy_vreg_l[] = { 1189 { .supply = "vdda-phy", .init_load_uA = 51400 }, 1190 { .supply = "vdda-pll", .init_load_uA = 14600 }, 1191 }; 1192 1193 static const struct regulator_bulk_data sm6115_ufsphy_vreg_l[] = { 1194 { .supply = "vdda-phy", .init_load_uA = 51400 }, 1195 { .supply = "vdda-pll", .init_load_uA = 14200 }, 1196 }; 1197 1198 static const struct regulator_bulk_data sm7150_ufsphy_vreg_l[] = { 1199 { .supply = "vdda-phy", .init_load_uA = 62900 }, 1200 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1201 }; 1202 1203 static const struct regulator_bulk_data sm8150_ufsphy_vreg_l[] = { 1204 { .supply = "vdda-phy", .init_load_uA = 90200 }, 1205 { .supply = "vdda-pll", .init_load_uA = 19000 }, 1206 }; 1207 1208 static const struct regulator_bulk_data sm8250_ufsphy_vreg_l[] = { 1209 { .supply = "vdda-phy", .init_load_uA = 89900 }, 1210 { .supply = "vdda-pll", .init_load_uA = 18800 }, 1211 }; 1212 1213 static const struct regulator_bulk_data sm8350_ufsphy_vreg_l[] = { 1214 { .supply = "vdda-phy", .init_load_uA = 91600 }, 1215 { .supply = "vdda-pll", .init_load_uA = 19000 }, 1216 }; 1217 1218 static const struct regulator_bulk_data sm8450_ufsphy_vreg_l[] = { 1219 { .supply = "vdda-phy", .init_load_uA = 173000 }, 1220 { .supply = "vdda-pll", .init_load_uA = 24900 }, 1221 }; 1222 1223 static const struct regulator_bulk_data sm8475_ufsphy_vreg_l[] = { 1224 { .supply = "vdda-phy", .init_load_uA = 213030 }, 1225 { .supply = "vdda-pll", .init_load_uA = 18340 }, 1226 }; 1227 1228 static const struct regulator_bulk_data sm8550_ufsphy_vreg_l[] = { 1229 { .supply = "vdda-phy", .init_load_uA = 188000 }, 1230 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1231 }; 1232 1233 static const struct regulator_bulk_data sm8650_ufsphy_vreg_l[] = { 1234 { .supply = "vdda-phy", .init_load_uA = 205000 }, 1235 { .supply = "vdda-pll", .init_load_uA = 17500 }, 1236 }; 1237 1238 static const struct regulator_bulk_data sm8750_ufsphy_vreg_l[] = { 1239 { .supply = "vdda-phy", .init_load_uA = 213000 }, 1240 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1241 }; 1242 1243 static const struct qmp_ufs_offsets qmp_ufs_offsets = { 1244 .serdes = 0, 1245 .pcs = 0xc00, 1246 .tx = 0x400, 1247 .rx = 0x600, 1248 .tx2 = 0x800, 1249 .rx2 = 0xa00, 1250 }; 1251 1252 static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = { 1253 .serdes = 0, 1254 .pcs = 0x0400, 1255 .tx = 0x1000, 1256 .rx = 0x1200, 1257 .tx2 = 0x1800, 1258 .rx2 = 0x1a00, 1259 }; 1260 1261 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { 1262 .lanes = 1, 1263 1264 .offsets = &qmp_ufs_offsets, 1265 .max_supported_gear = UFS_HS_G3, 1266 1267 .tbls = { 1268 .serdes = msm8996_ufsphy_serdes, 1269 .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes), 1270 .tx = msm8996_ufsphy_tx, 1271 .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx), 1272 .rx = msm8996_ufsphy_rx, 1273 .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx), 1274 }, 1275 1276 .vreg_list = msm8996_ufsphy_vreg_l, 1277 .num_vregs = ARRAY_SIZE(msm8996_ufsphy_vreg_l), 1278 1279 .regs = ufsphy_v2_regs_layout, 1280 1281 .no_pcs_sw_reset = true, 1282 }; 1283 1284 static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = { 1285 .lanes = 2, 1286 1287 .offsets = &qmp_ufs_offsets, 1288 .max_supported_gear = UFS_HS_G4, 1289 1290 .tbls = { 1291 .serdes = sm8350_ufsphy_serdes, 1292 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1293 .tx = sm8350_ufsphy_tx, 1294 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1295 .rx = sm8350_ufsphy_rx, 1296 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1297 .pcs = sm8350_ufsphy_pcs, 1298 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1299 }, 1300 .tbls_hs_b = { 1301 .serdes = sm8350_ufsphy_hs_b_serdes, 1302 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1303 }, 1304 .tbls_hs_overlay[0] = { 1305 .tx = sm8350_ufsphy_g4_tx, 1306 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1307 .rx = sm8350_ufsphy_g4_rx, 1308 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1309 .pcs = sm8350_ufsphy_g4_pcs, 1310 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1311 .max_gear = UFS_HS_G4, 1312 }, 1313 .vreg_list = sa8775p_ufsphy_vreg_l, 1314 .num_vregs = ARRAY_SIZE(sa8775p_ufsphy_vreg_l), 1315 .regs = ufsphy_v5_regs_layout, 1316 }; 1317 1318 static const struct qmp_phy_cfg sc7280_ufsphy_cfg = { 1319 .lanes = 2, 1320 1321 .offsets = &qmp_ufs_offsets, 1322 .max_supported_gear = UFS_HS_G4, 1323 1324 .tbls = { 1325 .serdes = sm8150_ufsphy_serdes, 1326 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1327 .tx = sc7280_ufsphy_tx, 1328 .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx), 1329 .rx = sc7280_ufsphy_rx, 1330 .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx), 1331 .pcs = sc7280_ufsphy_pcs, 1332 .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs), 1333 }, 1334 .tbls_hs_b = { 1335 .serdes = sm8150_ufsphy_hs_b_serdes, 1336 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1337 }, 1338 .tbls_hs_overlay[0] = { 1339 .tx = sm8250_ufsphy_hs_g4_tx, 1340 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), 1341 .rx = sc7280_ufsphy_hs_g4_rx, 1342 .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx), 1343 .pcs = sm8150_ufsphy_hs_g4_pcs, 1344 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1345 .max_gear = UFS_HS_G4, 1346 }, 1347 .vreg_list = sc7280_ufsphy_vreg_l, 1348 .num_vregs = ARRAY_SIZE(sc7280_ufsphy_vreg_l), 1349 .regs = ufsphy_v4_regs_layout, 1350 }; 1351 1352 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { 1353 .lanes = 2, 1354 1355 .offsets = &qmp_ufs_offsets, 1356 .max_supported_gear = UFS_HS_G4, 1357 1358 .tbls = { 1359 .serdes = sm8350_ufsphy_serdes, 1360 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1361 .tx = sm8350_ufsphy_tx, 1362 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1363 .rx = sm8350_ufsphy_rx, 1364 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1365 .pcs = sm8350_ufsphy_pcs, 1366 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1367 }, 1368 .tbls_hs_b = { 1369 .serdes = sm8350_ufsphy_hs_b_serdes, 1370 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1371 }, 1372 .tbls_hs_overlay[0] = { 1373 .tx = sm8350_ufsphy_g4_tx, 1374 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1375 .rx = sm8350_ufsphy_g4_rx, 1376 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1377 .pcs = sm8350_ufsphy_g4_pcs, 1378 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1379 .max_gear = UFS_HS_G4, 1380 }, 1381 .vreg_list = sc8280xp_ufsphy_vreg_l, 1382 .num_vregs = ARRAY_SIZE(sc8280xp_ufsphy_vreg_l), 1383 .regs = ufsphy_v5_regs_layout, 1384 }; 1385 1386 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { 1387 .lanes = 2, 1388 1389 .offsets = &qmp_ufs_offsets, 1390 .max_supported_gear = UFS_HS_G3, 1391 1392 .tbls = { 1393 .serdes = sdm845_ufsphy_serdes, 1394 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 1395 .tx = sdm845_ufsphy_tx, 1396 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), 1397 .rx = sdm845_ufsphy_rx, 1398 .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx), 1399 .pcs = sdm845_ufsphy_pcs, 1400 .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs), 1401 }, 1402 .tbls_hs_b = { 1403 .serdes = sdm845_ufsphy_hs_b_serdes, 1404 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 1405 }, 1406 .vreg_list = sdm845_ufsphy_vreg_l, 1407 .num_vregs = ARRAY_SIZE(sdm845_ufsphy_vreg_l), 1408 .regs = ufsphy_v3_regs_layout, 1409 1410 .no_pcs_sw_reset = true, 1411 }; 1412 1413 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { 1414 .lanes = 1, 1415 1416 .offsets = &qmp_ufs_offsets, 1417 .max_supported_gear = UFS_HS_G3, 1418 1419 .tbls = { 1420 .serdes = sm6115_ufsphy_serdes, 1421 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes), 1422 .tx = sm6115_ufsphy_tx, 1423 .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx), 1424 .rx = sm6115_ufsphy_rx, 1425 .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx), 1426 .pcs = sm6115_ufsphy_pcs, 1427 .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs), 1428 }, 1429 .tbls_hs_b = { 1430 .serdes = sm6115_ufsphy_hs_b_serdes, 1431 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), 1432 }, 1433 .vreg_list = sm6115_ufsphy_vreg_l, 1434 .num_vregs = ARRAY_SIZE(sm6115_ufsphy_vreg_l), 1435 .regs = ufsphy_v2_regs_layout, 1436 1437 .no_pcs_sw_reset = true, 1438 }; 1439 1440 static const struct qmp_phy_cfg sm7150_ufsphy_cfg = { 1441 .lanes = 1, 1442 1443 .offsets = &qmp_ufs_offsets, 1444 .max_supported_gear = UFS_HS_G3, 1445 1446 .tbls = { 1447 .serdes = sdm845_ufsphy_serdes, 1448 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 1449 .tx = sdm845_ufsphy_tx, 1450 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), 1451 .rx = sm7150_ufsphy_rx, 1452 .rx_num = ARRAY_SIZE(sm7150_ufsphy_rx), 1453 .pcs = sm7150_ufsphy_pcs, 1454 .pcs_num = ARRAY_SIZE(sm7150_ufsphy_pcs), 1455 }, 1456 .tbls_hs_b = { 1457 .serdes = sdm845_ufsphy_hs_b_serdes, 1458 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 1459 }, 1460 .vreg_list = sm7150_ufsphy_vreg_l, 1461 .num_vregs = ARRAY_SIZE(sm7150_ufsphy_vreg_l), 1462 .regs = ufsphy_v3_regs_layout, 1463 1464 .no_pcs_sw_reset = true, 1465 }; 1466 1467 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { 1468 .lanes = 2, 1469 1470 .offsets = &qmp_ufs_offsets, 1471 .max_supported_gear = UFS_HS_G4, 1472 1473 .tbls = { 1474 .serdes = sm8150_ufsphy_serdes, 1475 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1476 .tx = sm8150_ufsphy_tx, 1477 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 1478 .rx = sm8150_ufsphy_rx, 1479 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 1480 .pcs = sm8150_ufsphy_pcs, 1481 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 1482 }, 1483 .tbls_hs_b = { 1484 .serdes = sm8150_ufsphy_hs_b_serdes, 1485 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1486 }, 1487 .tbls_hs_overlay[0] = { 1488 .tx = sm8150_ufsphy_hs_g4_tx, 1489 .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), 1490 .rx = sm8150_ufsphy_hs_g4_rx, 1491 .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), 1492 .pcs = sm8150_ufsphy_hs_g4_pcs, 1493 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1494 .max_gear = UFS_HS_G4, 1495 }, 1496 .vreg_list = sm8150_ufsphy_vreg_l, 1497 .num_vregs = ARRAY_SIZE(sm8150_ufsphy_vreg_l), 1498 .regs = ufsphy_v4_regs_layout, 1499 }; 1500 1501 static const struct qmp_phy_cfg sm8250_ufsphy_cfg = { 1502 .lanes = 2, 1503 1504 .offsets = &qmp_ufs_offsets, 1505 .max_supported_gear = UFS_HS_G4, 1506 1507 .tbls = { 1508 .serdes = sm8150_ufsphy_serdes, 1509 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1510 .tx = sm8150_ufsphy_tx, 1511 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 1512 .rx = sm8150_ufsphy_rx, 1513 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 1514 .pcs = sm8150_ufsphy_pcs, 1515 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 1516 }, 1517 .tbls_hs_b = { 1518 .serdes = sm8150_ufsphy_hs_b_serdes, 1519 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1520 }, 1521 .tbls_hs_overlay[0] = { 1522 .tx = sm8250_ufsphy_hs_g4_tx, 1523 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), 1524 .rx = sm8250_ufsphy_hs_g4_rx, 1525 .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), 1526 .pcs = sm8150_ufsphy_hs_g4_pcs, 1527 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1528 .max_gear = UFS_HS_G4, 1529 }, 1530 .vreg_list = sm8250_ufsphy_vreg_l, 1531 .num_vregs = ARRAY_SIZE(sm8250_ufsphy_vreg_l), 1532 .regs = ufsphy_v4_regs_layout, 1533 }; 1534 1535 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { 1536 .lanes = 2, 1537 1538 .offsets = &qmp_ufs_offsets, 1539 .max_supported_gear = UFS_HS_G4, 1540 1541 .tbls = { 1542 .serdes = sm8350_ufsphy_serdes, 1543 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1544 .tx = sm8350_ufsphy_tx, 1545 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1546 .rx = sm8350_ufsphy_rx, 1547 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1548 .pcs = sm8350_ufsphy_pcs, 1549 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1550 }, 1551 .tbls_hs_b = { 1552 .serdes = sm8350_ufsphy_hs_b_serdes, 1553 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1554 }, 1555 .tbls_hs_overlay[0] = { 1556 .tx = sm8350_ufsphy_g4_tx, 1557 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1558 .rx = sm8350_ufsphy_g4_rx, 1559 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1560 .pcs = sm8350_ufsphy_g4_pcs, 1561 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1562 .max_gear = UFS_HS_G4, 1563 }, 1564 .vreg_list = sm8350_ufsphy_vreg_l, 1565 .num_vregs = ARRAY_SIZE(sm8350_ufsphy_vreg_l), 1566 .regs = ufsphy_v5_regs_layout, 1567 }; 1568 1569 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { 1570 .lanes = 2, 1571 1572 .offsets = &qmp_ufs_offsets, 1573 .max_supported_gear = UFS_HS_G4, 1574 1575 .tbls = { 1576 .serdes = sm8350_ufsphy_serdes, 1577 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1578 .tx = sm8350_ufsphy_tx, 1579 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1580 .rx = sm8350_ufsphy_rx, 1581 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1582 .pcs = sm8350_ufsphy_pcs, 1583 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1584 }, 1585 .tbls_hs_b = { 1586 .serdes = sm8350_ufsphy_hs_b_serdes, 1587 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1588 }, 1589 .tbls_hs_overlay[0] = { 1590 .tx = sm8350_ufsphy_g4_tx, 1591 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1592 .rx = sm8350_ufsphy_g4_rx, 1593 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1594 .pcs = sm8350_ufsphy_g4_pcs, 1595 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1596 .max_gear = UFS_HS_G4, 1597 }, 1598 .vreg_list = sm8450_ufsphy_vreg_l, 1599 .num_vregs = ARRAY_SIZE(sm8450_ufsphy_vreg_l), 1600 .regs = ufsphy_v5_regs_layout, 1601 }; 1602 1603 static const struct qmp_phy_cfg sm8475_ufsphy_cfg = { 1604 .lanes = 2, 1605 1606 .offsets = &qmp_ufs_offsets_v6, 1607 .max_supported_gear = UFS_HS_G4, 1608 1609 .tbls = { 1610 .serdes = sm8475_ufsphy_serdes, 1611 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_serdes), 1612 .tx = sm8550_ufsphy_tx, 1613 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), 1614 .rx = sm8550_ufsphy_rx, 1615 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), 1616 .pcs = sm8550_ufsphy_pcs, 1617 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), 1618 }, 1619 .tbls_hs_b = { 1620 .serdes = sm8550_ufsphy_hs_b_serdes, 1621 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), 1622 }, 1623 .tbls_hs_overlay[0] = { 1624 .serdes = sm8475_ufsphy_g4_serdes, 1625 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_g4_serdes), 1626 .tx = sm8550_ufsphy_g4_tx, 1627 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx), 1628 .rx = sm8550_ufsphy_g4_rx, 1629 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx), 1630 .pcs = sm8475_ufsphy_g4_pcs, 1631 .pcs_num = ARRAY_SIZE(sm8475_ufsphy_g4_pcs), 1632 .max_gear = UFS_HS_G4, 1633 }, 1634 .vreg_list = sm8475_ufsphy_vreg_l, 1635 .num_vregs = ARRAY_SIZE(sm8475_ufsphy_vreg_l), 1636 .regs = ufsphy_v6_regs_layout, 1637 }; 1638 1639 static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { 1640 .lanes = 2, 1641 1642 .offsets = &qmp_ufs_offsets_v6, 1643 .max_supported_gear = UFS_HS_G5, 1644 1645 .tbls = { 1646 .serdes = sm8550_ufsphy_serdes, 1647 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), 1648 .tx = sm8550_ufsphy_tx, 1649 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), 1650 .rx = sm8550_ufsphy_rx, 1651 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), 1652 .pcs = sm8550_ufsphy_pcs, 1653 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), 1654 }, 1655 .tbls_hs_b = { 1656 .serdes = sm8550_ufsphy_hs_b_serdes, 1657 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), 1658 }, 1659 .tbls_hs_overlay[0] = { 1660 .serdes = sm8550_ufsphy_g4_serdes, 1661 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes), 1662 .tx = sm8550_ufsphy_g4_tx, 1663 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx), 1664 .rx = sm8550_ufsphy_g4_rx, 1665 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx), 1666 .pcs = sm8550_ufsphy_g4_pcs, 1667 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs), 1668 .max_gear = UFS_HS_G4, 1669 }, 1670 .tbls_hs_overlay[1] = { 1671 .serdes = sm8550_ufsphy_g5_serdes, 1672 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes), 1673 .rx = sm8550_ufsphy_g5_rx, 1674 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx), 1675 .pcs = sm8550_ufsphy_g5_pcs, 1676 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs), 1677 .max_gear = UFS_HS_G5, 1678 }, 1679 .vreg_list = sm8550_ufsphy_vreg_l, 1680 .num_vregs = ARRAY_SIZE(sm8550_ufsphy_vreg_l), 1681 .regs = ufsphy_v6_regs_layout, 1682 }; 1683 1684 static const struct qmp_phy_cfg sm8650_ufsphy_cfg = { 1685 .lanes = 2, 1686 1687 .offsets = &qmp_ufs_offsets_v6, 1688 .max_supported_gear = UFS_HS_G5, 1689 1690 .tbls = { 1691 .serdes = sm8650_ufsphy_serdes, 1692 .serdes_num = ARRAY_SIZE(sm8650_ufsphy_serdes), 1693 .tx = sm8650_ufsphy_tx, 1694 .tx_num = ARRAY_SIZE(sm8650_ufsphy_tx), 1695 .rx = sm8650_ufsphy_rx, 1696 .rx_num = ARRAY_SIZE(sm8650_ufsphy_rx), 1697 .pcs = sm8650_ufsphy_pcs, 1698 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs), 1699 }, 1700 .tbls_hs_overlay[0] = { 1701 .pcs = sm8650_ufsphy_g4_pcs, 1702 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g4_pcs), 1703 .max_gear = UFS_HS_G4, 1704 }, 1705 .tbls_hs_overlay[1] = { 1706 .pcs = sm8650_ufsphy_g5_pcs, 1707 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs), 1708 .max_gear = UFS_HS_G5, 1709 }, 1710 1711 .vreg_list = sm8650_ufsphy_vreg_l, 1712 .num_vregs = ARRAY_SIZE(sm8650_ufsphy_vreg_l), 1713 .regs = ufsphy_v6_regs_layout, 1714 }; 1715 1716 static const struct qmp_phy_cfg sm8750_ufsphy_cfg = { 1717 .lanes = 2, 1718 1719 .offsets = &qmp_ufs_offsets_v6, 1720 .max_supported_gear = UFS_HS_G5, 1721 1722 .tbls = { 1723 .serdes = sm8750_ufsphy_serdes, 1724 .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes), 1725 .tx = sm8750_ufsphy_tx, 1726 .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx), 1727 .rx = sm8750_ufsphy_rx, 1728 .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx), 1729 .pcs = sm8750_ufsphy_pcs, 1730 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs), 1731 }, 1732 1733 .tbls_hs_b = { 1734 .pcs = sm8750_ufsphy_hs_b_pcs, 1735 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs), 1736 }, 1737 1738 .tbls_hs_overlay[0] = { 1739 .pcs = sm8750_ufsphy_g4_pcs, 1740 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs), 1741 .max_gear = UFS_HS_G4, 1742 }, 1743 .tbls_hs_overlay[1] = { 1744 .pcs = sm8650_ufsphy_g5_pcs, 1745 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs), 1746 .max_gear = UFS_HS_G5, 1747 }, 1748 1749 .vreg_list = sm8750_ufsphy_vreg_l, 1750 .num_vregs = ARRAY_SIZE(sm8750_ufsphy_vreg_l), 1751 .regs = ufsphy_v6_regs_layout, 1752 1753 }; 1754 1755 static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1756 { 1757 void __iomem *serdes = qmp->serdes; 1758 1759 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 1760 } 1761 1762 static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1763 { 1764 const struct qmp_phy_cfg *cfg = qmp->cfg; 1765 void __iomem *tx = qmp->tx; 1766 void __iomem *rx = qmp->rx; 1767 1768 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); 1769 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); 1770 1771 if (cfg->lanes >= 2) { 1772 qmp_configure_lane(qmp->dev, qmp->tx2, tbls->tx, tbls->tx_num, 2); 1773 qmp_configure_lane(qmp->dev, qmp->rx2, tbls->rx, tbls->rx_num, 2); 1774 } 1775 } 1776 1777 static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1778 { 1779 void __iomem *pcs = qmp->pcs; 1780 1781 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 1782 } 1783 1784 static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) 1785 { 1786 u32 max_gear, floor_max_gear = cfg->max_supported_gear; 1787 int idx, ret = -EINVAL; 1788 1789 for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) { 1790 max_gear = cfg->tbls_hs_overlay[idx].max_gear; 1791 1792 /* Skip if the table is not available */ 1793 if (max_gear == 0) 1794 continue; 1795 1796 /* Direct matching, bail */ 1797 if (qmp->submode == max_gear) 1798 return idx; 1799 1800 /* If no direct matching, the lowest gear is the best matching */ 1801 if (max_gear < floor_max_gear) { 1802 ret = idx; 1803 floor_max_gear = max_gear; 1804 } 1805 } 1806 1807 return ret; 1808 } 1809 1810 static void qmp_ufs_init_all(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1811 { 1812 qmp_ufs_serdes_init(qmp, tbls); 1813 qmp_ufs_lanes_init(qmp, tbls); 1814 qmp_ufs_pcs_init(qmp, tbls); 1815 } 1816 1817 static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) 1818 { 1819 int i; 1820 1821 qmp_ufs_init_all(qmp, &cfg->tbls); 1822 1823 i = qmp_ufs_get_gear_overlay(qmp, cfg); 1824 if (i >= 0) { 1825 qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]); 1826 } 1827 1828 if (qmp->mode == PHY_MODE_UFS_HS_B) 1829 qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); 1830 } 1831 1832 static int qmp_ufs_power_on(struct phy *phy) 1833 { 1834 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1835 const struct qmp_phy_cfg *cfg = qmp->cfg; 1836 void __iomem *pcs = qmp->pcs; 1837 int ret; 1838 1839 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1840 if (ret) { 1841 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1842 return ret; 1843 } 1844 1845 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 1846 if (ret) 1847 goto err_disable_regulators; 1848 1849 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1850 return 0; 1851 1852 err_disable_regulators: 1853 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1854 return ret; 1855 } 1856 1857 static int qmp_ufs_phy_calibrate(struct phy *phy) 1858 { 1859 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1860 const struct qmp_phy_cfg *cfg = qmp->cfg; 1861 void __iomem *pcs = qmp->pcs; 1862 void __iomem *status; 1863 unsigned int val; 1864 int ret; 1865 1866 ret = reset_control_assert(qmp->ufs_reset); 1867 if (ret) 1868 return ret; 1869 1870 qmp_ufs_init_registers(qmp, cfg); 1871 1872 ret = reset_control_deassert(qmp->ufs_reset); 1873 if (ret) 1874 return ret; 1875 1876 /* Pull PHY out of reset state */ 1877 if (!cfg->no_pcs_sw_reset) 1878 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1879 1880 /* start SerDes */ 1881 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); 1882 1883 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 1884 ret = readl_poll_timeout(status, val, (val & PCS_READY), 200, 1885 PHY_INIT_COMPLETE_TIMEOUT); 1886 if (ret) { 1887 dev_err(qmp->dev, "phy initialization timed-out\n"); 1888 return ret; 1889 } 1890 1891 return 0; 1892 } 1893 1894 static int qmp_ufs_power_off(struct phy *phy) 1895 { 1896 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1897 const struct qmp_phy_cfg *cfg = qmp->cfg; 1898 1899 /* Put PHY into POWER DOWN state: active low */ 1900 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1901 SW_PWRDN); 1902 1903 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 1904 1905 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1906 1907 return 0; 1908 } 1909 1910 static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) 1911 { 1912 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1913 const struct qmp_phy_cfg *cfg = qmp->cfg; 1914 1915 if (submode > cfg->max_supported_gear || submode == 0) { 1916 dev_err(qmp->dev, "Invalid PHY submode %d\n", submode); 1917 return -EINVAL; 1918 } 1919 1920 qmp->mode = mode; 1921 qmp->submode = submode; 1922 1923 return 0; 1924 } 1925 1926 static int qmp_ufs_phy_init(struct phy *phy) 1927 { 1928 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1929 const struct qmp_phy_cfg *cfg = qmp->cfg; 1930 int ret; 1931 1932 if (!cfg->no_pcs_sw_reset) 1933 return 0; 1934 1935 /* 1936 * Get UFS reset, which is delayed until now to avoid a 1937 * circular dependency where UFS needs its PHY, but the PHY 1938 * needs this UFS reset. 1939 */ 1940 if (!qmp->ufs_reset) { 1941 qmp->ufs_reset = 1942 devm_reset_control_get_exclusive(qmp->dev, "ufsphy"); 1943 1944 if (IS_ERR(qmp->ufs_reset)) { 1945 ret = PTR_ERR(qmp->ufs_reset); 1946 dev_err(qmp->dev, "failed to get PHY reset: %d\n", ret); 1947 qmp->ufs_reset = NULL; 1948 return ret; 1949 } 1950 } 1951 1952 return 0; 1953 } 1954 1955 static const struct phy_ops qcom_qmp_ufs_phy_ops = { 1956 .init = qmp_ufs_phy_init, 1957 .power_on = qmp_ufs_power_on, 1958 .power_off = qmp_ufs_power_off, 1959 .calibrate = qmp_ufs_phy_calibrate, 1960 .set_mode = qmp_ufs_set_mode, 1961 .owner = THIS_MODULE, 1962 }; 1963 1964 1965 static int qmp_ufs_clk_init(struct qmp_ufs *qmp) 1966 { 1967 struct device *dev = qmp->dev; 1968 1969 qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks); 1970 if (qmp->num_clks < 0) 1971 return qmp->num_clks; 1972 1973 return 0; 1974 } 1975 1976 static void qmp_ufs_clk_release_provider(void *res) 1977 { 1978 of_clk_del_provider(res); 1979 } 1980 1981 #define UFS_SYMBOL_CLOCKS 3 1982 1983 static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np) 1984 { 1985 struct clk_hw_onecell_data *clk_data; 1986 struct clk_hw *hw; 1987 char name[64]; 1988 int ret; 1989 1990 clk_data = devm_kzalloc(qmp->dev, 1991 struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS), 1992 GFP_KERNEL); 1993 if (!clk_data) 1994 return -ENOMEM; 1995 1996 clk_data->num = UFS_SYMBOL_CLOCKS; 1997 1998 snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev)); 1999 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 2000 if (IS_ERR(hw)) 2001 return PTR_ERR(hw); 2002 2003 clk_data->hws[0] = hw; 2004 2005 snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev)); 2006 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 2007 if (IS_ERR(hw)) 2008 return PTR_ERR(hw); 2009 2010 clk_data->hws[1] = hw; 2011 2012 snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev)); 2013 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 2014 if (IS_ERR(hw)) 2015 return PTR_ERR(hw); 2016 2017 clk_data->hws[2] = hw; 2018 2019 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 2020 if (ret) 2021 return ret; 2022 2023 /* 2024 * Roll a devm action because the clock provider can be a child node. 2025 */ 2026 return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np); 2027 } 2028 2029 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np) 2030 { 2031 struct platform_device *pdev = to_platform_device(qmp->dev); 2032 const struct qmp_phy_cfg *cfg = qmp->cfg; 2033 struct device *dev = qmp->dev; 2034 2035 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2036 if (IS_ERR(qmp->serdes)) 2037 return PTR_ERR(qmp->serdes); 2038 2039 /* 2040 * Get memory resources for the PHY: 2041 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2042 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2043 * For single lane PHYs: pcs_misc (optional) -> 3. 2044 */ 2045 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2046 if (IS_ERR(qmp->tx)) 2047 return PTR_ERR(qmp->tx); 2048 2049 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2050 if (IS_ERR(qmp->rx)) 2051 return PTR_ERR(qmp->rx); 2052 2053 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 2054 if (IS_ERR(qmp->pcs)) 2055 return PTR_ERR(qmp->pcs); 2056 2057 if (cfg->lanes >= 2) { 2058 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2059 if (IS_ERR(qmp->tx2)) 2060 return PTR_ERR(qmp->tx2); 2061 2062 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2063 if (IS_ERR(qmp->rx2)) 2064 return PTR_ERR(qmp->rx2); 2065 2066 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2067 } else { 2068 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2069 } 2070 2071 if (IS_ERR(qmp->pcs_misc)) 2072 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2073 2074 return 0; 2075 } 2076 2077 static int qmp_ufs_parse_dt(struct qmp_ufs *qmp) 2078 { 2079 struct platform_device *pdev = to_platform_device(qmp->dev); 2080 const struct qmp_phy_cfg *cfg = qmp->cfg; 2081 const struct qmp_ufs_offsets *offs = cfg->offsets; 2082 void __iomem *base; 2083 2084 if (!offs) 2085 return -EINVAL; 2086 2087 base = devm_platform_ioremap_resource(pdev, 0); 2088 if (IS_ERR(base)) 2089 return PTR_ERR(base); 2090 2091 qmp->serdes = base + offs->serdes; 2092 qmp->pcs = base + offs->pcs; 2093 qmp->tx = base + offs->tx; 2094 qmp->rx = base + offs->rx; 2095 2096 if (cfg->lanes >= 2) { 2097 qmp->tx2 = base + offs->tx2; 2098 qmp->rx2 = base + offs->rx2; 2099 } 2100 2101 return 0; 2102 } 2103 2104 static int qmp_ufs_probe(struct platform_device *pdev) 2105 { 2106 struct device *dev = &pdev->dev; 2107 struct phy_provider *phy_provider; 2108 struct device_node *np; 2109 struct qmp_ufs *qmp; 2110 int ret; 2111 2112 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2113 if (!qmp) 2114 return -ENOMEM; 2115 2116 qmp->dev = dev; 2117 2118 qmp->cfg = of_device_get_match_data(dev); 2119 if (!qmp->cfg) 2120 return -EINVAL; 2121 2122 ret = qmp_ufs_clk_init(qmp); 2123 if (ret) 2124 return ret; 2125 2126 ret = devm_regulator_bulk_get_const(dev, qmp->cfg->num_vregs, 2127 qmp->cfg->vreg_list, 2128 &qmp->vregs); 2129 if (ret) 2130 return ret; 2131 2132 /* Check for legacy binding with child node. */ 2133 np = of_get_next_available_child(dev->of_node, NULL); 2134 if (np) { 2135 ret = qmp_ufs_parse_dt_legacy(qmp, np); 2136 } else { 2137 np = of_node_get(dev->of_node); 2138 ret = qmp_ufs_parse_dt(qmp); 2139 } 2140 if (ret) 2141 goto err_node_put; 2142 2143 ret = qmp_ufs_register_clocks(qmp, np); 2144 if (ret) 2145 goto err_node_put; 2146 2147 qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops); 2148 if (IS_ERR(qmp->phy)) { 2149 ret = PTR_ERR(qmp->phy); 2150 dev_err(dev, "failed to create PHY: %d\n", ret); 2151 goto err_node_put; 2152 } 2153 2154 phy_set_drvdata(qmp->phy, qmp); 2155 2156 of_node_put(np); 2157 2158 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2159 2160 return PTR_ERR_OR_ZERO(phy_provider); 2161 2162 err_node_put: 2163 of_node_put(np); 2164 return ret; 2165 } 2166 2167 static const struct of_device_id qmp_ufs_of_match_table[] = { 2168 { 2169 .compatible = "qcom,msm8996-qmp-ufs-phy", 2170 .data = &msm8996_ufsphy_cfg, 2171 }, { 2172 .compatible = "qcom,msm8998-qmp-ufs-phy", 2173 .data = &sdm845_ufsphy_cfg, 2174 }, { 2175 .compatible = "qcom,sa8775p-qmp-ufs-phy", 2176 .data = &sa8775p_ufsphy_cfg, 2177 }, { 2178 .compatible = "qcom,sc7180-qmp-ufs-phy", 2179 .data = &sm7150_ufsphy_cfg, 2180 }, { 2181 .compatible = "qcom,sc7280-qmp-ufs-phy", 2182 .data = &sc7280_ufsphy_cfg, 2183 }, { 2184 .compatible = "qcom,sc8180x-qmp-ufs-phy", 2185 .data = &sm8150_ufsphy_cfg, 2186 }, { 2187 .compatible = "qcom,sc8280xp-qmp-ufs-phy", 2188 .data = &sc8280xp_ufsphy_cfg, 2189 }, { 2190 .compatible = "qcom,sdm845-qmp-ufs-phy", 2191 .data = &sdm845_ufsphy_cfg, 2192 }, { 2193 .compatible = "qcom,sm6115-qmp-ufs-phy", 2194 .data = &sm6115_ufsphy_cfg, 2195 }, { 2196 .compatible = "qcom,sm6125-qmp-ufs-phy", 2197 .data = &sm6115_ufsphy_cfg, 2198 }, { 2199 .compatible = "qcom,sm6350-qmp-ufs-phy", 2200 .data = &sdm845_ufsphy_cfg, 2201 }, { 2202 .compatible = "qcom,sm7150-qmp-ufs-phy", 2203 .data = &sm7150_ufsphy_cfg, 2204 }, { 2205 .compatible = "qcom,sm8150-qmp-ufs-phy", 2206 .data = &sm8150_ufsphy_cfg, 2207 }, { 2208 .compatible = "qcom,sm8250-qmp-ufs-phy", 2209 .data = &sm8250_ufsphy_cfg, 2210 }, { 2211 .compatible = "qcom,sm8350-qmp-ufs-phy", 2212 .data = &sm8350_ufsphy_cfg, 2213 }, { 2214 .compatible = "qcom,sm8450-qmp-ufs-phy", 2215 .data = &sm8450_ufsphy_cfg, 2216 }, { 2217 .compatible = "qcom,sm8475-qmp-ufs-phy", 2218 .data = &sm8475_ufsphy_cfg, 2219 }, { 2220 .compatible = "qcom,sm8550-qmp-ufs-phy", 2221 .data = &sm8550_ufsphy_cfg, 2222 }, { 2223 .compatible = "qcom,sm8650-qmp-ufs-phy", 2224 .data = &sm8650_ufsphy_cfg, 2225 }, { 2226 .compatible = "qcom,sm8750-qmp-ufs-phy", 2227 .data = &sm8750_ufsphy_cfg, 2228 }, 2229 2230 { }, 2231 }; 2232 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table); 2233 2234 static struct platform_driver qmp_ufs_driver = { 2235 .probe = qmp_ufs_probe, 2236 .driver = { 2237 .name = "qcom-qmp-ufs-phy", 2238 .of_match_table = qmp_ufs_of_match_table, 2239 }, 2240 }; 2241 2242 module_platform_driver(qmp_ufs_driver); 2243 2244 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2245 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver"); 2246 MODULE_LICENSE("GPL v2"); 2247