1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 22 #include <ufs/unipro.h> 23 24 #include "phy-qcom-qmp-common.h" 25 26 #include "phy-qcom-qmp.h" 27 #include "phy-qcom-qmp-pcs-ufs-v2.h" 28 #include "phy-qcom-qmp-pcs-ufs-v3.h" 29 #include "phy-qcom-qmp-pcs-ufs-v4.h" 30 #include "phy-qcom-qmp-pcs-ufs-v5.h" 31 #include "phy-qcom-qmp-pcs-ufs-v6.h" 32 33 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" 34 #include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h" 35 36 /* QPHY_PCS_READY_STATUS bit */ 37 #define PCS_READY BIT(0) 38 39 #define PHY_INIT_COMPLETE_TIMEOUT 10000 40 41 #define NUM_OVERLAY 2 42 43 /* set of registers with offsets different per-PHY */ 44 enum qphy_reg_layout { 45 /* PCS registers */ 46 QPHY_SW_RESET, 47 QPHY_START_CTRL, 48 QPHY_PCS_READY_STATUS, 49 QPHY_PCS_POWER_DOWN_CONTROL, 50 /* Keep last to ensure regs_layout arrays are properly initialized */ 51 QPHY_LAYOUT_SIZE 52 }; 53 54 static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 55 [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, 56 [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, 57 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, 58 }; 59 60 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 61 [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, 62 [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, 63 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL, 64 }; 65 66 static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 67 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, 68 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, 69 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, 70 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, 71 }; 72 73 static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 74 [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START, 75 [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS, 76 [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET, 77 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, 78 }; 79 80 static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 81 [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, 82 [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, 83 [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET, 84 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, 85 }; 86 87 static const struct qmp_phy_init_tbl milos_ufsphy_serdes[] = { 88 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 89 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 90 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 91 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 92 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 93 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 94 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a), 95 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17), 96 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 97 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 98 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 99 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 100 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14), 101 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 102 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18), 103 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff), 104 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c), 105 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98), 106 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14), 107 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 108 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18), 109 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32), 110 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f), 111 }; 112 113 static const struct qmp_phy_init_tbl milos_ufsphy_tx[] = { 114 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), 115 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 116 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 117 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0xcc), 118 }; 119 120 static const struct qmp_phy_init_tbl milos_ufsphy_rx[] = { 121 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 122 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e), 123 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 124 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce), 125 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce), 126 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18), 127 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 128 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f), 129 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 130 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 131 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 132 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 133 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 134 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 135 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 136 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94), 137 }; 138 139 static const struct qmp_phy_init_tbl milos_ufsphy_pcs[] = { 140 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 141 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 142 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b), 143 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 144 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), 145 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 146 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 147 }; 148 149 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { 150 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 151 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), 152 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 153 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 154 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 155 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 156 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), 157 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 158 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 159 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 160 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), 161 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 162 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 163 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 164 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 165 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 166 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), 167 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 168 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 169 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 170 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 171 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 172 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 173 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 174 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 175 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 176 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 177 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 178 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 179 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 180 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 181 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 182 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 183 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 184 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 185 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 186 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 187 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 188 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 189 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 190 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 191 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 192 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 193 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 194 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 195 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 196 }; 197 198 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = { 199 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 200 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), 201 }; 202 203 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = { 204 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 205 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), 206 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), 207 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), 208 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 209 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), 210 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), 211 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), 212 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), 213 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), 214 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), 215 }; 216 217 static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = { 218 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 219 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 220 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 221 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 222 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 223 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 224 }; 225 226 static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = { 227 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 228 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 229 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 230 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 231 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 232 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 233 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 234 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 235 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 236 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 237 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 238 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 239 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 240 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d), 247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d), 248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed), 249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 262 }; 263 264 static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = { 265 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 266 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 267 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 268 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 269 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 270 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 271 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 272 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03), 273 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), 274 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), 275 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), 276 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06), 277 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), 278 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), 279 }; 280 281 static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = { 282 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 283 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 284 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 285 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 286 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 287 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 288 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 289 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 290 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 291 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 292 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 293 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 294 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 295 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 296 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), 297 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 298 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 299 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 300 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 301 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 302 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 303 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 304 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 305 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 306 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 307 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), 308 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 309 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 310 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 311 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 312 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 313 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 314 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 315 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 316 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 317 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 318 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 319 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), 320 }; 321 322 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = { 323 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 324 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 325 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 326 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 327 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 328 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 329 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 330 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 331 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 332 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 333 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 334 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 335 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 336 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 337 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 338 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 339 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), 340 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 341 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 342 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 343 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 344 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 345 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 346 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 347 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 348 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 349 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 350 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 351 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 352 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 353 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 354 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 355 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 356 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 357 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 358 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 359 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 360 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 361 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 362 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 363 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 364 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 365 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 366 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 367 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 368 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 369 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 370 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 371 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), 372 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), 373 }; 374 375 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = { 376 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), 377 }; 378 379 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = { 380 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 381 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 382 }; 383 384 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = { 385 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 386 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), 387 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), 388 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), 389 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 390 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), 391 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), 392 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), 393 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), 394 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), 395 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), 396 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 397 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 398 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), 399 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), 400 }; 401 402 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = { 403 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15), 404 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 405 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 406 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 407 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), 408 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 409 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12), 410 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), 411 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ 412 }; 413 414 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = { 415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), 421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), 428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), 429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), 430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), 431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), 438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), 440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), 441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), 442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), 443 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), 444 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), 445 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 446 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 447 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), 448 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), 449 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), 450 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), 451 }; 452 453 static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = { 454 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), 455 }; 456 457 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = { 458 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 459 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), 460 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 461 }; 462 463 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = { 464 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 465 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 466 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 467 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 468 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 469 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 470 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 471 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 472 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 473 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 474 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 475 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 476 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 477 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 478 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 479 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 480 }; 481 482 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = { 483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), 484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), 489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), 490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 491 }; 492 493 static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = { 494 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 495 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 496 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 497 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 498 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 499 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 500 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 501 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 502 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 503 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 504 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 505 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 506 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b), 507 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 508 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 509 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 510 }; 511 512 static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = { 513 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f), 514 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 515 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 516 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 517 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 518 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), 519 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 520 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 521 }; 522 523 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = { 524 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), 525 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), 526 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 527 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), 528 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 529 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 530 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), 531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 532 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 533 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 534 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), 537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), 538 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 539 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 540 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), 541 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 542 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 543 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 544 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), 545 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), 546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 547 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 548 }; 549 550 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = { 551 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), 552 }; 553 554 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { 555 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 556 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 557 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 558 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 559 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), 560 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 561 }; 562 563 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = { 564 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), 565 }; 566 567 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { 568 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 569 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 570 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 571 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 572 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 573 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 574 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 575 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 576 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), 588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), 589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), 590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), 592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 602 }; 603 604 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = { 605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 615 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 616 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), 617 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 618 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 621 }; 622 623 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { 624 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 625 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 626 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 627 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 628 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 629 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 630 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 631 }; 632 633 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { 634 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), 635 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 636 }; 637 638 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = { 639 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), 640 }; 641 642 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = { 643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), 650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), 660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 664 }; 665 666 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { 667 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), 668 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), 669 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 670 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 671 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 672 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 673 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 674 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 675 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 676 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), 677 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), 678 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), 679 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 680 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), 681 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 682 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 683 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), 684 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), 685 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), 686 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), 687 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), 688 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), 689 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 690 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 691 }; 692 693 static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = { 694 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), 695 }; 696 697 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = { 698 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 699 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 700 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 701 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 702 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), 703 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 704 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), 705 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 706 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), 707 }; 708 709 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = { 710 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), 711 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), 712 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 713 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), 714 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 715 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 716 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), 717 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 718 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), 719 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), 720 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), 721 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), 722 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 723 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 724 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 725 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 726 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 727 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 728 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), 729 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 730 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 731 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), 732 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), 733 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), 734 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), 735 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), 736 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), 737 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), 738 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), 739 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), 740 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), 741 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), 742 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), 743 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), 744 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), 745 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), 746 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 747 }; 748 749 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = { 750 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 751 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 752 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 753 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 754 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 755 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 756 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), 757 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 758 }; 759 760 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = { 761 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), 762 }; 763 764 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = { 765 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), 766 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), 767 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 768 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 769 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 770 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), 771 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), 772 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 773 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), 774 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), 775 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 776 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), 777 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), 778 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), 779 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), 780 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), 781 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), 782 }; 783 784 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { 785 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 786 }; 787 788 static const struct qmp_phy_init_tbl sm8475_ufsphy_serdes[] = { 789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 792 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 793 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 794 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 795 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 796 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 797 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18), 798 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff), 799 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c), 800 }; 801 802 static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_serdes[] = { 803 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 804 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 805 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14), 806 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98), 807 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14), 808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 809 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18), 810 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32), 811 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f), 812 }; 813 814 static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_pcs[] = { 815 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b), 816 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 817 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 818 }; 819 820 static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { 821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 827 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 828 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 829 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 830 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 831 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 832 }; 833 834 static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { 835 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), 836 }; 837 838 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = { 839 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 840 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 841 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), 842 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 843 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), 844 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 845 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 846 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 847 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 848 }; 849 850 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = { 851 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 852 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b), 853 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c), 854 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 855 }; 856 857 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { 858 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), 859 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 860 }; 861 862 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = { 863 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c), 864 }; 865 866 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { 867 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 868 869 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), 870 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), 871 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 872 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 873 874 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 875 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 876 877 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 878 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 879 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 880 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 881 }; 882 883 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = { 884 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), 885 }; 886 887 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = { 888 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), 889 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), 890 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 891 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), 892 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 893 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 894 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 895 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 896 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08), 897 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), 898 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), 899 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff), 900 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), 901 }; 902 903 static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { 904 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), 905 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 906 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 907 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 908 }; 909 910 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = { 911 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), 912 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 913 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 914 }; 915 916 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = { 917 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 918 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f), 919 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), 920 }; 921 922 static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = { 923 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 924 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 925 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 926 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 927 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 928 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 929 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f), 930 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a), 931 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17), 932 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 933 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 934 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 935 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 936 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 937 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 938 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 939 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 940 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 941 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 942 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 943 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 944 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 945 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 946 }; 947 948 static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = { 949 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x01), 950 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 951 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 952 }; 953 954 static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = { 955 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 956 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), 957 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), 958 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 959 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), 960 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 961 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 962 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 963 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 964 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e), 965 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 966 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce), 967 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce), 968 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18), 969 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 970 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f), 971 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 972 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 973 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 974 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 975 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 976 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 977 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 978 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B0, 0x24), 979 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B1, 0x24), 980 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B2, 0x20), 981 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), 982 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), 983 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f), 984 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94), 985 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa), 986 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), 987 }; 988 989 static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = { 990 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 991 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 992 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1), 993 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 994 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 995 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), 996 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e), 997 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12), 998 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15), 999 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19), 1000 }; 1001 1002 static const struct qmp_phy_init_tbl sm8650_ufsphy_g4_pcs[] = { 1003 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 1004 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 1005 }; 1006 1007 static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = { 1008 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05), 1009 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05), 1010 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d), 1011 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), 1012 }; 1013 1014 static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = { 1015 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 1016 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 1017 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 1018 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1019 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 1020 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60), 1021 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 1022 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f), 1023 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07), 1024 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20), 1025 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 1026 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40), 1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06), 1028 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1029 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1030 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 1031 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 1032 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06), 1033 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18), 1034 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14), 1035 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 1036 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 1037 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92), 1038 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1039 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 1040 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1041 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 1042 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 1043 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06), 1044 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18), 1045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14), 1046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 1047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 1048 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe), 1049 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 1050 }; 1051 1052 static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = { 1053 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00), 1054 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 1055 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17), 1056 }; 1057 1058 static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = { 1059 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1060 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0c), 1061 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04), 1062 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 1063 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07), 1064 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 1065 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 1066 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 1067 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 1068 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8e), 1069 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1070 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xce), 1071 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xce), 1072 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18), 1073 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1a), 1074 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0f), 1075 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60), 1076 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62), 1077 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9a), 1078 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xe2), 1079 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06), 1080 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1b), 1081 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1b), 1082 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98), 1083 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9b), 1084 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2a), 1085 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12), 1086 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06), 1087 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01), 1088 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93), 1089 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93), 1090 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60), 1091 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99), 1092 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5f), 1093 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92), 1094 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xe3), 1095 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06), 1096 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9b), 1097 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9b), 1098 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60), 1099 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99), 1100 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5f), 1101 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92), 1102 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xfb), 1103 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06), 1104 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1f), 1105 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94), 1106 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xfa), 1107 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30), 1108 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77), 1109 }; 1110 1111 static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = { 1112 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 1113 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 1114 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40), 1115 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 1116 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), 1117 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e), 1118 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12), 1119 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15), 1120 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19), 1121 }; 1122 1123 static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = { 1124 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 1125 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 1126 }; 1127 1128 static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = { 1129 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41), 1130 }; 1131 1132 struct qmp_ufs_offsets { 1133 u16 serdes; 1134 u16 pcs; 1135 u16 tx; 1136 u16 rx; 1137 u16 tx2; 1138 u16 rx2; 1139 }; 1140 1141 struct qmp_phy_cfg_tbls { 1142 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1143 const struct qmp_phy_init_tbl *serdes; 1144 int serdes_num; 1145 const struct qmp_phy_init_tbl *tx; 1146 int tx_num; 1147 const struct qmp_phy_init_tbl *rx; 1148 int rx_num; 1149 const struct qmp_phy_init_tbl *pcs; 1150 int pcs_num; 1151 /* Maximum supported Gear of this tbls */ 1152 u32 max_gear; 1153 }; 1154 1155 /* struct qmp_phy_cfg - per-PHY initialization config */ 1156 struct qmp_phy_cfg { 1157 int lanes; 1158 1159 const struct qmp_ufs_offsets *offsets; 1160 /* Maximum supported Gear of this config */ 1161 u32 max_supported_gear; 1162 1163 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1164 const struct qmp_phy_cfg_tbls tbls; 1165 /* Additional sequence for HS Series B */ 1166 const struct qmp_phy_cfg_tbls tbls_hs_b; 1167 /* Additional sequence for different HS Gears */ 1168 const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY]; 1169 1170 /* regulators to be requested */ 1171 const struct regulator_bulk_data *vreg_list; 1172 int num_vregs; 1173 1174 /* array of registers with different offsets */ 1175 const unsigned int *regs; 1176 1177 /* true, if PCS block has no separate SW_RESET register */ 1178 bool no_pcs_sw_reset; 1179 }; 1180 1181 struct qmp_ufs { 1182 struct device *dev; 1183 1184 const struct qmp_phy_cfg *cfg; 1185 1186 void __iomem *serdes; 1187 void __iomem *pcs; 1188 void __iomem *pcs_misc; 1189 void __iomem *tx; 1190 void __iomem *rx; 1191 void __iomem *tx2; 1192 void __iomem *rx2; 1193 1194 struct clk_bulk_data *clks; 1195 int num_clks; 1196 struct regulator_bulk_data *vregs; 1197 struct reset_control *ufs_reset; 1198 1199 struct phy *phy; 1200 u32 mode; 1201 u32 submode; 1202 }; 1203 1204 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1205 { 1206 u32 reg; 1207 1208 reg = readl(base + offset); 1209 reg |= val; 1210 writel(reg, base + offset); 1211 1212 /* ensure that above write is through */ 1213 readl(base + offset); 1214 } 1215 1216 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1217 { 1218 u32 reg; 1219 1220 reg = readl(base + offset); 1221 reg &= ~val; 1222 writel(reg, base + offset); 1223 1224 /* ensure that above write is through */ 1225 readl(base + offset); 1226 } 1227 1228 /* Regulator bulk data with load values for specific configurations */ 1229 static const struct regulator_bulk_data milos_ufsphy_vreg_l[] = { 1230 { .supply = "vdda-phy", .init_load_uA = 140120 }, 1231 { .supply = "vdda-pll", .init_load_uA = 18340 }, 1232 }; 1233 1234 static const struct regulator_bulk_data msm8996_ufsphy_vreg_l[] = { 1235 { .supply = "vdda-phy", .init_load_uA = 51400 }, 1236 { .supply = "vdda-pll", .init_load_uA = 14600 }, 1237 }; 1238 1239 static const struct regulator_bulk_data sa8775p_ufsphy_vreg_l[] = { 1240 { .supply = "vdda-phy", .init_load_uA = 137000 }, 1241 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1242 }; 1243 1244 static const struct regulator_bulk_data sc7280_ufsphy_vreg_l[] = { 1245 { .supply = "vdda-phy", .init_load_uA = 97500 }, 1246 { .supply = "vdda-pll", .init_load_uA = 18400 }, 1247 }; 1248 1249 static const struct regulator_bulk_data sc8280xp_ufsphy_vreg_l[] = { 1250 { .supply = "vdda-phy", .init_load_uA = 85700 }, 1251 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1252 }; 1253 1254 static const struct regulator_bulk_data sdm845_ufsphy_vreg_l[] = { 1255 { .supply = "vdda-phy", .init_load_uA = 51400 }, 1256 { .supply = "vdda-pll", .init_load_uA = 14600 }, 1257 }; 1258 1259 static const struct regulator_bulk_data sm6115_ufsphy_vreg_l[] = { 1260 { .supply = "vdda-phy", .init_load_uA = 51400 }, 1261 { .supply = "vdda-pll", .init_load_uA = 14200 }, 1262 }; 1263 1264 static const struct regulator_bulk_data sm7150_ufsphy_vreg_l[] = { 1265 { .supply = "vdda-phy", .init_load_uA = 62900 }, 1266 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1267 }; 1268 1269 static const struct regulator_bulk_data sm8150_ufsphy_vreg_l[] = { 1270 { .supply = "vdda-phy", .init_load_uA = 90200 }, 1271 { .supply = "vdda-pll", .init_load_uA = 19000 }, 1272 }; 1273 1274 static const struct regulator_bulk_data sm8250_ufsphy_vreg_l[] = { 1275 { .supply = "vdda-phy", .init_load_uA = 89900 }, 1276 { .supply = "vdda-pll", .init_load_uA = 18800 }, 1277 }; 1278 1279 static const struct regulator_bulk_data sm8350_ufsphy_vreg_l[] = { 1280 { .supply = "vdda-phy", .init_load_uA = 91600 }, 1281 { .supply = "vdda-pll", .init_load_uA = 19000 }, 1282 }; 1283 1284 static const struct regulator_bulk_data sm8450_ufsphy_vreg_l[] = { 1285 { .supply = "vdda-phy", .init_load_uA = 173000 }, 1286 { .supply = "vdda-pll", .init_load_uA = 24900 }, 1287 }; 1288 1289 static const struct regulator_bulk_data sm8475_ufsphy_vreg_l[] = { 1290 { .supply = "vdda-phy", .init_load_uA = 213030 }, 1291 { .supply = "vdda-pll", .init_load_uA = 18340 }, 1292 }; 1293 1294 static const struct regulator_bulk_data sm8550_ufsphy_vreg_l[] = { 1295 { .supply = "vdda-phy", .init_load_uA = 188000 }, 1296 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1297 }; 1298 1299 static const struct regulator_bulk_data sm8650_ufsphy_vreg_l[] = { 1300 { .supply = "vdda-phy", .init_load_uA = 205000 }, 1301 { .supply = "vdda-pll", .init_load_uA = 17500 }, 1302 }; 1303 1304 static const struct regulator_bulk_data sm8750_ufsphy_vreg_l[] = { 1305 { .supply = "vdda-phy", .init_load_uA = 213000 }, 1306 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1307 }; 1308 1309 static const struct qmp_ufs_offsets qmp_ufs_offsets = { 1310 .serdes = 0, 1311 .pcs = 0xc00, 1312 .tx = 0x400, 1313 .rx = 0x600, 1314 .tx2 = 0x800, 1315 .rx2 = 0xa00, 1316 }; 1317 1318 static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = { 1319 .serdes = 0, 1320 .pcs = 0x0400, 1321 .tx = 0x1000, 1322 .rx = 0x1200, 1323 .tx2 = 0x1800, 1324 .rx2 = 0x1a00, 1325 }; 1326 1327 static const struct qmp_phy_cfg milos_ufsphy_cfg = { 1328 .lanes = 2, 1329 1330 .offsets = &qmp_ufs_offsets_v6, 1331 .max_supported_gear = UFS_HS_G4, 1332 1333 .tbls = { 1334 .serdes = milos_ufsphy_serdes, 1335 .serdes_num = ARRAY_SIZE(milos_ufsphy_serdes), 1336 .tx = milos_ufsphy_tx, 1337 .tx_num = ARRAY_SIZE(milos_ufsphy_tx), 1338 .rx = milos_ufsphy_rx, 1339 .rx_num = ARRAY_SIZE(milos_ufsphy_rx), 1340 .pcs = milos_ufsphy_pcs, 1341 .pcs_num = ARRAY_SIZE(milos_ufsphy_pcs), 1342 }, 1343 .tbls_hs_b = { 1344 .serdes = sm8550_ufsphy_hs_b_serdes, 1345 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), 1346 }, 1347 1348 .vreg_list = milos_ufsphy_vreg_l, 1349 .num_vregs = ARRAY_SIZE(milos_ufsphy_vreg_l), 1350 .regs = ufsphy_v6_regs_layout, 1351 }; 1352 1353 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { 1354 .lanes = 1, 1355 1356 .offsets = &qmp_ufs_offsets, 1357 .max_supported_gear = UFS_HS_G3, 1358 1359 .tbls = { 1360 .serdes = msm8996_ufsphy_serdes, 1361 .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes), 1362 .tx = msm8996_ufsphy_tx, 1363 .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx), 1364 .rx = msm8996_ufsphy_rx, 1365 .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx), 1366 }, 1367 1368 .vreg_list = msm8996_ufsphy_vreg_l, 1369 .num_vregs = ARRAY_SIZE(msm8996_ufsphy_vreg_l), 1370 1371 .regs = ufsphy_v2_regs_layout, 1372 1373 .no_pcs_sw_reset = true, 1374 }; 1375 1376 static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = { 1377 .lanes = 2, 1378 1379 .offsets = &qmp_ufs_offsets, 1380 .max_supported_gear = UFS_HS_G4, 1381 1382 .tbls = { 1383 .serdes = sm8350_ufsphy_serdes, 1384 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1385 .tx = sm8350_ufsphy_tx, 1386 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1387 .rx = sm8350_ufsphy_rx, 1388 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1389 .pcs = sm8350_ufsphy_pcs, 1390 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1391 }, 1392 .tbls_hs_b = { 1393 .serdes = sm8350_ufsphy_hs_b_serdes, 1394 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1395 }, 1396 .tbls_hs_overlay[0] = { 1397 .tx = sm8350_ufsphy_g4_tx, 1398 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1399 .rx = sm8350_ufsphy_g4_rx, 1400 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1401 .pcs = sm8350_ufsphy_g4_pcs, 1402 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1403 .max_gear = UFS_HS_G4, 1404 }, 1405 .vreg_list = sa8775p_ufsphy_vreg_l, 1406 .num_vregs = ARRAY_SIZE(sa8775p_ufsphy_vreg_l), 1407 .regs = ufsphy_v5_regs_layout, 1408 }; 1409 1410 static const struct qmp_phy_cfg sc7280_ufsphy_cfg = { 1411 .lanes = 2, 1412 1413 .offsets = &qmp_ufs_offsets, 1414 .max_supported_gear = UFS_HS_G4, 1415 1416 .tbls = { 1417 .serdes = sm8150_ufsphy_serdes, 1418 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1419 .tx = sc7280_ufsphy_tx, 1420 .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx), 1421 .rx = sc7280_ufsphy_rx, 1422 .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx), 1423 .pcs = sc7280_ufsphy_pcs, 1424 .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs), 1425 }, 1426 .tbls_hs_b = { 1427 .serdes = sm8150_ufsphy_hs_b_serdes, 1428 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1429 }, 1430 .tbls_hs_overlay[0] = { 1431 .tx = sm8250_ufsphy_hs_g4_tx, 1432 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), 1433 .rx = sc7280_ufsphy_hs_g4_rx, 1434 .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx), 1435 .pcs = sm8150_ufsphy_hs_g4_pcs, 1436 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1437 .max_gear = UFS_HS_G4, 1438 }, 1439 .vreg_list = sc7280_ufsphy_vreg_l, 1440 .num_vregs = ARRAY_SIZE(sc7280_ufsphy_vreg_l), 1441 .regs = ufsphy_v4_regs_layout, 1442 }; 1443 1444 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { 1445 .lanes = 2, 1446 1447 .offsets = &qmp_ufs_offsets, 1448 .max_supported_gear = UFS_HS_G4, 1449 1450 .tbls = { 1451 .serdes = sm8350_ufsphy_serdes, 1452 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1453 .tx = sm8350_ufsphy_tx, 1454 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1455 .rx = sm8350_ufsphy_rx, 1456 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1457 .pcs = sm8350_ufsphy_pcs, 1458 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1459 }, 1460 .tbls_hs_b = { 1461 .serdes = sm8350_ufsphy_hs_b_serdes, 1462 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1463 }, 1464 .tbls_hs_overlay[0] = { 1465 .tx = sm8350_ufsphy_g4_tx, 1466 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1467 .rx = sm8350_ufsphy_g4_rx, 1468 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1469 .pcs = sm8350_ufsphy_g4_pcs, 1470 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1471 .max_gear = UFS_HS_G4, 1472 }, 1473 .vreg_list = sc8280xp_ufsphy_vreg_l, 1474 .num_vregs = ARRAY_SIZE(sc8280xp_ufsphy_vreg_l), 1475 .regs = ufsphy_v5_regs_layout, 1476 }; 1477 1478 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { 1479 .lanes = 2, 1480 1481 .offsets = &qmp_ufs_offsets, 1482 .max_supported_gear = UFS_HS_G3, 1483 1484 .tbls = { 1485 .serdes = sdm845_ufsphy_serdes, 1486 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 1487 .tx = sdm845_ufsphy_tx, 1488 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), 1489 .rx = sdm845_ufsphy_rx, 1490 .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx), 1491 .pcs = sdm845_ufsphy_pcs, 1492 .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs), 1493 }, 1494 .tbls_hs_b = { 1495 .serdes = sdm845_ufsphy_hs_b_serdes, 1496 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 1497 }, 1498 .vreg_list = sdm845_ufsphy_vreg_l, 1499 .num_vregs = ARRAY_SIZE(sdm845_ufsphy_vreg_l), 1500 .regs = ufsphy_v3_regs_layout, 1501 1502 .no_pcs_sw_reset = true, 1503 }; 1504 1505 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { 1506 .lanes = 1, 1507 1508 .offsets = &qmp_ufs_offsets, 1509 .max_supported_gear = UFS_HS_G3, 1510 1511 .tbls = { 1512 .serdes = sm6115_ufsphy_serdes, 1513 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes), 1514 .tx = sm6115_ufsphy_tx, 1515 .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx), 1516 .rx = sm6115_ufsphy_rx, 1517 .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx), 1518 .pcs = sm6115_ufsphy_pcs, 1519 .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs), 1520 }, 1521 .tbls_hs_b = { 1522 .serdes = sm6115_ufsphy_hs_b_serdes, 1523 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), 1524 }, 1525 .vreg_list = sm6115_ufsphy_vreg_l, 1526 .num_vregs = ARRAY_SIZE(sm6115_ufsphy_vreg_l), 1527 .regs = ufsphy_v2_regs_layout, 1528 1529 .no_pcs_sw_reset = true, 1530 }; 1531 1532 static const struct qmp_phy_cfg sm7150_ufsphy_cfg = { 1533 .lanes = 1, 1534 1535 .offsets = &qmp_ufs_offsets, 1536 .max_supported_gear = UFS_HS_G3, 1537 1538 .tbls = { 1539 .serdes = sdm845_ufsphy_serdes, 1540 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 1541 .tx = sdm845_ufsphy_tx, 1542 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), 1543 .rx = sm7150_ufsphy_rx, 1544 .rx_num = ARRAY_SIZE(sm7150_ufsphy_rx), 1545 .pcs = sm7150_ufsphy_pcs, 1546 .pcs_num = ARRAY_SIZE(sm7150_ufsphy_pcs), 1547 }, 1548 .tbls_hs_b = { 1549 .serdes = sdm845_ufsphy_hs_b_serdes, 1550 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 1551 }, 1552 .vreg_list = sm7150_ufsphy_vreg_l, 1553 .num_vregs = ARRAY_SIZE(sm7150_ufsphy_vreg_l), 1554 .regs = ufsphy_v3_regs_layout, 1555 1556 .no_pcs_sw_reset = true, 1557 }; 1558 1559 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { 1560 .lanes = 2, 1561 1562 .offsets = &qmp_ufs_offsets, 1563 .max_supported_gear = UFS_HS_G4, 1564 1565 .tbls = { 1566 .serdes = sm8150_ufsphy_serdes, 1567 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1568 .tx = sm8150_ufsphy_tx, 1569 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 1570 .rx = sm8150_ufsphy_rx, 1571 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 1572 .pcs = sm8150_ufsphy_pcs, 1573 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 1574 }, 1575 .tbls_hs_b = { 1576 .serdes = sm8150_ufsphy_hs_b_serdes, 1577 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1578 }, 1579 .tbls_hs_overlay[0] = { 1580 .tx = sm8150_ufsphy_hs_g4_tx, 1581 .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), 1582 .rx = sm8150_ufsphy_hs_g4_rx, 1583 .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), 1584 .pcs = sm8150_ufsphy_hs_g4_pcs, 1585 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1586 .max_gear = UFS_HS_G4, 1587 }, 1588 .vreg_list = sm8150_ufsphy_vreg_l, 1589 .num_vregs = ARRAY_SIZE(sm8150_ufsphy_vreg_l), 1590 .regs = ufsphy_v4_regs_layout, 1591 }; 1592 1593 static const struct qmp_phy_cfg sm8250_ufsphy_cfg = { 1594 .lanes = 2, 1595 1596 .offsets = &qmp_ufs_offsets, 1597 .max_supported_gear = UFS_HS_G4, 1598 1599 .tbls = { 1600 .serdes = sm8150_ufsphy_serdes, 1601 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1602 .tx = sm8150_ufsphy_tx, 1603 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 1604 .rx = sm8150_ufsphy_rx, 1605 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 1606 .pcs = sm8150_ufsphy_pcs, 1607 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 1608 }, 1609 .tbls_hs_b = { 1610 .serdes = sm8150_ufsphy_hs_b_serdes, 1611 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1612 }, 1613 .tbls_hs_overlay[0] = { 1614 .tx = sm8250_ufsphy_hs_g4_tx, 1615 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), 1616 .rx = sm8250_ufsphy_hs_g4_rx, 1617 .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), 1618 .pcs = sm8150_ufsphy_hs_g4_pcs, 1619 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1620 .max_gear = UFS_HS_G4, 1621 }, 1622 .vreg_list = sm8250_ufsphy_vreg_l, 1623 .num_vregs = ARRAY_SIZE(sm8250_ufsphy_vreg_l), 1624 .regs = ufsphy_v4_regs_layout, 1625 }; 1626 1627 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { 1628 .lanes = 2, 1629 1630 .offsets = &qmp_ufs_offsets, 1631 .max_supported_gear = UFS_HS_G4, 1632 1633 .tbls = { 1634 .serdes = sm8350_ufsphy_serdes, 1635 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1636 .tx = sm8350_ufsphy_tx, 1637 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1638 .rx = sm8350_ufsphy_rx, 1639 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1640 .pcs = sm8350_ufsphy_pcs, 1641 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1642 }, 1643 .tbls_hs_b = { 1644 .serdes = sm8350_ufsphy_hs_b_serdes, 1645 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1646 }, 1647 .tbls_hs_overlay[0] = { 1648 .tx = sm8350_ufsphy_g4_tx, 1649 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1650 .rx = sm8350_ufsphy_g4_rx, 1651 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1652 .pcs = sm8350_ufsphy_g4_pcs, 1653 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1654 .max_gear = UFS_HS_G4, 1655 }, 1656 .vreg_list = sm8350_ufsphy_vreg_l, 1657 .num_vregs = ARRAY_SIZE(sm8350_ufsphy_vreg_l), 1658 .regs = ufsphy_v5_regs_layout, 1659 }; 1660 1661 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { 1662 .lanes = 2, 1663 1664 .offsets = &qmp_ufs_offsets, 1665 .max_supported_gear = UFS_HS_G4, 1666 1667 .tbls = { 1668 .serdes = sm8350_ufsphy_serdes, 1669 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1670 .tx = sm8350_ufsphy_tx, 1671 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1672 .rx = sm8350_ufsphy_rx, 1673 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1674 .pcs = sm8350_ufsphy_pcs, 1675 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1676 }, 1677 .tbls_hs_b = { 1678 .serdes = sm8350_ufsphy_hs_b_serdes, 1679 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1680 }, 1681 .tbls_hs_overlay[0] = { 1682 .tx = sm8350_ufsphy_g4_tx, 1683 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1684 .rx = sm8350_ufsphy_g4_rx, 1685 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1686 .pcs = sm8350_ufsphy_g4_pcs, 1687 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1688 .max_gear = UFS_HS_G4, 1689 }, 1690 .vreg_list = sm8450_ufsphy_vreg_l, 1691 .num_vregs = ARRAY_SIZE(sm8450_ufsphy_vreg_l), 1692 .regs = ufsphy_v5_regs_layout, 1693 }; 1694 1695 static const struct qmp_phy_cfg sm8475_ufsphy_cfg = { 1696 .lanes = 2, 1697 1698 .offsets = &qmp_ufs_offsets_v6, 1699 .max_supported_gear = UFS_HS_G4, 1700 1701 .tbls = { 1702 .serdes = sm8475_ufsphy_serdes, 1703 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_serdes), 1704 .tx = sm8550_ufsphy_tx, 1705 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), 1706 .rx = sm8550_ufsphy_rx, 1707 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), 1708 .pcs = sm8550_ufsphy_pcs, 1709 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), 1710 }, 1711 .tbls_hs_b = { 1712 .serdes = sm8550_ufsphy_hs_b_serdes, 1713 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), 1714 }, 1715 .tbls_hs_overlay[0] = { 1716 .serdes = sm8475_ufsphy_g4_serdes, 1717 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_g4_serdes), 1718 .tx = sm8550_ufsphy_g4_tx, 1719 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx), 1720 .rx = sm8550_ufsphy_g4_rx, 1721 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx), 1722 .pcs = sm8475_ufsphy_g4_pcs, 1723 .pcs_num = ARRAY_SIZE(sm8475_ufsphy_g4_pcs), 1724 .max_gear = UFS_HS_G4, 1725 }, 1726 .vreg_list = sm8475_ufsphy_vreg_l, 1727 .num_vregs = ARRAY_SIZE(sm8475_ufsphy_vreg_l), 1728 .regs = ufsphy_v6_regs_layout, 1729 }; 1730 1731 static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { 1732 .lanes = 2, 1733 1734 .offsets = &qmp_ufs_offsets_v6, 1735 .max_supported_gear = UFS_HS_G5, 1736 1737 .tbls = { 1738 .serdes = sm8550_ufsphy_serdes, 1739 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), 1740 .tx = sm8550_ufsphy_tx, 1741 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), 1742 .rx = sm8550_ufsphy_rx, 1743 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), 1744 .pcs = sm8550_ufsphy_pcs, 1745 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), 1746 }, 1747 .tbls_hs_b = { 1748 .serdes = sm8550_ufsphy_hs_b_serdes, 1749 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), 1750 }, 1751 .tbls_hs_overlay[0] = { 1752 .serdes = sm8550_ufsphy_g4_serdes, 1753 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes), 1754 .tx = sm8550_ufsphy_g4_tx, 1755 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx), 1756 .rx = sm8550_ufsphy_g4_rx, 1757 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx), 1758 .pcs = sm8550_ufsphy_g4_pcs, 1759 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs), 1760 .max_gear = UFS_HS_G4, 1761 }, 1762 .tbls_hs_overlay[1] = { 1763 .serdes = sm8550_ufsphy_g5_serdes, 1764 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes), 1765 .rx = sm8550_ufsphy_g5_rx, 1766 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx), 1767 .pcs = sm8550_ufsphy_g5_pcs, 1768 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs), 1769 .max_gear = UFS_HS_G5, 1770 }, 1771 .vreg_list = sm8550_ufsphy_vreg_l, 1772 .num_vregs = ARRAY_SIZE(sm8550_ufsphy_vreg_l), 1773 .regs = ufsphy_v6_regs_layout, 1774 }; 1775 1776 static const struct qmp_phy_cfg sm8650_ufsphy_cfg = { 1777 .lanes = 2, 1778 1779 .offsets = &qmp_ufs_offsets_v6, 1780 .max_supported_gear = UFS_HS_G5, 1781 1782 .tbls = { 1783 .serdes = sm8650_ufsphy_serdes, 1784 .serdes_num = ARRAY_SIZE(sm8650_ufsphy_serdes), 1785 .tx = sm8650_ufsphy_tx, 1786 .tx_num = ARRAY_SIZE(sm8650_ufsphy_tx), 1787 .rx = sm8650_ufsphy_rx, 1788 .rx_num = ARRAY_SIZE(sm8650_ufsphy_rx), 1789 .pcs = sm8650_ufsphy_pcs, 1790 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs), 1791 }, 1792 .tbls_hs_overlay[0] = { 1793 .pcs = sm8650_ufsphy_g4_pcs, 1794 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g4_pcs), 1795 .max_gear = UFS_HS_G4, 1796 }, 1797 .tbls_hs_overlay[1] = { 1798 .pcs = sm8650_ufsphy_g5_pcs, 1799 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs), 1800 .max_gear = UFS_HS_G5, 1801 }, 1802 1803 .vreg_list = sm8650_ufsphy_vreg_l, 1804 .num_vregs = ARRAY_SIZE(sm8650_ufsphy_vreg_l), 1805 .regs = ufsphy_v6_regs_layout, 1806 }; 1807 1808 static const struct qmp_phy_cfg sm8750_ufsphy_cfg = { 1809 .lanes = 2, 1810 1811 .offsets = &qmp_ufs_offsets_v6, 1812 .max_supported_gear = UFS_HS_G5, 1813 1814 .tbls = { 1815 .serdes = sm8750_ufsphy_serdes, 1816 .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes), 1817 .tx = sm8750_ufsphy_tx, 1818 .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx), 1819 .rx = sm8750_ufsphy_rx, 1820 .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx), 1821 .pcs = sm8750_ufsphy_pcs, 1822 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs), 1823 }, 1824 1825 .tbls_hs_b = { 1826 .pcs = sm8750_ufsphy_hs_b_pcs, 1827 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs), 1828 }, 1829 1830 .tbls_hs_overlay[0] = { 1831 .pcs = sm8750_ufsphy_g4_pcs, 1832 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs), 1833 .max_gear = UFS_HS_G4, 1834 }, 1835 .tbls_hs_overlay[1] = { 1836 .pcs = sm8650_ufsphy_g5_pcs, 1837 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs), 1838 .max_gear = UFS_HS_G5, 1839 }, 1840 1841 .vreg_list = sm8750_ufsphy_vreg_l, 1842 .num_vregs = ARRAY_SIZE(sm8750_ufsphy_vreg_l), 1843 .regs = ufsphy_v6_regs_layout, 1844 1845 }; 1846 1847 static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1848 { 1849 void __iomem *serdes = qmp->serdes; 1850 1851 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 1852 } 1853 1854 static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1855 { 1856 const struct qmp_phy_cfg *cfg = qmp->cfg; 1857 void __iomem *tx = qmp->tx; 1858 void __iomem *rx = qmp->rx; 1859 1860 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); 1861 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); 1862 1863 if (cfg->lanes >= 2) { 1864 qmp_configure_lane(qmp->dev, qmp->tx2, tbls->tx, tbls->tx_num, 2); 1865 qmp_configure_lane(qmp->dev, qmp->rx2, tbls->rx, tbls->rx_num, 2); 1866 } 1867 } 1868 1869 static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1870 { 1871 void __iomem *pcs = qmp->pcs; 1872 1873 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 1874 } 1875 1876 static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) 1877 { 1878 u32 max_gear, floor_max_gear = cfg->max_supported_gear; 1879 int idx, ret = -EINVAL; 1880 1881 for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) { 1882 max_gear = cfg->tbls_hs_overlay[idx].max_gear; 1883 1884 /* Skip if the table is not available */ 1885 if (max_gear == 0) 1886 continue; 1887 1888 /* Direct matching, bail */ 1889 if (qmp->submode == max_gear) 1890 return idx; 1891 1892 /* If no direct matching, the lowest gear is the best matching */ 1893 if (max_gear < floor_max_gear) { 1894 ret = idx; 1895 floor_max_gear = max_gear; 1896 } 1897 } 1898 1899 return ret; 1900 } 1901 1902 static void qmp_ufs_init_all(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1903 { 1904 qmp_ufs_serdes_init(qmp, tbls); 1905 qmp_ufs_lanes_init(qmp, tbls); 1906 qmp_ufs_pcs_init(qmp, tbls); 1907 } 1908 1909 static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) 1910 { 1911 int i; 1912 1913 qmp_ufs_init_all(qmp, &cfg->tbls); 1914 1915 i = qmp_ufs_get_gear_overlay(qmp, cfg); 1916 if (i >= 0) { 1917 qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]); 1918 } 1919 1920 if (qmp->mode == PHY_MODE_UFS_HS_B) 1921 qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); 1922 } 1923 1924 static int qmp_ufs_power_on(struct phy *phy) 1925 { 1926 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1927 const struct qmp_phy_cfg *cfg = qmp->cfg; 1928 void __iomem *pcs = qmp->pcs; 1929 int ret; 1930 1931 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1932 if (ret) { 1933 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1934 return ret; 1935 } 1936 1937 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 1938 if (ret) 1939 goto err_disable_regulators; 1940 1941 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1942 return 0; 1943 1944 err_disable_regulators: 1945 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1946 return ret; 1947 } 1948 1949 static int qmp_ufs_phy_calibrate(struct phy *phy) 1950 { 1951 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1952 const struct qmp_phy_cfg *cfg = qmp->cfg; 1953 void __iomem *pcs = qmp->pcs; 1954 void __iomem *status; 1955 unsigned int val; 1956 int ret; 1957 1958 ret = reset_control_assert(qmp->ufs_reset); 1959 if (ret) 1960 return ret; 1961 1962 qmp_ufs_init_registers(qmp, cfg); 1963 1964 ret = reset_control_deassert(qmp->ufs_reset); 1965 if (ret) 1966 return ret; 1967 1968 /* Pull PHY out of reset state */ 1969 if (!cfg->no_pcs_sw_reset) 1970 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1971 1972 /* start SerDes */ 1973 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); 1974 1975 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 1976 ret = readl_poll_timeout(status, val, (val & PCS_READY), 200, 1977 PHY_INIT_COMPLETE_TIMEOUT); 1978 if (ret) { 1979 dev_err(qmp->dev, "phy initialization timed-out\n"); 1980 return ret; 1981 } 1982 1983 return 0; 1984 } 1985 1986 static int qmp_ufs_power_off(struct phy *phy) 1987 { 1988 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1989 const struct qmp_phy_cfg *cfg = qmp->cfg; 1990 1991 /* Put PHY into POWER DOWN state: active low */ 1992 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1993 SW_PWRDN); 1994 1995 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 1996 1997 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1998 1999 return 0; 2000 } 2001 2002 static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2003 { 2004 struct qmp_ufs *qmp = phy_get_drvdata(phy); 2005 const struct qmp_phy_cfg *cfg = qmp->cfg; 2006 2007 if (submode > cfg->max_supported_gear || submode == 0) { 2008 dev_err(qmp->dev, "Invalid PHY submode %d\n", submode); 2009 return -EINVAL; 2010 } 2011 2012 qmp->mode = mode; 2013 qmp->submode = submode; 2014 2015 return 0; 2016 } 2017 2018 static int qmp_ufs_phy_init(struct phy *phy) 2019 { 2020 struct qmp_ufs *qmp = phy_get_drvdata(phy); 2021 const struct qmp_phy_cfg *cfg = qmp->cfg; 2022 int ret; 2023 2024 if (!cfg->no_pcs_sw_reset) 2025 return 0; 2026 2027 /* 2028 * Get UFS reset, which is delayed until now to avoid a 2029 * circular dependency where UFS needs its PHY, but the PHY 2030 * needs this UFS reset. 2031 */ 2032 if (!qmp->ufs_reset) { 2033 qmp->ufs_reset = 2034 devm_reset_control_get_exclusive(qmp->dev, "ufsphy"); 2035 2036 if (IS_ERR(qmp->ufs_reset)) { 2037 ret = PTR_ERR(qmp->ufs_reset); 2038 dev_err(qmp->dev, "failed to get PHY reset: %d\n", ret); 2039 qmp->ufs_reset = NULL; 2040 return ret; 2041 } 2042 } 2043 2044 return 0; 2045 } 2046 2047 static const struct phy_ops qcom_qmp_ufs_phy_ops = { 2048 .init = qmp_ufs_phy_init, 2049 .power_on = qmp_ufs_power_on, 2050 .power_off = qmp_ufs_power_off, 2051 .calibrate = qmp_ufs_phy_calibrate, 2052 .set_mode = qmp_ufs_set_mode, 2053 .owner = THIS_MODULE, 2054 }; 2055 2056 2057 static int qmp_ufs_clk_init(struct qmp_ufs *qmp) 2058 { 2059 struct device *dev = qmp->dev; 2060 2061 qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks); 2062 if (qmp->num_clks < 0) 2063 return qmp->num_clks; 2064 2065 return 0; 2066 } 2067 2068 static void qmp_ufs_clk_release_provider(void *res) 2069 { 2070 of_clk_del_provider(res); 2071 } 2072 2073 #define UFS_SYMBOL_CLOCKS 3 2074 2075 static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np) 2076 { 2077 struct clk_hw_onecell_data *clk_data; 2078 struct clk_hw *hw; 2079 char name[64]; 2080 int ret; 2081 2082 clk_data = devm_kzalloc(qmp->dev, 2083 struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS), 2084 GFP_KERNEL); 2085 if (!clk_data) 2086 return -ENOMEM; 2087 2088 clk_data->num = UFS_SYMBOL_CLOCKS; 2089 2090 snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev)); 2091 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 2092 if (IS_ERR(hw)) 2093 return PTR_ERR(hw); 2094 2095 clk_data->hws[0] = hw; 2096 2097 snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev)); 2098 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 2099 if (IS_ERR(hw)) 2100 return PTR_ERR(hw); 2101 2102 clk_data->hws[1] = hw; 2103 2104 snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev)); 2105 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 2106 if (IS_ERR(hw)) 2107 return PTR_ERR(hw); 2108 2109 clk_data->hws[2] = hw; 2110 2111 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 2112 if (ret) 2113 return ret; 2114 2115 /* 2116 * Roll a devm action because the clock provider can be a child node. 2117 */ 2118 return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np); 2119 } 2120 2121 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np) 2122 { 2123 struct platform_device *pdev = to_platform_device(qmp->dev); 2124 const struct qmp_phy_cfg *cfg = qmp->cfg; 2125 struct device *dev = qmp->dev; 2126 2127 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2128 if (IS_ERR(qmp->serdes)) 2129 return PTR_ERR(qmp->serdes); 2130 2131 /* 2132 * Get memory resources for the PHY: 2133 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2134 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2135 * For single lane PHYs: pcs_misc (optional) -> 3. 2136 */ 2137 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2138 if (IS_ERR(qmp->tx)) 2139 return PTR_ERR(qmp->tx); 2140 2141 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2142 if (IS_ERR(qmp->rx)) 2143 return PTR_ERR(qmp->rx); 2144 2145 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 2146 if (IS_ERR(qmp->pcs)) 2147 return PTR_ERR(qmp->pcs); 2148 2149 if (cfg->lanes >= 2) { 2150 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2151 if (IS_ERR(qmp->tx2)) 2152 return PTR_ERR(qmp->tx2); 2153 2154 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2155 if (IS_ERR(qmp->rx2)) 2156 return PTR_ERR(qmp->rx2); 2157 2158 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2159 } else { 2160 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2161 } 2162 2163 if (IS_ERR(qmp->pcs_misc)) 2164 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2165 2166 return 0; 2167 } 2168 2169 static int qmp_ufs_parse_dt(struct qmp_ufs *qmp) 2170 { 2171 struct platform_device *pdev = to_platform_device(qmp->dev); 2172 const struct qmp_phy_cfg *cfg = qmp->cfg; 2173 const struct qmp_ufs_offsets *offs = cfg->offsets; 2174 void __iomem *base; 2175 2176 if (!offs) 2177 return -EINVAL; 2178 2179 base = devm_platform_ioremap_resource(pdev, 0); 2180 if (IS_ERR(base)) 2181 return PTR_ERR(base); 2182 2183 qmp->serdes = base + offs->serdes; 2184 qmp->pcs = base + offs->pcs; 2185 qmp->tx = base + offs->tx; 2186 qmp->rx = base + offs->rx; 2187 2188 if (cfg->lanes >= 2) { 2189 qmp->tx2 = base + offs->tx2; 2190 qmp->rx2 = base + offs->rx2; 2191 } 2192 2193 return 0; 2194 } 2195 2196 static int qmp_ufs_probe(struct platform_device *pdev) 2197 { 2198 struct device *dev = &pdev->dev; 2199 struct phy_provider *phy_provider; 2200 struct device_node *np; 2201 struct qmp_ufs *qmp; 2202 int ret; 2203 2204 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2205 if (!qmp) 2206 return -ENOMEM; 2207 2208 qmp->dev = dev; 2209 2210 qmp->cfg = of_device_get_match_data(dev); 2211 if (!qmp->cfg) 2212 return -EINVAL; 2213 2214 ret = qmp_ufs_clk_init(qmp); 2215 if (ret) 2216 return ret; 2217 2218 ret = devm_regulator_bulk_get_const(dev, qmp->cfg->num_vregs, 2219 qmp->cfg->vreg_list, 2220 &qmp->vregs); 2221 if (ret) 2222 return ret; 2223 2224 /* Check for legacy binding with child node. */ 2225 np = of_get_next_available_child(dev->of_node, NULL); 2226 if (np) { 2227 ret = qmp_ufs_parse_dt_legacy(qmp, np); 2228 } else { 2229 np = of_node_get(dev->of_node); 2230 ret = qmp_ufs_parse_dt(qmp); 2231 } 2232 if (ret) 2233 goto err_node_put; 2234 2235 ret = qmp_ufs_register_clocks(qmp, np); 2236 if (ret) 2237 goto err_node_put; 2238 2239 qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops); 2240 if (IS_ERR(qmp->phy)) { 2241 ret = PTR_ERR(qmp->phy); 2242 dev_err(dev, "failed to create PHY: %d\n", ret); 2243 goto err_node_put; 2244 } 2245 2246 phy_set_drvdata(qmp->phy, qmp); 2247 2248 of_node_put(np); 2249 2250 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2251 2252 return PTR_ERR_OR_ZERO(phy_provider); 2253 2254 err_node_put: 2255 of_node_put(np); 2256 return ret; 2257 } 2258 2259 static const struct of_device_id qmp_ufs_of_match_table[] = { 2260 { 2261 .compatible = "qcom,milos-qmp-ufs-phy", 2262 .data = &milos_ufsphy_cfg, 2263 }, { 2264 .compatible = "qcom,msm8996-qmp-ufs-phy", 2265 .data = &msm8996_ufsphy_cfg, 2266 }, { 2267 .compatible = "qcom,msm8998-qmp-ufs-phy", 2268 .data = &sdm845_ufsphy_cfg, 2269 }, { 2270 .compatible = "qcom,sa8775p-qmp-ufs-phy", 2271 .data = &sa8775p_ufsphy_cfg, 2272 }, { 2273 .compatible = "qcom,sc7180-qmp-ufs-phy", 2274 .data = &sm7150_ufsphy_cfg, 2275 }, { 2276 .compatible = "qcom,sc7280-qmp-ufs-phy", 2277 .data = &sc7280_ufsphy_cfg, 2278 }, { 2279 .compatible = "qcom,sc8180x-qmp-ufs-phy", 2280 .data = &sm8150_ufsphy_cfg, 2281 }, { 2282 .compatible = "qcom,sc8280xp-qmp-ufs-phy", 2283 .data = &sc8280xp_ufsphy_cfg, 2284 }, { 2285 .compatible = "qcom,sdm845-qmp-ufs-phy", 2286 .data = &sdm845_ufsphy_cfg, 2287 }, { 2288 .compatible = "qcom,sm6115-qmp-ufs-phy", 2289 .data = &sm6115_ufsphy_cfg, 2290 }, { 2291 .compatible = "qcom,sm6125-qmp-ufs-phy", 2292 .data = &sm6115_ufsphy_cfg, 2293 }, { 2294 .compatible = "qcom,sm6350-qmp-ufs-phy", 2295 .data = &sdm845_ufsphy_cfg, 2296 }, { 2297 .compatible = "qcom,sm7150-qmp-ufs-phy", 2298 .data = &sm7150_ufsphy_cfg, 2299 }, { 2300 .compatible = "qcom,sm8150-qmp-ufs-phy", 2301 .data = &sm8150_ufsphy_cfg, 2302 }, { 2303 .compatible = "qcom,sm8250-qmp-ufs-phy", 2304 .data = &sm8250_ufsphy_cfg, 2305 }, { 2306 .compatible = "qcom,sm8350-qmp-ufs-phy", 2307 .data = &sm8350_ufsphy_cfg, 2308 }, { 2309 .compatible = "qcom,sm8450-qmp-ufs-phy", 2310 .data = &sm8450_ufsphy_cfg, 2311 }, { 2312 .compatible = "qcom,sm8475-qmp-ufs-phy", 2313 .data = &sm8475_ufsphy_cfg, 2314 }, { 2315 .compatible = "qcom,sm8550-qmp-ufs-phy", 2316 .data = &sm8550_ufsphy_cfg, 2317 }, { 2318 .compatible = "qcom,sm8650-qmp-ufs-phy", 2319 .data = &sm8650_ufsphy_cfg, 2320 }, { 2321 .compatible = "qcom,sm8750-qmp-ufs-phy", 2322 .data = &sm8750_ufsphy_cfg, 2323 }, 2324 2325 { }, 2326 }; 2327 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table); 2328 2329 static struct platform_driver qmp_ufs_driver = { 2330 .probe = qmp_ufs_probe, 2331 .driver = { 2332 .name = "qcom-qmp-ufs-phy", 2333 .of_match_table = qmp_ufs_of_match_table, 2334 }, 2335 }; 2336 2337 module_platform_driver(qmp_ufs_driver); 2338 2339 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2340 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver"); 2341 MODULE_LICENSE("GPL v2"); 2342