1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 22 #include <ufs/unipro.h> 23 24 #include "phy-qcom-qmp-common.h" 25 26 #include "phy-qcom-qmp.h" 27 #include "phy-qcom-qmp-pcs-ufs-v2.h" 28 #include "phy-qcom-qmp-pcs-ufs-v3.h" 29 #include "phy-qcom-qmp-pcs-ufs-v4.h" 30 #include "phy-qcom-qmp-pcs-ufs-v5.h" 31 #include "phy-qcom-qmp-pcs-ufs-v6.h" 32 33 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" 34 35 /* QPHY_PCS_READY_STATUS bit */ 36 #define PCS_READY BIT(0) 37 38 #define PHY_INIT_COMPLETE_TIMEOUT 10000 39 40 #define NUM_OVERLAY 2 41 42 /* set of registers with offsets different per-PHY */ 43 enum qphy_reg_layout { 44 /* PCS registers */ 45 QPHY_SW_RESET, 46 QPHY_START_CTRL, 47 QPHY_PCS_READY_STATUS, 48 QPHY_PCS_POWER_DOWN_CONTROL, 49 /* Keep last to ensure regs_layout arrays are properly initialized */ 50 QPHY_LAYOUT_SIZE 51 }; 52 53 static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 54 [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, 55 [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, 56 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, 57 }; 58 59 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 60 [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, 61 [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, 62 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL, 63 }; 64 65 static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 66 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, 67 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, 68 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, 69 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, 70 }; 71 72 static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 73 [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START, 74 [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS, 75 [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET, 76 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, 77 }; 78 79 static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 80 [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, 81 [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, 82 [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET, 83 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, 84 }; 85 86 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { 87 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 88 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), 89 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 90 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 91 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 92 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 93 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), 94 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 95 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 96 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 97 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), 98 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 99 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 100 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 101 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 102 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 103 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), 104 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 105 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 106 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 107 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 108 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 109 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 110 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 111 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 112 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 113 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 114 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 115 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 116 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 117 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 118 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 119 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 120 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 121 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 122 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 123 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 124 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 125 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 126 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 127 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 128 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 129 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 130 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 131 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 132 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 133 }; 134 135 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = { 136 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 137 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), 138 }; 139 140 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = { 141 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 142 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), 143 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), 144 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), 145 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 146 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), 147 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), 148 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), 149 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), 150 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), 151 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), 152 }; 153 154 static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = { 155 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 156 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 157 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 158 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 159 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 160 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 161 }; 162 163 static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = { 164 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 165 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 166 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 167 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 168 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 169 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 170 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 171 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 172 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 173 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 174 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 175 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 176 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 177 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 178 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 179 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 180 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 181 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 182 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 183 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d), 184 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d), 185 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed), 186 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 187 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c), 188 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 189 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 190 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 191 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 192 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 193 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 194 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 195 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 196 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 197 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 198 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 199 }; 200 201 static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = { 202 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 203 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 204 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 205 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 206 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 207 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 208 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 209 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03), 210 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), 211 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), 212 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), 213 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06), 214 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), 215 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), 216 }; 217 218 static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = { 219 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 220 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 221 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 222 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 223 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 224 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 225 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 226 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 227 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 228 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 229 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 230 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 231 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 232 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 233 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), 234 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 235 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 236 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 237 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 238 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 239 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 240 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), 245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), 257 }; 258 259 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = { 260 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 261 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 262 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 263 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 264 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 265 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 266 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 267 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 268 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 269 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 270 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 271 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 272 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 273 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 274 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 275 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 276 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), 277 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 278 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 279 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 280 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 281 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 282 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 283 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 284 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 285 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 286 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 287 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 288 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 289 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 290 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 291 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 292 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 293 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 294 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 295 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 296 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 297 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 298 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 299 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 300 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 301 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 302 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 303 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 304 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 305 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 306 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 307 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 308 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), 309 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), 310 }; 311 312 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = { 313 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), 314 }; 315 316 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = { 317 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 318 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 319 }; 320 321 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = { 322 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 323 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), 324 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), 325 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), 326 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 327 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), 328 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), 329 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), 330 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), 331 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), 332 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), 333 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 334 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 335 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), 336 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), 337 }; 338 339 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = { 340 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15), 341 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 342 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 343 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 344 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), 345 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 346 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12), 347 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), 348 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ 349 }; 350 351 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = { 352 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 353 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 354 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 355 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 356 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 357 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), 358 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 359 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 360 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 361 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 362 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 363 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 364 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), 365 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), 366 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), 367 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), 368 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 369 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 370 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 371 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 372 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 373 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 374 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), 375 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 376 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), 377 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), 378 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), 379 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), 380 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), 381 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), 382 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 383 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 384 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), 385 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), 386 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), 387 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), 388 }; 389 390 static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = { 391 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), 392 }; 393 394 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = { 395 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 396 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), 397 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 398 }; 399 400 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = { 401 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 402 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 403 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 404 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 405 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 406 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 407 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 408 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 409 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 410 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 411 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 412 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 413 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 414 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 415 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 416 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 417 }; 418 419 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = { 420 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), 421 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 422 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), 427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 428 }; 429 430 static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = { 431 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 432 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 433 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 434 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 435 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 436 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 437 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 438 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 439 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 440 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 441 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 442 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 443 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b), 444 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 445 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 446 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 447 }; 448 449 static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = { 450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f), 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 458 }; 459 460 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = { 461 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), 462 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), 463 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 464 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), 465 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 466 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 467 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), 468 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 469 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 470 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 471 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 472 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), 474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), 475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), 478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), 482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), 483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 485 }; 486 487 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = { 488 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), 489 }; 490 491 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { 492 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 493 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 494 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 495 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 496 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), 497 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 498 }; 499 500 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = { 501 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), 502 }; 503 504 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { 505 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 506 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 507 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 508 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 509 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 510 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 511 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 512 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 513 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 514 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 515 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 516 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 517 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 518 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 519 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 520 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 521 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 522 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 523 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), 525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), 526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), 527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 539 }; 540 541 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = { 542 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), 554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 558 }; 559 560 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { 561 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 562 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 563 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 564 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 565 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 566 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 567 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 568 }; 569 570 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { 571 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), 572 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 573 }; 574 575 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = { 576 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), 577 }; 578 579 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = { 580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), 587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 601 }; 602 603 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { 604 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), 605 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), 606 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 607 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 608 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 609 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 610 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 611 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 612 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 613 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), 614 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), 615 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), 616 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 617 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), 618 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 619 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 620 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), 621 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), 622 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), 623 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), 624 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), 625 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), 626 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 627 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 628 }; 629 630 static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = { 631 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), 632 }; 633 634 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = { 635 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 636 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 637 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 638 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 639 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), 640 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 641 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), 642 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 643 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), 644 }; 645 646 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = { 647 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), 648 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), 649 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 650 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), 651 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 652 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 653 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), 654 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 655 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), 656 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), 657 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), 658 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), 659 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 660 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 661 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 662 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 663 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 664 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 665 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), 666 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 667 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 668 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), 669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), 670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), 671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), 672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), 673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), 674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), 675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), 676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), 677 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), 678 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), 679 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), 680 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), 681 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), 682 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), 683 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 684 }; 685 686 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = { 687 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 688 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 689 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 690 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 691 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 692 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 693 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), 694 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 695 }; 696 697 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = { 698 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), 699 }; 700 701 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = { 702 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), 703 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), 704 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 705 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 706 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 707 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), 708 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), 709 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 710 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), 711 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), 712 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 713 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), 714 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), 715 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), 716 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), 717 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), 718 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), 719 }; 720 721 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { 722 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 723 }; 724 725 static const struct qmp_phy_init_tbl sm8475_ufsphy_serdes[] = { 726 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 727 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 728 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 729 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 730 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 731 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 732 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 733 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18), 735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff), 736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c), 737 }; 738 739 static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_serdes[] = { 740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14), 743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98), 744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14), 745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18), 747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32), 748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f), 749 }; 750 751 static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_pcs[] = { 752 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b), 753 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 754 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 755 }; 756 757 static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { 758 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 769 }; 770 771 static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { 772 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), 773 }; 774 775 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = { 776 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), 779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), 781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 785 }; 786 787 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = { 788 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b), 790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c), 791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 792 }; 793 794 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { 795 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), 796 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 797 }; 798 799 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = { 800 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c), 801 }; 802 803 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { 804 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 805 806 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), 807 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), 808 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 809 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 810 811 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 812 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 813 814 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 815 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 816 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 817 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 818 }; 819 820 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = { 821 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), 822 }; 823 824 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = { 825 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), 826 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), 827 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 828 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), 829 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 830 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 831 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 832 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 833 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08), 834 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), 835 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), 836 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff), 837 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), 838 }; 839 840 static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { 841 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), 842 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 843 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 844 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 845 }; 846 847 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = { 848 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), 849 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 850 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 851 }; 852 853 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = { 854 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 855 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f), 856 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), 857 }; 858 859 static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = { 860 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 861 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 862 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 863 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 864 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 865 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 866 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f), 867 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a), 868 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17), 869 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 870 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 871 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 872 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 873 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 874 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 875 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 876 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 877 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 878 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 879 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 880 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 881 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 882 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 883 }; 884 885 static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = { 886 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x01), 887 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 888 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 889 }; 890 891 static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = { 892 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 893 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), 894 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), 895 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 896 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), 897 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 898 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 899 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 900 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 901 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e), 902 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 903 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce), 904 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce), 905 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18), 906 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 907 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f), 908 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 909 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 910 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 911 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 912 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 913 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 914 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 915 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B0, 0x24), 916 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B1, 0x24), 917 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B2, 0x20), 918 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), 919 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), 920 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f), 921 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94), 922 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa), 923 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), 924 }; 925 926 static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = { 927 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 928 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 929 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1), 930 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 931 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), 932 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e), 933 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12), 934 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15), 935 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19), 936 }; 937 938 static const struct qmp_phy_init_tbl sm8650_ufsphy_g4_pcs[] = { 939 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x13), 940 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 941 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 942 }; 943 944 static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = { 945 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 946 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05), 947 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05), 948 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d), 949 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), 950 }; 951 952 struct qmp_ufs_offsets { 953 u16 serdes; 954 u16 pcs; 955 u16 tx; 956 u16 rx; 957 u16 tx2; 958 u16 rx2; 959 }; 960 961 struct qmp_phy_cfg_tbls { 962 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 963 const struct qmp_phy_init_tbl *serdes; 964 int serdes_num; 965 const struct qmp_phy_init_tbl *tx; 966 int tx_num; 967 const struct qmp_phy_init_tbl *rx; 968 int rx_num; 969 const struct qmp_phy_init_tbl *pcs; 970 int pcs_num; 971 /* Maximum supported Gear of this tbls */ 972 u32 max_gear; 973 }; 974 975 /* struct qmp_phy_cfg - per-PHY initialization config */ 976 struct qmp_phy_cfg { 977 int lanes; 978 979 const struct qmp_ufs_offsets *offsets; 980 /* Maximum supported Gear of this config */ 981 u32 max_supported_gear; 982 983 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 984 const struct qmp_phy_cfg_tbls tbls; 985 /* Additional sequence for HS Series B */ 986 const struct qmp_phy_cfg_tbls tbls_hs_b; 987 /* Additional sequence for different HS Gears */ 988 const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY]; 989 990 /* regulators to be requested */ 991 const char * const *vreg_list; 992 int num_vregs; 993 994 /* array of registers with different offsets */ 995 const unsigned int *regs; 996 997 /* true, if PCS block has no separate SW_RESET register */ 998 bool no_pcs_sw_reset; 999 }; 1000 1001 struct qmp_ufs { 1002 struct device *dev; 1003 1004 const struct qmp_phy_cfg *cfg; 1005 1006 void __iomem *serdes; 1007 void __iomem *pcs; 1008 void __iomem *pcs_misc; 1009 void __iomem *tx; 1010 void __iomem *rx; 1011 void __iomem *tx2; 1012 void __iomem *rx2; 1013 1014 struct clk_bulk_data *clks; 1015 int num_clks; 1016 struct regulator_bulk_data *vregs; 1017 struct reset_control *ufs_reset; 1018 1019 struct phy *phy; 1020 u32 mode; 1021 u32 submode; 1022 }; 1023 1024 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1025 { 1026 u32 reg; 1027 1028 reg = readl(base + offset); 1029 reg |= val; 1030 writel(reg, base + offset); 1031 1032 /* ensure that above write is through */ 1033 readl(base + offset); 1034 } 1035 1036 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1037 { 1038 u32 reg; 1039 1040 reg = readl(base + offset); 1041 reg &= ~val; 1042 writel(reg, base + offset); 1043 1044 /* ensure that above write is through */ 1045 readl(base + offset); 1046 } 1047 1048 /* list of regulators */ 1049 static const char * const qmp_phy_vreg_l[] = { 1050 "vdda-phy", "vdda-pll", 1051 }; 1052 1053 static const struct qmp_ufs_offsets qmp_ufs_offsets = { 1054 .serdes = 0, 1055 .pcs = 0xc00, 1056 .tx = 0x400, 1057 .rx = 0x600, 1058 .tx2 = 0x800, 1059 .rx2 = 0xa00, 1060 }; 1061 1062 static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = { 1063 .serdes = 0, 1064 .pcs = 0x0400, 1065 .tx = 0x1000, 1066 .rx = 0x1200, 1067 .tx2 = 0x1800, 1068 .rx2 = 0x1a00, 1069 }; 1070 1071 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { 1072 .lanes = 1, 1073 1074 .offsets = &qmp_ufs_offsets, 1075 .max_supported_gear = UFS_HS_G3, 1076 1077 .tbls = { 1078 .serdes = msm8996_ufsphy_serdes, 1079 .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes), 1080 .tx = msm8996_ufsphy_tx, 1081 .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx), 1082 .rx = msm8996_ufsphy_rx, 1083 .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx), 1084 }, 1085 1086 .vreg_list = qmp_phy_vreg_l, 1087 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1088 1089 .regs = ufsphy_v2_regs_layout, 1090 1091 .no_pcs_sw_reset = true, 1092 }; 1093 1094 static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = { 1095 .lanes = 2, 1096 1097 .offsets = &qmp_ufs_offsets, 1098 .max_supported_gear = UFS_HS_G4, 1099 1100 .tbls = { 1101 .serdes = sm8350_ufsphy_serdes, 1102 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1103 .tx = sm8350_ufsphy_tx, 1104 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1105 .rx = sm8350_ufsphy_rx, 1106 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1107 .pcs = sm8350_ufsphy_pcs, 1108 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1109 }, 1110 .tbls_hs_b = { 1111 .serdes = sm8350_ufsphy_hs_b_serdes, 1112 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1113 }, 1114 .tbls_hs_overlay[0] = { 1115 .tx = sm8350_ufsphy_g4_tx, 1116 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1117 .rx = sm8350_ufsphy_g4_rx, 1118 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1119 .pcs = sm8350_ufsphy_g4_pcs, 1120 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1121 .max_gear = UFS_HS_G4, 1122 }, 1123 .vreg_list = qmp_phy_vreg_l, 1124 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1125 .regs = ufsphy_v5_regs_layout, 1126 }; 1127 1128 static const struct qmp_phy_cfg sc7280_ufsphy_cfg = { 1129 .lanes = 2, 1130 1131 .offsets = &qmp_ufs_offsets, 1132 .max_supported_gear = UFS_HS_G4, 1133 1134 .tbls = { 1135 .serdes = sm8150_ufsphy_serdes, 1136 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1137 .tx = sc7280_ufsphy_tx, 1138 .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx), 1139 .rx = sc7280_ufsphy_rx, 1140 .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx), 1141 .pcs = sc7280_ufsphy_pcs, 1142 .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs), 1143 }, 1144 .tbls_hs_b = { 1145 .serdes = sm8150_ufsphy_hs_b_serdes, 1146 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1147 }, 1148 .tbls_hs_overlay[0] = { 1149 .tx = sm8250_ufsphy_hs_g4_tx, 1150 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), 1151 .rx = sc7280_ufsphy_hs_g4_rx, 1152 .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx), 1153 .pcs = sm8150_ufsphy_hs_g4_pcs, 1154 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1155 .max_gear = UFS_HS_G4, 1156 }, 1157 .vreg_list = qmp_phy_vreg_l, 1158 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1159 .regs = ufsphy_v4_regs_layout, 1160 }; 1161 1162 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { 1163 .lanes = 2, 1164 1165 .offsets = &qmp_ufs_offsets, 1166 .max_supported_gear = UFS_HS_G4, 1167 1168 .tbls = { 1169 .serdes = sm8350_ufsphy_serdes, 1170 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1171 .tx = sm8350_ufsphy_tx, 1172 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1173 .rx = sm8350_ufsphy_rx, 1174 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1175 .pcs = sm8350_ufsphy_pcs, 1176 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1177 }, 1178 .tbls_hs_b = { 1179 .serdes = sm8350_ufsphy_hs_b_serdes, 1180 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1181 }, 1182 .tbls_hs_overlay[0] = { 1183 .tx = sm8350_ufsphy_g4_tx, 1184 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1185 .rx = sm8350_ufsphy_g4_rx, 1186 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1187 .pcs = sm8350_ufsphy_g4_pcs, 1188 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1189 .max_gear = UFS_HS_G4, 1190 }, 1191 .vreg_list = qmp_phy_vreg_l, 1192 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1193 .regs = ufsphy_v5_regs_layout, 1194 }; 1195 1196 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { 1197 .lanes = 2, 1198 1199 .offsets = &qmp_ufs_offsets, 1200 .max_supported_gear = UFS_HS_G3, 1201 1202 .tbls = { 1203 .serdes = sdm845_ufsphy_serdes, 1204 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 1205 .tx = sdm845_ufsphy_tx, 1206 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), 1207 .rx = sdm845_ufsphy_rx, 1208 .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx), 1209 .pcs = sdm845_ufsphy_pcs, 1210 .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs), 1211 }, 1212 .tbls_hs_b = { 1213 .serdes = sdm845_ufsphy_hs_b_serdes, 1214 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 1215 }, 1216 .vreg_list = qmp_phy_vreg_l, 1217 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1218 .regs = ufsphy_v3_regs_layout, 1219 1220 .no_pcs_sw_reset = true, 1221 }; 1222 1223 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { 1224 .lanes = 1, 1225 1226 .offsets = &qmp_ufs_offsets, 1227 .max_supported_gear = UFS_HS_G3, 1228 1229 .tbls = { 1230 .serdes = sm6115_ufsphy_serdes, 1231 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes), 1232 .tx = sm6115_ufsphy_tx, 1233 .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx), 1234 .rx = sm6115_ufsphy_rx, 1235 .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx), 1236 .pcs = sm6115_ufsphy_pcs, 1237 .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs), 1238 }, 1239 .tbls_hs_b = { 1240 .serdes = sm6115_ufsphy_hs_b_serdes, 1241 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), 1242 }, 1243 .vreg_list = qmp_phy_vreg_l, 1244 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1245 .regs = ufsphy_v2_regs_layout, 1246 1247 .no_pcs_sw_reset = true, 1248 }; 1249 1250 static const struct qmp_phy_cfg sm7150_ufsphy_cfg = { 1251 .lanes = 1, 1252 1253 .offsets = &qmp_ufs_offsets, 1254 .max_supported_gear = UFS_HS_G3, 1255 1256 .tbls = { 1257 .serdes = sdm845_ufsphy_serdes, 1258 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 1259 .tx = sdm845_ufsphy_tx, 1260 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), 1261 .rx = sm7150_ufsphy_rx, 1262 .rx_num = ARRAY_SIZE(sm7150_ufsphy_rx), 1263 .pcs = sm7150_ufsphy_pcs, 1264 .pcs_num = ARRAY_SIZE(sm7150_ufsphy_pcs), 1265 }, 1266 .tbls_hs_b = { 1267 .serdes = sdm845_ufsphy_hs_b_serdes, 1268 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 1269 }, 1270 .vreg_list = qmp_phy_vreg_l, 1271 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1272 .regs = ufsphy_v3_regs_layout, 1273 1274 .no_pcs_sw_reset = true, 1275 }; 1276 1277 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { 1278 .lanes = 2, 1279 1280 .offsets = &qmp_ufs_offsets, 1281 .max_supported_gear = UFS_HS_G4, 1282 1283 .tbls = { 1284 .serdes = sm8150_ufsphy_serdes, 1285 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1286 .tx = sm8150_ufsphy_tx, 1287 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 1288 .rx = sm8150_ufsphy_rx, 1289 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 1290 .pcs = sm8150_ufsphy_pcs, 1291 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 1292 }, 1293 .tbls_hs_b = { 1294 .serdes = sm8150_ufsphy_hs_b_serdes, 1295 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1296 }, 1297 .tbls_hs_overlay[0] = { 1298 .tx = sm8150_ufsphy_hs_g4_tx, 1299 .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), 1300 .rx = sm8150_ufsphy_hs_g4_rx, 1301 .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), 1302 .pcs = sm8150_ufsphy_hs_g4_pcs, 1303 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1304 .max_gear = UFS_HS_G4, 1305 }, 1306 .vreg_list = qmp_phy_vreg_l, 1307 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1308 .regs = ufsphy_v4_regs_layout, 1309 }; 1310 1311 static const struct qmp_phy_cfg sm8250_ufsphy_cfg = { 1312 .lanes = 2, 1313 1314 .offsets = &qmp_ufs_offsets, 1315 .max_supported_gear = UFS_HS_G4, 1316 1317 .tbls = { 1318 .serdes = sm8150_ufsphy_serdes, 1319 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1320 .tx = sm8150_ufsphy_tx, 1321 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 1322 .rx = sm8150_ufsphy_rx, 1323 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 1324 .pcs = sm8150_ufsphy_pcs, 1325 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 1326 }, 1327 .tbls_hs_b = { 1328 .serdes = sm8150_ufsphy_hs_b_serdes, 1329 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1330 }, 1331 .tbls_hs_overlay[0] = { 1332 .tx = sm8250_ufsphy_hs_g4_tx, 1333 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), 1334 .rx = sm8250_ufsphy_hs_g4_rx, 1335 .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), 1336 .pcs = sm8150_ufsphy_hs_g4_pcs, 1337 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1338 .max_gear = UFS_HS_G4, 1339 }, 1340 .vreg_list = qmp_phy_vreg_l, 1341 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1342 .regs = ufsphy_v4_regs_layout, 1343 }; 1344 1345 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { 1346 .lanes = 2, 1347 1348 .offsets = &qmp_ufs_offsets, 1349 .max_supported_gear = UFS_HS_G4, 1350 1351 .tbls = { 1352 .serdes = sm8350_ufsphy_serdes, 1353 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1354 .tx = sm8350_ufsphy_tx, 1355 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1356 .rx = sm8350_ufsphy_rx, 1357 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1358 .pcs = sm8350_ufsphy_pcs, 1359 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1360 }, 1361 .tbls_hs_b = { 1362 .serdes = sm8350_ufsphy_hs_b_serdes, 1363 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1364 }, 1365 .tbls_hs_overlay[0] = { 1366 .tx = sm8350_ufsphy_g4_tx, 1367 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1368 .rx = sm8350_ufsphy_g4_rx, 1369 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1370 .pcs = sm8350_ufsphy_g4_pcs, 1371 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1372 .max_gear = UFS_HS_G4, 1373 }, 1374 .vreg_list = qmp_phy_vreg_l, 1375 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1376 .regs = ufsphy_v5_regs_layout, 1377 }; 1378 1379 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { 1380 .lanes = 2, 1381 1382 .offsets = &qmp_ufs_offsets, 1383 .max_supported_gear = UFS_HS_G4, 1384 1385 .tbls = { 1386 .serdes = sm8350_ufsphy_serdes, 1387 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1388 .tx = sm8350_ufsphy_tx, 1389 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1390 .rx = sm8350_ufsphy_rx, 1391 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1392 .pcs = sm8350_ufsphy_pcs, 1393 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1394 }, 1395 .tbls_hs_b = { 1396 .serdes = sm8350_ufsphy_hs_b_serdes, 1397 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1398 }, 1399 .tbls_hs_overlay[0] = { 1400 .tx = sm8350_ufsphy_g4_tx, 1401 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1402 .rx = sm8350_ufsphy_g4_rx, 1403 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1404 .pcs = sm8350_ufsphy_g4_pcs, 1405 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1406 .max_gear = UFS_HS_G4, 1407 }, 1408 .vreg_list = qmp_phy_vreg_l, 1409 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1410 .regs = ufsphy_v5_regs_layout, 1411 }; 1412 1413 static const struct qmp_phy_cfg sm8475_ufsphy_cfg = { 1414 .lanes = 2, 1415 1416 .offsets = &qmp_ufs_offsets_v6, 1417 .max_supported_gear = UFS_HS_G4, 1418 1419 .tbls = { 1420 .serdes = sm8475_ufsphy_serdes, 1421 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_serdes), 1422 .tx = sm8550_ufsphy_tx, 1423 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), 1424 .rx = sm8550_ufsphy_rx, 1425 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), 1426 .pcs = sm8550_ufsphy_pcs, 1427 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), 1428 }, 1429 .tbls_hs_b = { 1430 .serdes = sm8550_ufsphy_hs_b_serdes, 1431 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), 1432 }, 1433 .tbls_hs_overlay[0] = { 1434 .serdes = sm8475_ufsphy_g4_serdes, 1435 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_g4_serdes), 1436 .tx = sm8550_ufsphy_g4_tx, 1437 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx), 1438 .rx = sm8550_ufsphy_g4_rx, 1439 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx), 1440 .pcs = sm8475_ufsphy_g4_pcs, 1441 .pcs_num = ARRAY_SIZE(sm8475_ufsphy_g4_pcs), 1442 .max_gear = UFS_HS_G4, 1443 }, 1444 .vreg_list = qmp_phy_vreg_l, 1445 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1446 .regs = ufsphy_v6_regs_layout, 1447 }; 1448 1449 static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { 1450 .lanes = 2, 1451 1452 .offsets = &qmp_ufs_offsets_v6, 1453 .max_supported_gear = UFS_HS_G5, 1454 1455 .tbls = { 1456 .serdes = sm8550_ufsphy_serdes, 1457 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), 1458 .tx = sm8550_ufsphy_tx, 1459 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), 1460 .rx = sm8550_ufsphy_rx, 1461 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), 1462 .pcs = sm8550_ufsphy_pcs, 1463 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), 1464 }, 1465 .tbls_hs_b = { 1466 .serdes = sm8550_ufsphy_hs_b_serdes, 1467 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), 1468 }, 1469 .tbls_hs_overlay[0] = { 1470 .serdes = sm8550_ufsphy_g4_serdes, 1471 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes), 1472 .tx = sm8550_ufsphy_g4_tx, 1473 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx), 1474 .rx = sm8550_ufsphy_g4_rx, 1475 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx), 1476 .pcs = sm8550_ufsphy_g4_pcs, 1477 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs), 1478 .max_gear = UFS_HS_G4, 1479 }, 1480 .tbls_hs_overlay[1] = { 1481 .serdes = sm8550_ufsphy_g5_serdes, 1482 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes), 1483 .rx = sm8550_ufsphy_g5_rx, 1484 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx), 1485 .pcs = sm8550_ufsphy_g5_pcs, 1486 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs), 1487 .max_gear = UFS_HS_G5, 1488 }, 1489 .vreg_list = qmp_phy_vreg_l, 1490 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1491 .regs = ufsphy_v6_regs_layout, 1492 }; 1493 1494 static const struct qmp_phy_cfg sm8650_ufsphy_cfg = { 1495 .lanes = 2, 1496 1497 .offsets = &qmp_ufs_offsets_v6, 1498 .max_supported_gear = UFS_HS_G5, 1499 1500 .tbls = { 1501 .serdes = sm8650_ufsphy_serdes, 1502 .serdes_num = ARRAY_SIZE(sm8650_ufsphy_serdes), 1503 .tx = sm8650_ufsphy_tx, 1504 .tx_num = ARRAY_SIZE(sm8650_ufsphy_tx), 1505 .rx = sm8650_ufsphy_rx, 1506 .rx_num = ARRAY_SIZE(sm8650_ufsphy_rx), 1507 .pcs = sm8650_ufsphy_pcs, 1508 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs), 1509 }, 1510 .tbls_hs_overlay[0] = { 1511 .pcs = sm8650_ufsphy_g4_pcs, 1512 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g4_pcs), 1513 .max_gear = UFS_HS_G4, 1514 }, 1515 .tbls_hs_overlay[1] = { 1516 .pcs = sm8650_ufsphy_g5_pcs, 1517 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs), 1518 .max_gear = UFS_HS_G5, 1519 }, 1520 1521 .vreg_list = qmp_phy_vreg_l, 1522 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1523 .regs = ufsphy_v6_regs_layout, 1524 }; 1525 1526 static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1527 { 1528 void __iomem *serdes = qmp->serdes; 1529 1530 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 1531 } 1532 1533 static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1534 { 1535 const struct qmp_phy_cfg *cfg = qmp->cfg; 1536 void __iomem *tx = qmp->tx; 1537 void __iomem *rx = qmp->rx; 1538 1539 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); 1540 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); 1541 1542 if (cfg->lanes >= 2) { 1543 qmp_configure_lane(qmp->dev, qmp->tx2, tbls->tx, tbls->tx_num, 2); 1544 qmp_configure_lane(qmp->dev, qmp->rx2, tbls->rx, tbls->rx_num, 2); 1545 } 1546 } 1547 1548 static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1549 { 1550 void __iomem *pcs = qmp->pcs; 1551 1552 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 1553 } 1554 1555 static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) 1556 { 1557 u32 max_gear, floor_max_gear = cfg->max_supported_gear; 1558 int idx, ret = -EINVAL; 1559 1560 for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) { 1561 max_gear = cfg->tbls_hs_overlay[idx].max_gear; 1562 1563 /* Skip if the table is not available */ 1564 if (max_gear == 0) 1565 continue; 1566 1567 /* Direct matching, bail */ 1568 if (qmp->submode == max_gear) 1569 return idx; 1570 1571 /* If no direct matching, the lowest gear is the best matching */ 1572 if (max_gear < floor_max_gear) { 1573 ret = idx; 1574 floor_max_gear = max_gear; 1575 } 1576 } 1577 1578 return ret; 1579 } 1580 1581 static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) 1582 { 1583 int i; 1584 1585 qmp_ufs_serdes_init(qmp, &cfg->tbls); 1586 qmp_ufs_lanes_init(qmp, &cfg->tbls); 1587 qmp_ufs_pcs_init(qmp, &cfg->tbls); 1588 1589 i = qmp_ufs_get_gear_overlay(qmp, cfg); 1590 if (i >= 0) { 1591 qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]); 1592 qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]); 1593 qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]); 1594 } 1595 1596 if (qmp->mode == PHY_MODE_UFS_HS_B) 1597 qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); 1598 } 1599 1600 static int qmp_ufs_com_init(struct qmp_ufs *qmp) 1601 { 1602 const struct qmp_phy_cfg *cfg = qmp->cfg; 1603 void __iomem *pcs = qmp->pcs; 1604 int ret; 1605 1606 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1607 if (ret) { 1608 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1609 return ret; 1610 } 1611 1612 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 1613 if (ret) 1614 goto err_disable_regulators; 1615 1616 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1617 1618 return 0; 1619 1620 err_disable_regulators: 1621 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1622 1623 return ret; 1624 } 1625 1626 static int qmp_ufs_com_exit(struct qmp_ufs *qmp) 1627 { 1628 const struct qmp_phy_cfg *cfg = qmp->cfg; 1629 1630 reset_control_assert(qmp->ufs_reset); 1631 1632 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 1633 1634 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1635 1636 return 0; 1637 } 1638 1639 static int qmp_ufs_init(struct phy *phy) 1640 { 1641 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1642 const struct qmp_phy_cfg *cfg = qmp->cfg; 1643 int ret; 1644 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 1645 1646 if (cfg->no_pcs_sw_reset) { 1647 /* 1648 * Get UFS reset, which is delayed until now to avoid a 1649 * circular dependency where UFS needs its PHY, but the PHY 1650 * needs this UFS reset. 1651 */ 1652 if (!qmp->ufs_reset) { 1653 qmp->ufs_reset = 1654 devm_reset_control_get_exclusive(qmp->dev, 1655 "ufsphy"); 1656 1657 if (IS_ERR(qmp->ufs_reset)) { 1658 ret = PTR_ERR(qmp->ufs_reset); 1659 dev_err(qmp->dev, 1660 "failed to get UFS reset: %d\n", 1661 ret); 1662 1663 qmp->ufs_reset = NULL; 1664 return ret; 1665 } 1666 } 1667 1668 ret = reset_control_assert(qmp->ufs_reset); 1669 if (ret) 1670 return ret; 1671 } 1672 1673 ret = qmp_ufs_com_init(qmp); 1674 if (ret) 1675 return ret; 1676 1677 return 0; 1678 } 1679 1680 static int qmp_ufs_power_on(struct phy *phy) 1681 { 1682 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1683 const struct qmp_phy_cfg *cfg = qmp->cfg; 1684 void __iomem *pcs = qmp->pcs; 1685 void __iomem *status; 1686 unsigned int val; 1687 int ret; 1688 1689 qmp_ufs_init_registers(qmp, cfg); 1690 1691 ret = reset_control_deassert(qmp->ufs_reset); 1692 if (ret) 1693 return ret; 1694 1695 /* Pull PHY out of reset state */ 1696 if (!cfg->no_pcs_sw_reset) 1697 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1698 1699 /* start SerDes */ 1700 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); 1701 1702 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 1703 ret = readl_poll_timeout(status, val, (val & PCS_READY), 200, 1704 PHY_INIT_COMPLETE_TIMEOUT); 1705 if (ret) { 1706 dev_err(qmp->dev, "phy initialization timed-out\n"); 1707 return ret; 1708 } 1709 1710 return 0; 1711 } 1712 1713 static int qmp_ufs_power_off(struct phy *phy) 1714 { 1715 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1716 const struct qmp_phy_cfg *cfg = qmp->cfg; 1717 1718 /* PHY reset */ 1719 if (!cfg->no_pcs_sw_reset) 1720 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1721 1722 /* stop SerDes */ 1723 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); 1724 1725 /* Put PHY into POWER DOWN state: active low */ 1726 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1727 SW_PWRDN); 1728 1729 return 0; 1730 } 1731 1732 static int qmp_ufs_exit(struct phy *phy) 1733 { 1734 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1735 1736 qmp_ufs_com_exit(qmp); 1737 1738 return 0; 1739 } 1740 1741 static int qmp_ufs_enable(struct phy *phy) 1742 { 1743 int ret; 1744 1745 ret = qmp_ufs_init(phy); 1746 if (ret) 1747 return ret; 1748 1749 ret = qmp_ufs_power_on(phy); 1750 if (ret) 1751 qmp_ufs_exit(phy); 1752 1753 return ret; 1754 } 1755 1756 static int qmp_ufs_disable(struct phy *phy) 1757 { 1758 int ret; 1759 1760 ret = qmp_ufs_power_off(phy); 1761 if (ret) 1762 return ret; 1763 return qmp_ufs_exit(phy); 1764 } 1765 1766 static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) 1767 { 1768 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1769 const struct qmp_phy_cfg *cfg = qmp->cfg; 1770 1771 if (submode > cfg->max_supported_gear || submode == 0) { 1772 dev_err(qmp->dev, "Invalid PHY submode %d\n", submode); 1773 return -EINVAL; 1774 } 1775 1776 qmp->mode = mode; 1777 qmp->submode = submode; 1778 1779 return 0; 1780 } 1781 1782 static const struct phy_ops qcom_qmp_ufs_phy_ops = { 1783 .power_on = qmp_ufs_enable, 1784 .power_off = qmp_ufs_disable, 1785 .set_mode = qmp_ufs_set_mode, 1786 .owner = THIS_MODULE, 1787 }; 1788 1789 static int qmp_ufs_vreg_init(struct qmp_ufs *qmp) 1790 { 1791 const struct qmp_phy_cfg *cfg = qmp->cfg; 1792 struct device *dev = qmp->dev; 1793 int num = cfg->num_vregs; 1794 int i; 1795 1796 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 1797 if (!qmp->vregs) 1798 return -ENOMEM; 1799 1800 for (i = 0; i < num; i++) 1801 qmp->vregs[i].supply = cfg->vreg_list[i]; 1802 1803 return devm_regulator_bulk_get(dev, num, qmp->vregs); 1804 } 1805 1806 static int qmp_ufs_clk_init(struct qmp_ufs *qmp) 1807 { 1808 struct device *dev = qmp->dev; 1809 1810 qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks); 1811 if (qmp->num_clks < 0) 1812 return qmp->num_clks; 1813 1814 return 0; 1815 } 1816 1817 static void qmp_ufs_clk_release_provider(void *res) 1818 { 1819 of_clk_del_provider(res); 1820 } 1821 1822 #define UFS_SYMBOL_CLOCKS 3 1823 1824 static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np) 1825 { 1826 struct clk_hw_onecell_data *clk_data; 1827 struct clk_hw *hw; 1828 char name[64]; 1829 int ret; 1830 1831 clk_data = devm_kzalloc(qmp->dev, 1832 struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS), 1833 GFP_KERNEL); 1834 if (!clk_data) 1835 return -ENOMEM; 1836 1837 clk_data->num = UFS_SYMBOL_CLOCKS; 1838 1839 snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev)); 1840 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 1841 if (IS_ERR(hw)) 1842 return PTR_ERR(hw); 1843 1844 clk_data->hws[0] = hw; 1845 1846 snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev)); 1847 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 1848 if (IS_ERR(hw)) 1849 return PTR_ERR(hw); 1850 1851 clk_data->hws[1] = hw; 1852 1853 snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev)); 1854 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 1855 if (IS_ERR(hw)) 1856 return PTR_ERR(hw); 1857 1858 clk_data->hws[2] = hw; 1859 1860 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 1861 if (ret) 1862 return ret; 1863 1864 /* 1865 * Roll a devm action because the clock provider can be a child node. 1866 */ 1867 return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np); 1868 } 1869 1870 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np) 1871 { 1872 struct platform_device *pdev = to_platform_device(qmp->dev); 1873 const struct qmp_phy_cfg *cfg = qmp->cfg; 1874 struct device *dev = qmp->dev; 1875 1876 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 1877 if (IS_ERR(qmp->serdes)) 1878 return PTR_ERR(qmp->serdes); 1879 1880 /* 1881 * Get memory resources for the PHY: 1882 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 1883 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 1884 * For single lane PHYs: pcs_misc (optional) -> 3. 1885 */ 1886 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 1887 if (IS_ERR(qmp->tx)) 1888 return PTR_ERR(qmp->tx); 1889 1890 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 1891 if (IS_ERR(qmp->rx)) 1892 return PTR_ERR(qmp->rx); 1893 1894 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 1895 if (IS_ERR(qmp->pcs)) 1896 return PTR_ERR(qmp->pcs); 1897 1898 if (cfg->lanes >= 2) { 1899 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 1900 if (IS_ERR(qmp->tx2)) 1901 return PTR_ERR(qmp->tx2); 1902 1903 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 1904 if (IS_ERR(qmp->rx2)) 1905 return PTR_ERR(qmp->rx2); 1906 1907 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 1908 } else { 1909 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 1910 } 1911 1912 if (IS_ERR(qmp->pcs_misc)) 1913 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 1914 1915 return 0; 1916 } 1917 1918 static int qmp_ufs_parse_dt(struct qmp_ufs *qmp) 1919 { 1920 struct platform_device *pdev = to_platform_device(qmp->dev); 1921 const struct qmp_phy_cfg *cfg = qmp->cfg; 1922 const struct qmp_ufs_offsets *offs = cfg->offsets; 1923 void __iomem *base; 1924 1925 if (!offs) 1926 return -EINVAL; 1927 1928 base = devm_platform_ioremap_resource(pdev, 0); 1929 if (IS_ERR(base)) 1930 return PTR_ERR(base); 1931 1932 qmp->serdes = base + offs->serdes; 1933 qmp->pcs = base + offs->pcs; 1934 qmp->tx = base + offs->tx; 1935 qmp->rx = base + offs->rx; 1936 1937 if (cfg->lanes >= 2) { 1938 qmp->tx2 = base + offs->tx2; 1939 qmp->rx2 = base + offs->rx2; 1940 } 1941 1942 return 0; 1943 } 1944 1945 static int qmp_ufs_probe(struct platform_device *pdev) 1946 { 1947 struct device *dev = &pdev->dev; 1948 struct phy_provider *phy_provider; 1949 struct device_node *np; 1950 struct qmp_ufs *qmp; 1951 int ret; 1952 1953 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 1954 if (!qmp) 1955 return -ENOMEM; 1956 1957 qmp->dev = dev; 1958 1959 qmp->cfg = of_device_get_match_data(dev); 1960 if (!qmp->cfg) 1961 return -EINVAL; 1962 1963 ret = qmp_ufs_clk_init(qmp); 1964 if (ret) 1965 return ret; 1966 1967 ret = qmp_ufs_vreg_init(qmp); 1968 if (ret) 1969 return ret; 1970 1971 /* Check for legacy binding with child node. */ 1972 np = of_get_next_available_child(dev->of_node, NULL); 1973 if (np) { 1974 ret = qmp_ufs_parse_dt_legacy(qmp, np); 1975 } else { 1976 np = of_node_get(dev->of_node); 1977 ret = qmp_ufs_parse_dt(qmp); 1978 } 1979 if (ret) 1980 goto err_node_put; 1981 1982 ret = qmp_ufs_register_clocks(qmp, np); 1983 if (ret) 1984 goto err_node_put; 1985 1986 qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops); 1987 if (IS_ERR(qmp->phy)) { 1988 ret = PTR_ERR(qmp->phy); 1989 dev_err(dev, "failed to create PHY: %d\n", ret); 1990 goto err_node_put; 1991 } 1992 1993 phy_set_drvdata(qmp->phy, qmp); 1994 1995 of_node_put(np); 1996 1997 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1998 1999 return PTR_ERR_OR_ZERO(phy_provider); 2000 2001 err_node_put: 2002 of_node_put(np); 2003 return ret; 2004 } 2005 2006 static const struct of_device_id qmp_ufs_of_match_table[] = { 2007 { 2008 .compatible = "qcom,msm8996-qmp-ufs-phy", 2009 .data = &msm8996_ufsphy_cfg, 2010 }, { 2011 .compatible = "qcom,msm8998-qmp-ufs-phy", 2012 .data = &sdm845_ufsphy_cfg, 2013 }, { 2014 .compatible = "qcom,sa8775p-qmp-ufs-phy", 2015 .data = &sa8775p_ufsphy_cfg, 2016 }, { 2017 .compatible = "qcom,sc7180-qmp-ufs-phy", 2018 .data = &sm7150_ufsphy_cfg, 2019 }, { 2020 .compatible = "qcom,sc7280-qmp-ufs-phy", 2021 .data = &sc7280_ufsphy_cfg, 2022 }, { 2023 .compatible = "qcom,sc8180x-qmp-ufs-phy", 2024 .data = &sm8150_ufsphy_cfg, 2025 }, { 2026 .compatible = "qcom,sc8280xp-qmp-ufs-phy", 2027 .data = &sc8280xp_ufsphy_cfg, 2028 }, { 2029 .compatible = "qcom,sdm845-qmp-ufs-phy", 2030 .data = &sdm845_ufsphy_cfg, 2031 }, { 2032 .compatible = "qcom,sm6115-qmp-ufs-phy", 2033 .data = &sm6115_ufsphy_cfg, 2034 }, { 2035 .compatible = "qcom,sm6125-qmp-ufs-phy", 2036 .data = &sm6115_ufsphy_cfg, 2037 }, { 2038 .compatible = "qcom,sm6350-qmp-ufs-phy", 2039 .data = &sdm845_ufsphy_cfg, 2040 }, { 2041 .compatible = "qcom,sm7150-qmp-ufs-phy", 2042 .data = &sm7150_ufsphy_cfg, 2043 }, { 2044 .compatible = "qcom,sm8150-qmp-ufs-phy", 2045 .data = &sm8150_ufsphy_cfg, 2046 }, { 2047 .compatible = "qcom,sm8250-qmp-ufs-phy", 2048 .data = &sm8250_ufsphy_cfg, 2049 }, { 2050 .compatible = "qcom,sm8350-qmp-ufs-phy", 2051 .data = &sm8350_ufsphy_cfg, 2052 }, { 2053 .compatible = "qcom,sm8450-qmp-ufs-phy", 2054 .data = &sm8450_ufsphy_cfg, 2055 }, { 2056 .compatible = "qcom,sm8475-qmp-ufs-phy", 2057 .data = &sm8475_ufsphy_cfg, 2058 }, { 2059 .compatible = "qcom,sm8550-qmp-ufs-phy", 2060 .data = &sm8550_ufsphy_cfg, 2061 }, { 2062 .compatible = "qcom,sm8650-qmp-ufs-phy", 2063 .data = &sm8650_ufsphy_cfg, 2064 }, 2065 { }, 2066 }; 2067 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table); 2068 2069 static struct platform_driver qmp_ufs_driver = { 2070 .probe = qmp_ufs_probe, 2071 .driver = { 2072 .name = "qcom-qmp-ufs-phy", 2073 .of_match_table = qmp_ufs_of_match_table, 2074 }, 2075 }; 2076 2077 module_platform_driver(qmp_ufs_driver); 2078 2079 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2080 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver"); 2081 MODULE_LICENSE("GPL v2"); 2082