1*c1282d5fSXiangxu Yin /* SPDX-License-Identifier: GPL-2.0 */ 2*c1282d5fSXiangxu Yin /* 3*c1282d5fSXiangxu Yin * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4*c1282d5fSXiangxu Yin */ 5*c1282d5fSXiangxu Yin 6*c1282d5fSXiangxu Yin #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V2_H_ 7*c1282d5fSXiangxu Yin #define QCOM_PHY_QMP_QSERDES_TXRX_V2_H_ 8*c1282d5fSXiangxu Yin 9*c1282d5fSXiangxu Yin /* Only for QMP V2 PHY - TX registers */ 10*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_BIST_MODE_LANENO 0x000 11*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_CLKBUF_ENABLE 0x008 12*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_TX_EMP_POST1_LVL 0x00c 13*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_TX_DRV_LVL 0x01c 14*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_RESET_TSYNC_EN 0x024 15*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_PRE_STALL_LDO_BOOST_EN 0x028 16*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_TX_BAND 0x02c 17*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_SLEW_CNTL 0x030 18*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_INTERFACE_SELECT 0x034 19*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_RES_CODE_LANE_TX 0x03c 20*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_RES_CODE_LANE_RX 0x040 21*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_RES_CODE_LANE_OFFSET_TX 0x044 22*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_RES_CODE_LANE_OFFSET_RX 0x048 23*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_DEBUG_BUS_SEL 0x058 24*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_TRANSCEIVER_BIAS_EN 0x05c 25*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_HIGHZ_DRVR_EN 0x060 26*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_TX_POL_INV 0x064 27*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 28*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_LANE_MODE_1 0x08c 29*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_LANE_MODE_2 0x090 30*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_LANE_MODE_3 0x094 31*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_RCV_DETECT_LVL_2 0x0a4 32*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_TRAN_DRVR_EMP_EN 0x0c0 33*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_TX_INTERFACE_MODE 0x0c4 34*c1282d5fSXiangxu Yin #define QSERDES_V2_TX_VMODE_CTRL1 0x0f0 35*c1282d5fSXiangxu Yin 36*c1282d5fSXiangxu Yin /* Only for QMP V2 PHY - RX registers */ 37*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_FO_GAIN 0x008 38*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_SO_GAIN_HALF 0x00c 39*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_SO_GAIN 0x014 40*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_SVS_SO_GAIN_HALF 0x024 41*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 42*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_SVS_SO_GAIN 0x02c 43*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN 0x030 44*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 45*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 46*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 47*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_UCDR_PI_CONTROLS 0x044 48*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_TERM_BW 0x07c 49*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_VGA_CAL_CNTRL1 0x0bc 50*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_VGA_CAL_CNTRL2 0x0c0 51*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_EQ_GAIN2_LSB 0x0c8 52*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_EQ_GAIN2_MSB 0x0cc 53*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d0 54*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 55*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 56*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 57*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 58*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 59*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_SIGDET_ENABLES 0x100 60*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_SIGDET_CNTRL 0x104 61*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_SIGDET_LVL 0x108 62*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL 0x10c 63*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_BAND 0x110 64*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_INTERFACE_MODE 0x11c 65*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_MODE_00 0x164 66*c1282d5fSXiangxu Yin #define QSERDES_V2_RX_RX_MODE_01 0x168 67*c1282d5fSXiangxu Yin 68*c1282d5fSXiangxu Yin #endif 69