1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef QCOM_PHY_QMP_QSERDES_COM_H_ 7 #define QCOM_PHY_QMP_QSERDES_COM_H_ 8 9 /* Only for QMP V2 PHY - QSERDES COM registers */ 10 #define QSERDES_COM_ATB_SEL1 0x000 11 #define QSERDES_COM_ATB_SEL2 0x004 12 #define QSERDES_COM_FREQ_UPDATE 0x008 13 #define QSERDES_COM_BG_TIMER 0x00c 14 #define QSERDES_COM_SSC_EN_CENTER 0x010 15 #define QSERDES_COM_SSC_ADJ_PER1 0x014 16 #define QSERDES_COM_SSC_ADJ_PER2 0x018 17 #define QSERDES_COM_SSC_PER1 0x01c 18 #define QSERDES_COM_SSC_PER2 0x020 19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024 20 #define QSERDES_COM_SSC_STEP_SIZE2 0x028 21 #define QSERDES_COM_POST_DIV 0x02c 22 #define QSERDES_COM_POST_DIV_MUX 0x030 23 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 24 #define QSERDES_COM_CLK_ENABLE1 0x038 25 #define QSERDES_COM_SYS_CLK_CTRL 0x03c 26 #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 27 #define QSERDES_COM_PLL_EN 0x044 28 #define QSERDES_COM_PLL_IVCO 0x048 29 #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 30 #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 31 #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 32 #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 33 #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 34 #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 35 #define QSERDES_COM_LOCK_CMP1_MODE2 0x064 36 #define QSERDES_COM_CMN_RSVD0 0x064 37 #define QSERDES_COM_LOCK_CMP2_MODE2 0x068 38 #define QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x068 39 #define QSERDES_COM_LOCK_CMP3_MODE2 0x06c 40 #define QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x06c 41 #define QSERDES_COM_BG_TRIM 0x070 42 #define QSERDES_COM_CLK_EP_DIV 0x074 43 #define QSERDES_COM_CP_CTRL_MODE0 0x078 44 #define QSERDES_COM_CP_CTRL_MODE1 0x07c 45 #define QSERDES_COM_CP_CTRL_MODE2 0x080 46 #define QSERDES_COM_CMN_RSVD1 0x080 47 #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 48 #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 49 #define QSERDES_COM_PLL_RCTRL_MODE2 0x08c 50 #define QSERDES_COM_CMN_RSVD2 0x08c 51 #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 52 #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 53 #define QSERDES_COM_PLL_CCTRL_MODE2 0x098 54 #define QSERDES_COM_CMN_RSVD3 0x098 55 #define QSERDES_COM_PLL_CNTRL 0x09c 56 #define QSERDES_COM_PHASE_SEL_CTRL 0x0a0 57 #define QSERDES_COM_PHASE_SEL_DC 0x0a4 58 #define QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x0a8 59 #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 60 #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 61 #define QSERDES_COM_CML_SYSCLK_SEL 0x0b0 62 #define QSERDES_COM_RESETSM_CNTRL 0x0b4 63 #define QSERDES_COM_RESETSM_CNTRL2 0x0b8 64 #define QSERDES_COM_RESTRIM_CTRL 0x0bc 65 #define QSERDES_COM_RESTRIM_CTRL2 0x0c0 66 #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 67 #define QSERDES_COM_LOCK_CMP_EN 0x0c8 68 #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 69 #define QSERDES_COM_DEC_START_MODE0 0x0d0 70 #define QSERDES_COM_DEC_START_MODE1 0x0d4 71 #define QSERDES_COM_DEC_START_MODE2 0x0d8 72 #define QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x0d8 73 #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 74 #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 75 #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 76 #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 77 #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 78 #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 79 #define QSERDES_COM_DIV_FRAC_START1_MODE2 0x0f4 80 #define QSERDES_COM_VCO_TUNE_MINVAL1 0x0f4 81 #define QSERDES_COM_DIV_FRAC_START2_MODE2 0x0f8 82 #define QSERDES_COM_VCO_TUNE_MINVAL2 0x0f8 83 #define QSERDES_COM_DIV_FRAC_START3_MODE2 0x0fc 84 #define QSERDES_COM_CMN_RSVD4 0x0fc 85 #define QSERDES_COM_INTEGLOOP_INITVAL 0x100 86 #define QSERDES_COM_INTEGLOOP_EN 0x104 87 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 88 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 89 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 90 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 91 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x118 92 #define QSERDES_COM_VCO_TUNE_MAXVAL1 0x118 93 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x11c 94 #define QSERDES_COM_VCO_TUNE_MAXVAL2 0x11c 95 #define QSERDES_COM_RES_TRIM_CONTROL2 0x120 96 #define QSERDES_COM_VCO_TUNE_CTRL 0x124 97 #define QSERDES_COM_VCO_TUNE_MAP 0x128 98 #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 99 #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 100 #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 101 #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 102 #define QSERDES_COM_VCO_TUNE1_MODE2 0x13c 103 #define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c 104 #define QSERDES_COM_VCO_TUNE2_MODE2 0x140 105 #define QSERDES_COM_VCO_TUNE_INITVAL2 0x140 106 #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 107 #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 108 #define QSERDES_COM_SAR 0x14c 109 #define QSERDES_COM_SAR_CLK 0x150 110 #define QSERDES_COM_SAR_CODE_OUT_STATUS 0x154 111 #define QSERDES_COM_SAR_CODE_READY_STATUS 0x158 112 #define QSERDES_COM_CMN_STATUS 0x15c 113 #define QSERDES_COM_RESET_SM_STATUS 0x160 114 #define QSERDES_COM_RESTRIM_CODE_STATUS 0x164 115 #define QSERDES_COM_PLLCAL_CODE1_STATUS 0x168 116 #define QSERDES_COM_PLLCAL_CODE2_STATUS 0x16c 117 #define QSERDES_COM_BG_CTRL 0x170 118 #define QSERDES_COM_CLK_SELECT 0x174 119 #define QSERDES_COM_HSCLK_SEL 0x178 120 #define QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x17c 121 #define QSERDES_COM_PLL_ANALOG 0x180 122 #define QSERDES_COM_CORECLK_DIV 0x184 123 #define QSERDES_COM_SW_RESET 0x188 124 #define QSERDES_COM_CORE_CLK_EN 0x18c 125 #define QSERDES_COM_C_READY_STATUS 0x190 126 #define QSERDES_COM_CMN_CONFIG 0x194 127 #define QSERDES_COM_CMN_RATE_OVERRIDE 0x198 128 #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 129 #define QSERDES_COM_DEBUG_BUS0 0x1a0 130 #define QSERDES_COM_DEBUG_BUS1 0x1a4 131 #define QSERDES_COM_DEBUG_BUS2 0x1a8 132 #define QSERDES_COM_DEBUG_BUS3 0x1ac 133 #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 134 #define QSERDES_COM_CMN_MISC1 0x1b4 135 #define QSERDES_COM_CMN_MISC2 0x1b8 136 #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 137 #define QSERDES_COM_CORECLK_DIV_MODE2 0x1c0 138 #define QSERDES_COM_CMN_RSVD5 0x1c4 139 140 #endif 141